include/linux/cd1400.h

/* */
   1 /*****************************************************************************/
   2 
   3 /*
   4  *      cd1400.h  -- cd1400 UART hardware info.
   5  *
   6  *      Copyright (C) 1994,1995  Greg Ungerer (gerg@stallion.oz.au).
   7  *
   8  *      This program is free software; you can redistribute it and/or modify
   9  *      it under the terms of the GNU General Public License as published by
  10  *      the Free Software Foundation; either version 2 of the License, or
  11  *      (at your option) any later version.
  12  *
  13  *      This program is distributed in the hope that it will be useful,
  14  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *      GNU General Public License for more details.
  17  *
  18  *      You should have received a copy of the GNU General Public License
  19  *      along with this program; if not, write to the Free Software
  20  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22 
  23 /*****************************************************************************/
  24 
  25 #ifndef _CD1400_H
  26 #define _CD1400_H
  27 /*****************************************************************************/
  28 
  29 /*
  30  *      Define the number of async ports per cd1400 uart chip.
  31  */
  32 #define CD1400_PORTS            4
  33 
  34 #define CD1400_CLKHZ            25000000
  35 
  36 /*
  37  *      Define the cd1400 uarts internal FIFO sizes.
  38  */
  39 #define CD1400_TXFIFOSIZE       12
  40 #define CD1400_RXFIFOSIZE       12
  41 
  42 /*
  43  *      Local RX FIFO thresh hold level. Also define the RTS thresh hold
  44  *      based on the RX thresh hold.
  45  */
  46 #define FIFO_RXTHRESHOLD        6
  47 #define FIFO_RTSTHRESHOLD       7
  48 
  49 /*****************************************************************************/
  50 
  51 /*
  52  *      Define the cd1400 register addresses. These are all the valid
  53  *      registers with the cd1400. Some are global, some virtual, some
  54  *      per port.
  55  */
  56 #define GFRCR           0x40
  57 #define CAR             0x68
  58 #define GCR             0x4b
  59 #define SVRR            0x67
  60 #define RICR            0x44
  61 #define TICR            0x45
  62 #define MICR            0x46
  63 #define RIR             0x6b
  64 #define TIR             0x6a
  65 #define MIR             0x69
  66 #define PPR             0x7e
  67 
  68 #define RIVR            0x43
  69 #define TIVR            0x42
  70 #define MIVR            0x41
  71 #define TDR             0x63
  72 #define RDSR            0x62
  73 #define MISR            0x4c
  74 #define EOSRR           0x60
  75 
  76 #define LIVR            0x18
  77 #define CCR             0x05
  78 #define SRER            0x06
  79 #define COR1            0x08
  80 #define COR2            0x09
  81 #define COR3            0x0a
  82 #define COR4            0x1e
  83 #define COR5            0x1f
  84 #define CCSR            0x0b
  85 #define RDCR            0x0e
  86 #define SCHR1           0x1a
  87 #define SCHR2           0x1b
  88 #define SCHR3           0x1c
  89 #define SCHR4           0x1d
  90 #define SCRL            0x22
  91 #define SCRH            0x23
  92 #define LNC             0x24
  93 #define MCOR1           0x15
  94 #define MCOR2           0x16
  95 #define RTPR            0x21
  96 #define MSVR1           0x6c
  97 #define MSVR2           0x6d
  98 #define PSVR            0x6f
  99 #define RBPR            0x78
 100 #define RCOR            0x7c
 101 #define TBPR            0x72
 102 #define TCOR            0x76
 103 
 104 /*****************************************************************************/
 105 
 106 /*
 107  *      Define the set of baud rate clock divisors.
 108  */
 109 #define CD1400_CLK0     8
 110 #define CD1400_CLK1     32
 111 #define CD1400_CLK2     128
 112 #define CD1400_CLK3     512
 113 #define CD1400_CLK4     2048
 114 
 115 #define CD1400_NUMCLKS  5
 116 
 117 /*****************************************************************************/
 118 
 119 /*
 120  *      Define the clock pre-scalar value to be a 5 ms clock. This should be
 121  *      OK for now. It would probably be better to make it 10 ms, but we
 122  *      can't fit that divisor into 8 bits!
 123  */
 124 #define PPR_SCALAR      244
 125 
 126 /*****************************************************************************/
 127 
 128 /*
 129  *      Define values used to set character size options.
 130  */
 131 #define COR1_CHL5       0x00
 132 #define COR1_CHL6       0x01
 133 #define COR1_CHL7       0x02
 134 #define COR1_CHL8       0x03
 135 
 136 /*
 137  *      Define values used to set the number of stop bits.
 138  */
 139 #define COR1_STOP1      0x00
 140 #define COR1_STOP15     0x04
 141 #define COR1_STOP2      0x08
 142 
 143 /*
 144  *      Define values used to set the parity scheme in use.
 145  */
 146 #define COR1_PARNONE    0x00
 147 #define COR1_PARFORCE   0x20
 148 #define COR1_PARENB     0x40
 149 #define COR1_PARIGNORE  0x10
 150 
 151 #define COR1_PARODD     0x80
 152 #define COR1_PAREVEN    0x00
 153 
 154 #define COR2_IXM        0x80
 155 #define COR2_TXIBE      0x40
 156 #define COR2_ETC        0x20
 157 #define COR2_LLM        0x10
 158 #define COR2_RLM        0x08
 159 #define COR2_RTSAO      0x04
 160 #define COR2_CTSAE      0x02
 161 
 162 #define COR3_SCDRNG     0x80
 163 #define COR3_SCD34      0x40
 164 #define COR3_FCT        0x20
 165 #define COR3_SCD12      0x10
 166 
 167 /*
 168  *      Define values used by COR4.
 169  */
 170 #define COR4_BRKINT     0x08
 171 #define COR4_IGNBRK     0x18
 172 
 173 /*****************************************************************************/
 174 
 175 /*
 176  *      Define the modem control register values.
 177  *      Note that the actual hardware is a little different to the conventional
 178  *      pin names on the cd1400.
 179  */
 180 #define MSVR1_DTR       0x01
 181 #define MSVR1_DSR       0x10
 182 #define MSVR1_RI        0x20
 183 #define MSVR1_CTS       0x40
 184 #define MSVR1_DCD       0x80
 185 
 186 #define MSVR2_RTS       0x02
 187 #define MSVR2_DSR       0x10
 188 #define MSVR2_RI        0x20
 189 #define MSVR2_CTS       0x40
 190 #define MSVR2_DCD       0x80
 191 
 192 #define MCOR1_DCD       0x80
 193 #define MCOR1_CTS       0x40
 194 #define MCOR1_RI        0x20
 195 #define MCOR1_DSR       0x10
 196 
 197 #define MCOR2_DCD       0x80
 198 #define MCOR2_CTS       0x40
 199 #define MCOR2_RI        0x20
 200 #define MCOR2_DSR       0x10
 201 
 202 /*****************************************************************************/
 203 
 204 /*
 205  *      Define the bits used with the service (interrupt) enable register.
 206  */
 207 #define SRER_NNDT       0x01
 208 #define SRER_TXEMPTY    0x02
 209 #define SRER_TXDATA     0x04
 210 #define SRER_RXDATA     0x10
 211 #define SRER_MODEM      0x80
 212 
 213 /*****************************************************************************/
 214 
 215 /*
 216  *      Define operational commands for the command register.
 217  */
 218 #define CCR_RESET       0x80
 219 #define CCR_CORCHANGE   0x4e
 220 #define CCR_SENDCH      0x20
 221 #define CCR_CHANCTRL    0x10
 222 
 223 #define CCR_TXENABLE    (CCR_CHANCTRL | 0x08)
 224 #define CCR_TXDISABLE   (CCR_CHANCTRL | 0x04)
 225 #define CCR_RXENABLE    (CCR_CHANCTRL | 0x02)
 226 #define CCR_RXDISABLE   (CCR_CHANCTRL | 0x01)
 227 
 228 #define CCR_SENDSCHR1   (CCR_SENDCH | 0x01)
 229 #define CCR_SENDSCHR2   (CCR_SENDCH | 0x02)
 230 #define CCR_SENDSCHR3   (CCR_SENDCH | 0x03)
 231 #define CCR_SENDSCHR4   (CCR_SENDCH | 0x04)
 232 
 233 #define CCR_RESETCHAN   (CCR_RESET | 0x00)
 234 #define CCR_RESETFULL   (CCR_RESET | 0x01)
 235 #define CCR_TXFLUSHFIFO (CCR_RESET | 0x02)
 236 
 237 #define CCR_MAXWAIT     10000
 238 
 239 /*****************************************************************************/
 240 
 241 /*
 242  *      Define the valid acknowledgement types (for hw ack cycle).
 243  */
 244 #define ACK_TYPMASK     0x07
 245 #define ACK_TYPTX       0x02
 246 #define ACK_TYPMDM      0x01
 247 #define ACK_TYPRXGOOD   0x03
 248 #define ACK_TYPRXBAD    0x07
 249 
 250 #define SVRR_RX         0x01
 251 #define SVRR_TX         0x02
 252 #define SVRR_MDM        0x04
 253 
 254 #define ST_OVERRUN      0x01
 255 #define ST_FRAMING      0x02
 256 #define ST_PARITY       0x04
 257 #define ST_BREAK        0x08
 258 #define ST_SCHAR1       0x10
 259 #define ST_SCHAR2       0x20
 260 #define ST_SCHAR3       0x30
 261 #define ST_SCHAR4       0x40
 262 #define ST_RANGE        0x70
 263 #define ST_TIMEOUT      0x80
 264 
 265 #define MISR_DCD        0x80
 266 #define MISR_CTS        0x40
 267 #define MISR_RI         0x20
 268 #define MISR_DSR        0x10
 269 
 270 /*****************************************************************************/
 271 
 272 /*
 273  *      Defines for the CCSR status register.
 274  */
 275 #define CCSR_RXENABLED  0x80
 276 #define CCSR_RXFLOWON   0x40
 277 #define CCSR_RXFLOWOFF  0x20
 278 #define CCSR_TXENABLED  0x08
 279 #define CCSR_TXFLOWON   0x04
 280 #define CCSR_TXFLOWOFF  0x02
 281 
 282 /*****************************************************************************/
 283 
 284 /*
 285  *      Define the embedded commands.
 286  */
 287 #define ETC_CMD         0x00
 288 #define ETC_STARTBREAK  0x81
 289 #define ETC_DELAY       0x82
 290 #define ETC_STOPBREAK   0x83
 291 
 292 /*****************************************************************************/
 293 #endif
/* */
root/include/linux/cd1400.h

INCLUDED FROM
