drivers/net/eth16i.c

/* */
This source file includes following definitions.
eth16i_probe
eth16i_probe1
eth16i_initialize
eth16i_probe_port
eth16i_set_port
eth16i_send_probe_packet
eth16i_receive_probe_packet
eth16i_get_irq
eth16i_check_signature
eth16i_read_eeprom
eth16i_read_eeprom_word
eth16i_eeprom_cmd
eth16i_open
eth16i_close
eth16i_tx
eth16i_rx
eth16i_interrupt
eth16i_multicast
eth16i_get_stats
eth16i_select_regbank
init_module
cleanup_module
   1 /* eth16i.c An ICL EtherTeam 16i/32 ethernet driver for Linux
   2 
   3    Written 1994-95 by Mika Kuoppala
   4 
   5    Copyright (C) 1994, 1995 by Mika Kuoppala
   6    Based on skeleton.c and at1700.c by Donald Becker
   7 
   8    This software may be used and distributed according to the terms
   9    of the GNU Public Licence, incorporated herein by reference.
  10 
  11    The author may be reached as miku@pupu.elt.icl.fi
  12 
  13    Sources:
  14      - skeleton.c  a sample network driver core for linux,
  15        written by Donald Becker <becker@cesdis.gsfc.nasa.gov>
  16      - at1700.c a driver for Allied Telesis AT1700, written 
  17        by Donald Becker.
  18      - e16iSRV.asm a Netware 3.X Server Driver for ICL EtherTeam16i
  19        written by Markku Viima
  20      - The Fujitsu MB86965 databook.
  21    
  22    Valuable assistance from:
  23         Markku Viima (ICL) 
  24         Ari Valve (ICL)
  25    
  26    Revision history:
  27 
  28    Version      Date            Description
  29    
  30    0.01         15.12-94        Initial version (card detection)
  31    0.02         23.01-95        Interrupt is now hooked correctly
  32    0.03         01.02-95        Rewrote initialization part
  33    0.04         07.02-95        Base skeleton done...
  34                                 Made a few changes to signature checking
  35                                 to make it a bit reliable.
  36                                 - fixed bug in tx_buf mapping
  37                                 - fixed bug in initialization (DLC_EN
  38                                   wasn't enabled when initialization
  39                                   was done.)
  40    0.05         08.02-95        If there were more than one packet to send,
  41                                 transmit was jammed due to invalid
  42                                 register write...now fixed
  43    0.06         19.02-95        Rewrote interrupt handling        
  44    0.07         13.04-95        Wrote EEPROM read routines
  45                                 Card configuration now set according to
  46                                 data read from EEPROM
  47    0.08         23.06-95        Wrote part that tries to probe used interface
  48                                 port if AUTO is selected
  49 
  50    0.09         01.09-95        Added module support
  51    
  52    0.10         04.09-95        Fixed receive packet allocation to work         
  53                                 with kernels > 1.3.x
  54    
  55    0.20         20.09-95        Added support for EtherTeam32 EISA      
  56 
  57    0.21         17.10-95        Removed the unnecessary extern 
  58                                 init_etherdev() declaration. Some
  59                                 other cleanups.
  60    Bugs:
  61         In some cases the interface autoprobing code doesn't find 
  62         the correct interface type. In this case you can 
  63         manually choose the interface type in DOS with E16IC.EXE which is 
  64         configuration software for EtherTeam16i and EtherTeam32 cards.
  65         
  66    To do:
  67         - Real multicast support
  68 */
  69 
  70 static char *version = 
  71         "eth16i.c: v0.21 17-10-95 Mika Kuoppala (miku@pupu.elt.icl.fi)\n";
  72 
  73 #include <linux/module.h>
  74 
  75 #include <linux/kernel.h>
  76 #include <linux/sched.h>
  77 #include <linux/types.h>                  
  78 #include <linux/fcntl.h>                  
  79 #include <linux/interrupt.h>              
  80 #include <linux/ptrace.h>                 
  81 #include <linux/ioport.h>                 
  82 #include <linux/in.h>             
  83 #include <linux/malloc.h>                 
  84 #include <linux/string.h>                 
  85 #include <linux/errno.h>
  86 
  87 #include <linux/netdevice.h>
  88 #include <linux/etherdevice.h>
  89 #include <linux/skbuff.h>
  90 
  91 #include <asm/system.h>           
  92 #include <asm/bitops.h>           
  93 #include <asm/io.h>               
  94 #include <asm/dma.h>
  95 
  96 /* Few macros */
  97 #define BIT(a)                  ( (1 << (a)) )  
  98 #define BITSET(ioaddr, bnum)   ((outb(((inb(ioaddr)) | (bnum)), ioaddr))) 
  99 #define BITCLR(ioaddr, bnum)   ((outb(((inb(ioaddr)) & (~(bnum))), ioaddr)))
 100 
 101 /* This is the I/O address space for Etherteam 16i adapter. */
 102 #define ETH16I_IO_EXTENT 32
 103 
 104 /* Ticks before deciding that transmit has timed out */
 105 #define TIMEOUT_TICKS          30
 106 
 107 /* Maximum loop count when receiving packets */
 108 #define MAX_RX_LOOP            40
 109 
 110 /* Some interrupt masks */
 111 #define ETH16I_INTR_ON         0x8f82
 112 #define ETH16I_INTR_OFF        0x0000
 113          
 114 /* Buffers header status byte meanings */
 115 #define PKT_GOOD               BIT(5)
 116 #define PKT_GOOD_RMT           BIT(4)
 117 #define PKT_SHORT              BIT(3)
 118 #define PKT_ALIGN_ERR          BIT(2)
 119 #define PKT_CRC_ERR            BIT(1)
 120 #define PKT_RX_BUF_OVERFLOW    BIT(0)
 121 
 122 /* Transmit status register (DLCR0) */
 123 #define TX_STATUS_REG          0
 124 #define TX_DONE                BIT(7)
 125 #define NET_BUSY               BIT(6)
 126 #define TX_PKT_RCD             BIT(5)
 127 #define CR_LOST                BIT(4)
 128 #define COLLISION              BIT(2)
 129 #define COLLISIONS_16          BIT(1)
 130 
 131 /* Receive status register (DLCR1) */
 132 #define RX_STATUS_REG          1
 133 #define RX_PKT                 BIT(7)  /* Packet received */
 134 #define BUS_RD_ERR             BIT(6)
 135 #define SHORT_PKT_ERR          BIT(3)
 136 #define ALIGN_ERR              BIT(2)
 137 #define CRC_ERR                BIT(1)
 138 #define RX_BUF_OVERFLOW        BIT(0)
 139               
 140 /* Transmit Interrupt Enable Register (DLCR2) */
 141 #define TX_INTR_REG            2
 142 #define TX_INTR_DONE           BIT(7)
 143 #define TX_INTR_COL            BIT(2)
 144 #define TX_INTR_16_COL         BIT(1)
 145 
 146 /* Receive Interrupt Enable Register (DLCR3) */
 147 #define RX_INTR_REG            3
 148 #define RX_INTR_RECEIVE        BIT(7)
 149 #define RX_INTR_SHORT_PKT      BIT(3)
 150 #define RX_INTR_CRC_ERR        BIT(1)
 151 #define RX_INTR_BUF_OVERFLOW   BIT(0)
 152 
 153 /* Transmit Mode Register (DLCR4) */
 154 #define TRANSMIT_MODE_REG      4
 155 #define LOOPBACK_CONTROL       BIT(1)
 156 #define CONTROL_OUTPUT         BIT(2)
 157 
 158 /* Receive Mode Register (DLCR5) */
 159 #define RECEIVE_MODE_REG       5
 160 #define RX_BUFFER_EMPTY        BIT(6)
 161 #define ACCEPT_BAD_PACKETS     BIT(5)
 162 #define RECEIVE_SHORT_ADDR     BIT(4)
 163 #define ACCEPT_SHORT_PACKETS   BIT(3)
 164 #define REMOTE_RESET           BIT(2)
 165 
 166 #define ADDRESS_FILTER_MODE    BIT(1) | BIT(0)
 167 #define REJECT_ALL             0
 168 #define ACCEPT_ALL             3
 169 #define MODE_1                 1            /* NODE ID, BC, MC, 2-24th bit */
 170 #define MODE_2                 2            /* NODE ID, BC, MC, Hash Table */
 171 
 172 /* Configuration Register 0 (DLCR6) */
 173 #define CONFIG_REG_0           6
 174 #define DLC_EN                 BIT(7)
 175 #define SRAM_CYCLE_TIME_100NS  BIT(6)
 176 #define SYSTEM_BUS_WIDTH_8     BIT(5)       /* 1 = 8bit, 0 = 16bit */
 177 #define BUFFER_WIDTH_8         BIT(4)       /* 1 = 8bit, 0 = 16bit */
 178 #define TBS1                   BIT(3)       
 179 #define TBS0                   BIT(2)
 180 #define BS1                    BIT(1)       /* 00=8kb,  01=16kb  */
 181 #define BS0                    BIT(0)       /* 10=32kb, 11=64kb  */
 182 
 183 #ifndef ETH16I_TX_BUF_SIZE                   /* 0 = 2kb, 1 = 4kb  */ 
 184 #define ETH16I_TX_BUF_SIZE     2             /* 2 = 8kb, 3 = 16kb */
 185 #endif                                      
 186 #define TX_BUF_1x2048            0
 187 #define TX_BUF_2x2048            1
 188 #define TX_BUF_2x4098            2
 189 #define TX_BUF_2x8192            3
 190 
 191 /* Configuration Register 1 (DLCR7) */
 192 #define CONFIG_REG_1           7
 193 #define POWERUP                BIT(5)
 194 
 195 /* Transmit start register */
 196 #define TRANSMIT_START_REG     10
 197 #define TRANSMIT_START_RB      2
 198 #define TX_START               BIT(7)       /* Rest of register bit indicate*/
 199                                             /* number of packets in tx buffer*/
 200 /* Node ID registers (DLCR8-13) */
 201 #define NODE_ID_0              8
 202 #define NODE_ID_RB             0
 203 
 204 /* Hash Table registers (HT8-15) */
 205 #define HASH_TABLE_0           8
 206 #define HASH_TABLE_RB          1
 207 
 208 /* Buffer memory ports */
 209 #define BUFFER_MEM_PORT_LB    8
 210 #define DATAPORT              BUFFER_MEM_PORT_LB
 211 #define BUFFER_MEM_PORT_HB    9
 212 
 213 /* 16 Collision control register (BMPR11) */
 214 #define COL_16_REG             11
 215 #define HALT_ON_16             0x00
 216 #define RETRANS_AND_HALT_ON_16 0x02
 217 
 218 /* DMA Burst and Transceiver Mode Register (BMPR13) */
 219 #define TRANSCEIVER_MODE_REG   13
 220 #define TRANSCEIVER_MODE_RB    2         
 221 #define IO_BASE_UNLOCK         BIT(7)
 222 #define LOWER_SQUELCH_TRESH    BIT(6)
 223 #define LINK_TEST_DISABLE      BIT(5)
 224 #define AUI_SELECT             BIT(4)
 225 #define DIS_AUTO_PORT_SEL      BIT(3)
 226 
 227 /* Filter Self Receive Register (BMPR14)  */
 228 #define FILTER_SELF_RX_REG     14
 229 #define SKIP_RECEIVE_PACKET    BIT(2)
 230 #define FILTER_SELF_RECEIVE    BIT(0)
 231 #define RX_BUF_SKIP_PACKET     SKIP_RECEIVE_PACKET | FILTER_SELF_RECEIVE
 232 
 233 /* EEPROM Control Register (BMPR 16) */
 234 #define EEPROM_CTRL_REG        16
 235 
 236 /* EEPROM Data Register (BMPR 17) */
 237 #define EEPROM_DATA_REG        17
 238 
 239 /* NMC93CSx6 EEPROM Control Bits */
 240 #define CS_0                   0x00
 241 #define CS_1                   0x20
 242 #define SK_0                   0x00
 243 #define SK_1                   0x40
 244 #define DI_0                   0x00
 245 #define DI_1                   0x80
 246 
 247 /* NMC93CSx6 EEPROM Instructions */
 248 #define EEPROM_READ            0x80
 249 
 250 /* NMC93CSx6 EEPROM Addresses */
 251 #define E_NODEID_0                     0x02
 252 #define E_NODEID_1                     0x03
 253 #define E_NODEID_2                     0x04
 254 #define E_PORT_SELECT                  0x14
 255   #define E_PORT_BNC                   0
 256   #define E_PORT_DIX                   1
 257   #define E_PORT_TP                    2
 258   #define E_PORT_AUTO                  3
 259 #define E_PRODUCT_CFG                  0x30
 260  
 261 
 262 /* Macro to slow down io between EEPROM clock transitions */
 263 #define eeprom_slow_io() do { int _i = 40; while(--_i > 0) { __SLOW_DOWN_IO; }}while(0)
 264 
 265 /* Jumperless Configuration Register (BMPR19) */
 266 #define JUMPERLESS_CONFIG      19
 267 
 268 /* ID ROM registers, writing to them also resets some parts of chip */
 269 #define ID_ROM_0               24
 270 #define ID_ROM_7               31
 271 #define RESET                  ID_ROM_0
 272 
 273 /* This is the I/O address list to be probed when seeking the card */
 274 static unsigned int eth16i_portlist[] =
 275    { 0x260, 0x280, 0x2A0, 0x240, 0x340, 0x320, 0x380, 0x300, 0 };
 276 
 277 static unsigned int eth32i_portlist[] =
 278    { 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7000, 0x8000,
 279      0x9000, 0xA000, 0xB000, 0xC000, 0xD000, 0xE000, 0xF000, 0 };
 280 
 281 /* This is the Interrupt lookup table for Eth16i card */
 282 static unsigned int eth16i_irqmap[] = { 9, 10, 5, 15 };
 283 
 284 /* This is the Interrupt lookup table for Eth32i card */
 285 static unsigned int eth32i_irqmap[] = { 3, 5, 7, 9, 10, 11, 12, 15 };  
 286 #define EISA_IRQ_REG    0xc89
 287 
 288 static unsigned int eth16i_tx_buf_map[] = { 2048, 2048, 4096, 8192 };
 289 unsigned int boot = 1;
 290 
 291 /* Use 0 for production, 1 for verification, >2 for debug */
 292 #ifndef ETH16I_DEBUG
 293 #define ETH16I_DEBUG 0
 294 #endif
 295 static unsigned int eth16i_debug = ETH16I_DEBUG;
 296 
 297 /* Information for each board */
 298 struct eth16i_local {
 299   struct enet_statistics stats;
 300   unsigned int tx_started:1;
 301   unsigned char tx_queue;         /* Number of packets in transmit buffer */
 302   unsigned short tx_queue_len;         
 303   unsigned int tx_buf_size;
 304   unsigned long open_time;
 305 };
 306 
 307 /* Function prototypes */
 308 
 309 extern int eth16i_probe(struct device *dev);
 310 
 311 static int eth16i_probe1(struct device *dev, short ioaddr);
 312 static int eth16i_check_signature(short ioaddr);
 313 static int eth16i_probe_port(short ioaddr);
 314 static void eth16i_set_port(short ioaddr, int porttype);
 315 static int eth16i_send_probe_packet(short ioaddr, unsigned char *b, int l);
 316 static int eth16i_receive_probe_packet(short ioaddr);
 317 static int eth16i_get_irq(short ioaddr);
 318 static int eth16i_read_eeprom(int ioaddr, int offset);
 319 static int eth16i_read_eeprom_word(int ioaddr);
 320 static void eth16i_eeprom_cmd(int ioaddr, unsigned char command);
 321 static int eth16i_open(struct device *dev);
 322 static int eth16i_close(struct device *dev);
 323 static int eth16i_tx(struct sk_buff *skb, struct device *dev);
 324 static void eth16i_rx(struct device *dev);
 325 static void eth16i_interrupt(int irq, struct pt_regs *regs);
 326 static void eth16i_multicast(struct device *dev, int num_addrs, void *addrs); 
 327 static void eth16i_select_regbank(unsigned char regbank, short ioaddr);
 328 static void eth16i_initialize(struct device *dev);
 329 static struct enet_statistics *eth16i_get_stats(struct device *dev);
 330 
 331 static char *cardname = "ICL EtherTeam 16i/32";
 332 
 333 #ifdef HAVE_DEVLIST 
 334 /* Support for alternate probe manager */
 335 /struct netdev_entry eth16i_drv = 
 336    {"eth16i", eth16i_probe1, ETH16I_IO_EXTENT, eth16i_probe_list}; 
 337 
 338 #else  /* Not HAVE_DEVLIST */
 339 int eth16i_probe(struct device *dev)
     /*  */
 340 {
 341   int i;
 342   int ioaddr;
 343   int base_addr = dev ? dev->base_addr : 0;
 344 
 345   if(eth16i_debug > 4) 
 346     printk("Probing started for %s\n", cardname);
 347 
 348   if(base_addr > 0x1ff)           /* Check only single location */
 349     return eth16i_probe1(dev, base_addr);
 350   else if(base_addr != 0)         /* Don't probe at all */
 351     return ENXIO;
 352 
 353   /* Seek card from the ISA io address space */
 354   for(i = 0; (ioaddr = eth16i_portlist[i]) ; i++) {
 355     if(check_region(ioaddr, ETH16I_IO_EXTENT))
 356       continue;
 357     if(eth16i_probe1(dev, ioaddr) == 0)
 358       return 0;
 359   }
 360 
 361   /* Seek card from the EISA io address space */
 362   for(i = 0; (ioaddr = eth32i_portlist[i]) ; i++) {
 363     if(check_region(ioaddr, ETH16I_IO_EXTENT))
 364         continue;
 365     if(eth16i_probe1(dev, ioaddr) == 0)
 366         return 0;
 367    }
 368 
 369   return ENODEV;
 370 }
 371 #endif  /* Not HAVE_DEVLIST */
 372 
 373 static int eth16i_probe1(struct device *dev, short ioaddr)
     /*  */
 374 {
 375   static unsigned version_printed = 0;
 376   unsigned int irq = 0;
 377   boot = 1;          /* To inform initilization that we are in boot probe */
 378 
 379   /*
 380      The MB86985 chip has on register which holds information in which 
 381      io address the chip lies. First read this register and compare
 382      it to our current io address and if match then this could
 383      be our chip.
 384   */
 385   
 386   if(ioaddr < 0x1000) {
 387     if(eth16i_portlist[(inb(ioaddr + JUMPERLESS_CONFIG) & 0x07)] != ioaddr)
 388       return -ENODEV;
 389   }
 390 
 391   /* Now we will go a bit deeper and try to find the chip's signature */
 392 
 393   if(eth16i_check_signature(ioaddr) != 0) /* Can we find the signature here */
 394     return -ENODEV;
 395   
 396   /* 
 397      Now it seems that we have found a ethernet chip in this particular
 398      ioaddr. The MB86985 chip has this feature, that when you read a 
 399      certain register it will increase it's io base address to next
 400      configurable slot. Now when we have found the chip, first thing is
 401      to make sure that the chip's ioaddr will hold still here.
 402   */
 403   
 404   eth16i_select_regbank(TRANSCEIVER_MODE_RB, ioaddr);
 405   outb(0x00, ioaddr + TRANSCEIVER_MODE_REG);
 406   
 407   outb(0x00, ioaddr + RESET);             /* Will reset some parts of chip */
 408   BITSET(ioaddr + CONFIG_REG_0, BIT(7));  /* This will disable the data link */
 409   
 410   if(dev == NULL)
 411     dev = init_etherdev(0, sizeof(struct eth16i_local));
 412 
 413   if( (eth16i_debug & version_printed++) == 0)
 414     printk(version);
 415 
 416   dev->base_addr = ioaddr;
 417  
 418   irq = eth16i_get_irq(ioaddr);
 419   dev->irq = irq;
 420 
 421   /* Try to obtain interrupt vector */
 422   if(request_irq(dev->irq, &eth16i_interrupt, 0, "eth16i")) {
 423     printk("%s: %s at %#3x, but is unusable due 
 424            conflict on IRQ %d.\n", dev->name, cardname, ioaddr, irq);
 425     return EAGAIN;
 426   }
 427 
 428   printk("%s: %s at %#3x, IRQ %d, ", 
 429          dev->name, cardname, ioaddr, dev->irq);
 430 
 431   /* Let's grab the region */
 432   request_region(ioaddr, ETH16I_IO_EXTENT, "eth16i");
 433 
 434   /* Now we will have to lock the chip's io address */
 435   eth16i_select_regbank(TRANSCEIVER_MODE_RB, ioaddr);
 436   outb(0x38, ioaddr + TRANSCEIVER_MODE_REG); 
 437 
 438   eth16i_initialize(dev);   /* Initialize rest of the chip's registers */
 439   
 440   /* Now let's same some energy by shutting down the chip ;) */
 441   BITCLR(ioaddr + CONFIG_REG_1, POWERUP);
 442    
 443   /* Initialize the device structure */
 444   if(dev->priv == NULL)
 445     dev->priv = kmalloc(sizeof(struct eth16i_local), GFP_KERNEL);
 446   memset(dev->priv, 0, sizeof(struct eth16i_local));
 447 
 448   dev->open               = eth16i_open;
 449   dev->stop               = eth16i_close;
 450   dev->hard_start_xmit    = eth16i_tx;
 451   dev->get_stats          = eth16i_get_stats;
 452   dev->set_multicast_list = &eth16i_multicast;
 453 
 454   /* Fill in the fields of the device structure with ethernet values. */
 455   ether_setup(dev);
 456 
 457   boot = 0;
 458 
 459   return 0;
 460 }
 461 
 462 
 463 static void eth16i_initialize(struct device *dev)
     /*  */
 464 {
 465   short ioaddr = dev->base_addr;
 466   int i, node_w = 0;
 467   unsigned char node_byte = 0;
 468 
 469   /* Setup station address */
 470   eth16i_select_regbank(NODE_ID_RB, ioaddr);
 471   for(i = 0 ; i < 3 ; i++) {
 472     unsigned short node_val = eth16i_read_eeprom(ioaddr, E_NODEID_0 + i);
 473     ((unsigned short *)dev->dev_addr)[i] = ntohs(node_val);
 474   }
 475 
 476   for(i = 0; i < 6; i++) { 
 477     outb( ((unsigned char *)dev->dev_addr)[i], ioaddr + NODE_ID_0 + i);
 478     if(boot) {
 479       printk("%02x", inb(ioaddr + NODE_ID_0 + i));
 480       if(i != 5)
 481         printk(":");
 482     }
 483   }
 484 
 485   /* Now we will set multicast addresses to accept none */
 486   eth16i_select_regbank(HASH_TABLE_RB, ioaddr);
 487   for(i = 0; i < 8; i++) 
 488     outb(0x00, ioaddr + HASH_TABLE_0 + i);
 489 
 490   /*
 491      Now let's disable the transmitter and receiver, set the buffer ram 
 492      cycle time, bus width and buffer data path width. Also we shall
 493      set transmit buffer size and total buffer size.
 494   */
 495 
 496   eth16i_select_regbank(2, ioaddr);
 497 
 498   node_byte = 0;
 499   node_w = eth16i_read_eeprom(ioaddr, E_PRODUCT_CFG);
 500 
 501   if( (node_w & 0xFF00) == 0x0800)
 502     node_byte |= BUFFER_WIDTH_8;
 503 
 504   node_byte |= BS1;
 505 
 506   if( (node_w & 0x00FF) == 64)
 507     node_byte |= BS0;
 508   
 509   node_byte |= DLC_EN | SRAM_CYCLE_TIME_100NS | (ETH16I_TX_BUF_SIZE << 2);
 510 
 511   outb(node_byte, ioaddr + CONFIG_REG_0);
 512 
 513   /* We shall halt the transmitting, if 16 collisions are detected */
 514   outb(RETRANS_AND_HALT_ON_16, ioaddr + COL_16_REG);
 515 
 516   if(boot) /* Now set port type */
 517   {
 518     char *porttype[] = {"BNC", "DIX", "TP", "AUTO"};
 519     
 520     ushort ptype = eth16i_read_eeprom(ioaddr, E_PORT_SELECT);
 521     dev->if_port = (ptype & 0x00FF);
 522     
 523     printk(" %s interface.\n", porttype[dev->if_port]);
 524 
 525     if(ptype == E_PORT_AUTO)
 526       ptype = eth16i_probe_port(ioaddr);
 527     
 528     eth16i_set_port(ioaddr, ptype);
 529   }
 530 
 531   /* Set Receive Mode to normal operation */
 532   outb(MODE_2, ioaddr + RECEIVE_MODE_REG);
 533 }
 534 
 535 static int eth16i_probe_port(short ioaddr)
     /*  */
 536 {
 537   int i;
 538   int retcode;
 539   unsigned char dummy_packet[64] = { 0 };
 540 
 541   /* Powerup the chip */
 542   outb(0xc0 | POWERUP, ioaddr + CONFIG_REG_1);
 543 
 544   BITSET(ioaddr + CONFIG_REG_0, DLC_EN);
 545 
 546   eth16i_select_regbank(NODE_ID_RB, ioaddr);
 547 
 548   for(i = 0; i < 6; i++) {
 549     dummy_packet[i] = inb(ioaddr + NODE_ID_0 + i);
 550     dummy_packet[i+6] = inb(ioaddr + NODE_ID_0 + i);
 551   }
 552 
 553   dummy_packet[12] = 0x00;
 554   dummy_packet[13] = 0x04;
 555 
 556   eth16i_select_regbank(2, ioaddr);
 557 
 558   for(i = 0; i < 3; i++) {
 559     BITSET(ioaddr + CONFIG_REG_0, DLC_EN);
 560     BITCLR(ioaddr + CONFIG_REG_0, DLC_EN);
 561     eth16i_set_port(ioaddr, i);
 562    
 563     if(eth16i_debug > 1)
 564         printk("Set port number %d\n", i);
 565 
 566     retcode = eth16i_send_probe_packet(ioaddr, dummy_packet, 64);
 567     if(retcode == 0) {
 568       retcode = eth16i_receive_probe_packet(ioaddr);
 569       if(retcode != -1) {
 570         if(eth16i_debug > 1)
 571                 printk("Eth16i interface port found at %d\n", i);
 572         return i;
 573       }
 574     }
 575     else {
 576       if(eth16i_debug > 1)
 577         printk("TRANSMIT_DONE timeout\n");
 578     }
 579   }
 580   
 581   if( eth16i_debug > 1)
 582         printk("Using default port\n");
 583  
 584  return E_PORT_BNC;
 585 }
 586 
 587 static void eth16i_set_port(short ioaddr, int porttype)
     /*  */
 588 { 
 589     unsigned short temp = 0;
 590 
 591     eth16i_select_regbank(TRANSCEIVER_MODE_RB, ioaddr);
 592     outb(LOOPBACK_CONTROL, ioaddr + TRANSMIT_MODE_REG);
 593 
 594     temp |= DIS_AUTO_PORT_SEL;
 595 
 596     switch(porttype) {
 597 
 598     case E_PORT_BNC :
 599       temp |= AUI_SELECT;
 600       break;
 601 
 602     case E_PORT_TP :
 603       break;
 604       
 605     case E_PORT_DIX :
 606       temp |= AUI_SELECT;
 607       BITSET(ioaddr + TRANSMIT_MODE_REG, CONTROL_OUTPUT);
 608       break;
 609     }  
 610     outb(temp, ioaddr + TRANSCEIVER_MODE_REG);
 611 
 612     if(eth16i_debug > 1) {
 613         printk("TRANSMIT_MODE_REG = %x\n", inb(ioaddr + TRANSMIT_MODE_REG));
 614         printk("TRANSCEIVER_MODE_REG = %x\n", inb(ioaddr+TRANSCEIVER_MODE_REG));
 615     }
 616 }
 617 
 618 static int eth16i_send_probe_packet(short ioaddr, unsigned char *b, int l)
     /*  */
 619 {
 620   int starttime;
 621 
 622   outb(0xff, ioaddr + TX_STATUS_REG);
 623 
 624   outw(l, ioaddr + DATAPORT);
 625   outsw(ioaddr + DATAPORT, (unsigned short *)b, (l + 1) >> 1);  
 626   
 627   starttime = jiffies;
 628   outb(TX_START | 1, ioaddr + TRANSMIT_START_REG); 
 629 
 630   while( (inb(ioaddr + TX_STATUS_REG) & 0x80) == 0) {
 631     if( (jiffies - starttime) > TIMEOUT_TICKS) {
 632       break;
 633     }
 634   }
 635   
 636   return(0);
 637 }
 638 
 639 static int eth16i_receive_probe_packet(short ioaddr)
     /*  */
 640 {
 641   int starttime;
 642   
 643   starttime = jiffies;
 644   
 645   while((inb(ioaddr + TX_STATUS_REG) & 0x20) == 0) {
 646     if( (jiffies - starttime) > TIMEOUT_TICKS) {
 647       
 648       if(eth16i_debug > 1)
 649         printk("Timeout occured waiting transmit packet received\n");
 650       starttime = jiffies;
 651       while((inb(ioaddr + RX_STATUS_REG) & 0x80) == 0) {
 652         if( (jiffies - starttime) > TIMEOUT_TICKS) {
 653         if(eth16i_debug > 1)
 654           printk("Timeout occured waiting receive packet\n");
 655         return -1;
 656         }
 657       }
 658       
 659       if(eth16i_debug > 1)
 660         printk("RECEIVE_PACKET\n");
 661       return(0); /* Found receive packet */
 662     }
 663   }
 664 
 665   if(eth16i_debug > 1) {
 666         printk("TRANSMIT_PACKET_RECEIVED %x\n", inb(ioaddr + TX_STATUS_REG));
 667         printk("RX_STATUS_REG = %x\n", inb(ioaddr + RX_STATUS_REG));
 668   }
 669 
 670   return(0); /* Return success */
 671 }
 672 
 673 static int eth16i_get_irq(short ioaddr)
     /*  */
 674 {
 675   unsigned char cbyte;
 676   
 677   if( ioaddr < 0x1000) {
 678         cbyte = inb(ioaddr + JUMPERLESS_CONFIG);
 679         return( eth16i_irqmap[ ((cbyte & 0xC0) >> 6) ] );
 680   } else {  /* Oh..the card is EISA so method getting IRQ different */
 681         unsigned short index = 0;
 682         cbyte = inb(ioaddr + EISA_IRQ_REG);
 683         while( (cbyte & 0x01) == 0) {
 684                 cbyte = cbyte >> 1;
 685                 index++;
 686         }
 687         return( eth32i_irqmap[ index ] );
 688   }
 689 }
 690 
 691 static int eth16i_check_signature(short ioaddr)
     /*  */
 692 {
 693   int i;
 694   unsigned char creg[4] = { 0 };
 695   
 696   for(i = 0; i < 4 ; i++) {
 697 
 698     creg[i] = inb(ioaddr + TRANSMIT_MODE_REG + i);
 699   
 700     if(eth16i_debug > 1)
 701         printk("eth16i: read signature byte %x at %x\n", creg[i],
 702                ioaddr + TRANSMIT_MODE_REG + i);
 703   }
 704 
 705   creg[0] &= 0x0F;      /* Mask collision cnr */
 706   creg[2] &= 0x7F;      /* Mask DCLEN bit */
 707 
 708 #ifdef 0
 709 /* 
 710         This was removed because the card was sometimes left to state
 711         from which it couldn't be find anymore. If there is need
 712         to more strict chech still this have to be fixed.
 713 */
 714   if( !( (creg[0] == 0x06) && (creg[1] == 0x41)) ) {
 715     if(creg[1] != 0x42)
 716       return -1;
 717   }
 718 #endif
 719 
 720   if( !( (creg[2] == 0x36) && (creg[3] == 0xE0)) ) {
 721       creg[2] &= 0x42;
 722       creg[3] &= 0x03;
 723 
 724       if( !( (creg[2] == 0x42) && (creg[3] == 0x00)) )
 725         return -1;
 726   }
 727 
 728   if(eth16i_read_eeprom(ioaddr, E_NODEID_0) != 0)
 729     return -1;
 730   if((eth16i_read_eeprom(ioaddr, E_NODEID_1) & 0xFF00) != 0x4B00)
 731     return -1;
 732 
 733   return 0;
 734 }
 735 
 736 static int eth16i_read_eeprom(int ioaddr, int offset)
     /*  */
 737 {
 738   int data = 0;
 739 
 740   eth16i_eeprom_cmd(ioaddr, EEPROM_READ | offset);
 741   outb(CS_1, ioaddr + EEPROM_CTRL_REG);
 742   data = eth16i_read_eeprom_word(ioaddr);
 743   outb(CS_0 | SK_0, ioaddr + EEPROM_CTRL_REG);
 744 
 745   return(data);  
 746 }
 747 
 748 static int eth16i_read_eeprom_word(int ioaddr)
     /*  */
 749 {
 750   int i;
 751   int data = 0;
 752 
 753   for(i = 16; i > 0; i--) {
 754     outb(CS_1 | SK_0, ioaddr + EEPROM_CTRL_REG);
 755     eeprom_slow_io();
 756     outb(CS_1 | SK_1, ioaddr + EEPROM_CTRL_REG);
 757     eeprom_slow_io();
 758     data = (data << 1) | ((inb(ioaddr + EEPROM_DATA_REG) & DI_1) ? 1 : 0);
 759     eeprom_slow_io();
 760   }
 761 
 762   return(data);
 763 }
 764 
 765 static void eth16i_eeprom_cmd(int ioaddr, unsigned char command)
     /*  */
 766 {
 767   int i;
 768   
 769   outb(CS_0 | SK_0, ioaddr + EEPROM_CTRL_REG);
 770   outb(DI_0, ioaddr + EEPROM_DATA_REG);
 771   outb(CS_1 | SK_0, ioaddr + EEPROM_CTRL_REG);
 772   outb(DI_1, ioaddr + EEPROM_DATA_REG);
 773   outb(CS_1 | SK_1, ioaddr + EEPROM_CTRL_REG);
 774 
 775   for(i = 7; i >= 0; i--) {
 776     short cmd = ( (command & (1 << i)) ? DI_1 : DI_0 );
 777     outb(cmd, ioaddr + EEPROM_DATA_REG);
 778     outb(CS_1 | SK_0, ioaddr + EEPROM_CTRL_REG);
 779     eeprom_slow_io();
 780     outb(CS_1 | SK_1, ioaddr + EEPROM_CTRL_REG);
 781     eeprom_slow_io();
 782   } 
 783 }
 784 
 785 static int eth16i_open(struct device *dev)
     /*  */
 786 {
 787   struct eth16i_local *lp = (struct eth16i_local *)dev->priv;
 788   int ioaddr = dev->base_addr;
 789   
 790   irq2dev_map[dev->irq] = dev;
 791 
 792   /* Powerup the chip */
 793   outb(0xc0 | POWERUP, ioaddr + CONFIG_REG_1);
 794   
 795   /* Initialize the chip */
 796   eth16i_initialize(dev);  
 797   
 798   /* Set the transmit buffer size */
 799   lp->tx_buf_size = eth16i_tx_buf_map[ETH16I_TX_BUF_SIZE & 0x03];
 800   
 801   if(eth16i_debug > 3)
 802     printk("%s: transmit buffer size %d\n", dev->name, lp->tx_buf_size);
 803 
 804   /* Now enable Transmitter and Receiver sections */
 805   BITCLR(ioaddr + CONFIG_REG_0, DLC_EN);
 806  
 807   /* Now switch to register bank 2, for run time operation */
 808   eth16i_select_regbank(2, ioaddr);
 809 
 810   lp->open_time = jiffies;
 811   lp->tx_started = 0;
 812   lp->tx_queue = 0;
 813   lp->tx_queue_len = 0;
 814 
 815   /* Turn on interrupts*/
 816   outw(ETH16I_INTR_ON, ioaddr + TX_INTR_REG);  
 817 
 818   dev->tbusy = 0;
 819   dev->interrupt = 0;
 820   dev->start = 1;
 821 
 822 #ifdef MODULE
 823   MOD_INC_USE_COUNT;
 824 #endif
 825 
 826   return 0;
 827 }
 828 
 829 static int eth16i_close(struct device *dev)
     /*  */
 830 {
 831   struct eth16i_local *lp = (struct eth16i_local *)dev->priv;
 832   int ioaddr = dev->base_addr;
 833 
 834   lp->open_time = 0;
 835 
 836   dev->tbusy = 1;
 837   dev->start = 0;
 838 
 839   /* Disable transmit and receive */
 840   BITSET(ioaddr + CONFIG_REG_0, DLC_EN);
 841 
 842   /* Reset the chip */
 843   outb(0xff, ioaddr + RESET);
 844 
 845   /* Save some energy by switching off power */
 846   BITCLR(ioaddr + CONFIG_REG_1, POWERUP);
 847 
 848 #ifdef MODULE
 849   MOD_DEC_USE_COUNT;
 850 #endif
 851 
 852   return 0;
 853 }
 854 
 855 static int eth16i_tx(struct sk_buff *skb, struct device *dev)
     /*  */
 856 {
 857   struct eth16i_local *lp = (struct eth16i_local *)dev->priv;
 858   int ioaddr = dev->base_addr;
 859 
 860   if(dev->tbusy) {
 861     /* 
 862        If we get here, some higher level has decided that we are broken. 
 863        There should really be a "kick me" function call instead. 
 864     */
 865     
 866     int tickssofar = jiffies - dev->trans_start;
 867     if(tickssofar < TIMEOUT_TICKS)  /* Let's not rush with our timeout, */  
 868       return 1;                     /* wait a couple of ticks first     */
 869 
 870     printk("%s: transmit timed out with status %04x, %s ?\n", dev->name,
 871            inw(ioaddr + TX_STATUS_REG), 
 872            (inb(ioaddr + TX_STATUS_REG) & TX_DONE) ? 
 873            "IRQ conflict" : "network cable problem");
 874 
 875     /* Let's dump all registers */
 876     if(eth16i_debug > 0) { 
 877       printk("%s: timeout regs: %02x %02x %02x %02x %02x %02x %02x %02x.\n",
 878              dev->name, inb(ioaddr + 0), inb(ioaddr + 1), inb(ioaddr + 2), 
 879              inb(ioaddr + 3), inb(ioaddr + 4), inb(ioaddr + 5),
 880              inb(ioaddr + 6), inb(ioaddr + 7));
 881 
 882 
 883       printk("lp->tx_queue = %d\n", lp->tx_queue);
 884       printk("lp->tx_queue_len = %d\n", lp->tx_queue_len);
 885       printk("lp->tx_started = %d\n", lp->tx_started);
 886 
 887     }
 888 
 889     lp->stats.tx_errors++;
 890 
 891     /* Now let's try to restart the adaptor */
 892     
 893     BITSET(ioaddr + CONFIG_REG_0, DLC_EN);
 894     outw(0xffff, ioaddr + RESET);
 895     eth16i_initialize(dev);
 896     outw(0xffff, ioaddr + TX_STATUS_REG);
 897     BITCLR(ioaddr + CONFIG_REG_0, DLC_EN);
 898             
 899     lp->tx_started = 0;
 900     lp->tx_queue = 0;
 901     lp->tx_queue_len = 0;
 902     
 903     outw(ETH16I_INTR_ON, ioaddr + TX_INTR_REG);
 904     
 905     dev->tbusy = 0;
 906     dev->trans_start = jiffies;
 907   }
 908 
 909   /* 
 910      If some higher layer thinks we've missed an tx-done interrupt
 911      we are passed NULL. Caution: dev_tint() handles the cli()/sti()
 912      itself 
 913   */
 914   if(skb == NULL) {
 915     dev_tint(dev);
 916     return 0;
 917   }
 918 
 919   /* Block a timer based transmitter from overlapping. This could better be
 920      done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
 921 
 922   /* Turn off TX interrupts */
 923   outw(ETH16I_INTR_OFF, ioaddr + TX_INTR_REG);
 924 
 925   if(set_bit(0, (void *)&dev->tbusy) != 0)
 926     printk("%s: Transmitter access conflict.\n", dev->name);
 927   else {
 928     short length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
 929     unsigned char *buf = skb->data;
 930   
 931     outw(length, ioaddr + DATAPORT);
 932     
 933     if( ioaddr < 0x1000 ) 
 934         outsw(ioaddr + DATAPORT, buf, (length + 1) >> 1);
 935     else {
 936         unsigned char frag = length % 4;
 937 
 938         outsl(ioaddr + DATAPORT, buf, length >> 2);
 939         
 940         if( frag != 0 ) {
 941           outsw(ioaddr + DATAPORT, (buf + (length & 0xFFFC)), 1);
 942           if( frag == 3 ) 
 943             outsw(ioaddr + DATAPORT, (buf + (length & 0xFFFC) + 2), 1);
 944         }
 945     }
 946 
 947     lp->tx_queue++;
 948     lp->tx_queue_len += length + 2;
 949 
 950     if(lp->tx_started == 0) {
 951       /* If the transmitter is idle..always trigger a transmit */
 952       outb(TX_START | lp->tx_queue, ioaddr + TRANSMIT_START_REG);
 953       lp->tx_queue = 0;
 954       lp->tx_queue_len = 0;
 955       dev->trans_start = jiffies;
 956       lp->tx_started = 1;
 957       dev->tbusy = 0;
 958     }
 959     else if(lp->tx_queue_len < lp->tx_buf_size - (ETH_FRAME_LEN + 2)) {
 960       /* There is still more room for one more packet in tx buffer */
 961       dev->tbusy = 0;
 962     }
 963         
 964     outw(ETH16I_INTR_ON, ioaddr + TX_INTR_REG);
 965 
 966     /* Turn TX interrupts back on */
 967     /* outb(TX_INTR_DONE | TX_INTR_16_COL, ioaddr + TX_INTR_REG); */
 968   } 
 969   dev_kfree_skb(skb, FREE_WRITE);
 970 
 971   return 0;
 972 }
 973 
 974 static void eth16i_rx(struct device *dev)
     /*  */
 975 {
 976   struct eth16i_local *lp = (struct eth16i_local *)dev->priv;
 977   int ioaddr = dev->base_addr;
 978   int boguscount = MAX_RX_LOOP;
 979 
 980   /* Loop until all packets have been read */
 981   while( (inb(ioaddr + RECEIVE_MODE_REG) & RX_BUFFER_EMPTY) == 0) {
 982     
 983     /* Read status byte from receive buffer */ 
 984     ushort status = inw(ioaddr + DATAPORT);
 985 
 986     if(eth16i_debug > 4)
 987       printk("%s: Receiving packet mode %02x status %04x.\n", 
 988              dev->name, inb(ioaddr + RECEIVE_MODE_REG), status);
 989   
 990       if( !(status & PKT_GOOD) ) {
 991         /* Hmm..something went wrong. Let's check what error occured */
 992         lp->stats.rx_errors++;
 993         if( status & PKT_SHORT     ) lp->stats.rx_length_errors++;
 994         if( status & PKT_ALIGN_ERR ) lp->stats.rx_frame_errors++;
 995         if( status & PKT_CRC_ERR   ) lp->stats.rx_crc_errors++;
 996         if( status & PKT_RX_BUF_OVERFLOW) lp->stats.rx_over_errors++;
 997       }
 998       else {   /* Ok so now we should have a good packet */
 999         struct sk_buff *skb;
1000 
1001         /* Get the size of the packet from receive buffer */
1002         ushort pkt_len = inw(ioaddr + DATAPORT);
1003 
1004         if(pkt_len > ETH_FRAME_LEN) {
1005           printk("%s: %s claimed a very large packet, size of %d bytes.\n", 
1006                  dev->name, cardname, pkt_len);
1007           outb(RX_BUF_SKIP_PACKET, ioaddr + FILTER_SELF_RX_REG);
1008           lp->stats.rx_dropped++;
1009           break;
1010         }
1011 
1012         skb = dev_alloc_skb(pkt_len + 3);
1013         if( skb == NULL ) {
1014           printk("%s: Could'n allocate memory for packet (len %d)\n", 
1015                  dev->name, pkt_len);
1016           outb(RX_BUF_SKIP_PACKET, ioaddr + FILTER_SELF_RX_REG);
1017           lp->stats.rx_dropped++;
1018           break;
1019         }
1020         
1021         skb->dev = dev;
1022         skb_reserve(skb,2);
1023         /* 
1024            Now let's get the packet out of buffer.
1025            size is (pkt_len + 1) >> 1, cause we are now reading words
1026            and it have to be even aligned.
1027         */ 
1028 
1029         if( ioaddr < 0x1000) 
1030           insw(ioaddr + DATAPORT, skb_put(skb, pkt_len), (pkt_len + 1) >> 1);
1031         else {  
1032           unsigned char *buf = skb_put(skb, pkt_len);
1033           unsigned char frag = pkt_len % 4;
1034 
1035           insl(ioaddr + DATAPORT, buf, pkt_len >> 2);
1036         
1037           if(frag != 0) {
1038                 unsigned short rest[2];
1039                 rest[0] = inw( ioaddr + DATAPORT );
1040                 if(frag == 3)
1041                         rest[1] = inw( ioaddr + DATAPORT );
1042 
1043                 memcpy(buf + (pkt_len & 0xfffc), (char *)rest, frag);
1044           }
1045         }
1046         
1047         skb->protocol=eth_type_trans(skb, dev);
1048         netif_rx(skb);
1049         lp->stats.rx_packets++;
1050          
1051         if( eth16i_debug > 5 ) {
1052           int i;
1053           printk("%s: Received packet of length %d.\n", dev->name, pkt_len);
1054           for(i = 0; i < 14; i++) 
1055             printk(" %02x", skb->data[i]);
1056           printk(".\n");
1057         }
1058         
1059       } /* else */
1060 
1061     if(--boguscount <= 0)
1062       break;
1063 
1064   } /* while */
1065 
1066 #if 0
1067   {
1068     int i;
1069 
1070     for(i = 0; i < 20; i++) {
1071       if( (inb(ioaddr+RECEIVE_MODE_REG) & RX_BUFFER_EMPTY) == RX_BUFFER_EMPTY)
1072         break;
1073       inw(ioaddr + DATAPORT);
1074       outb(RX_BUF_SKIP_PACKET, ioaddr + FILTER_SELF_RX_REG);
1075     }
1076 
1077     if(eth16i_debug > 1)
1078       printk("%s: Flushed receive buffer.\n", dev->name);
1079   }
1080 #endif
1081 
1082   return;
1083 }
1084 
1085 static void eth16i_interrupt(int irq, struct pt_regs *regs)
     /*  */
1086 {
1087   struct device *dev = (struct device *)(irq2dev_map[irq]);
1088   struct eth16i_local *lp;
1089   int ioaddr = 0,
1090       status;
1091 
1092   if(dev == NULL) {
1093     printk("eth16i_interrupt(): irq %d for unknown device. \n", irq);
1094     return;
1095   }
1096 
1097   /* Turn off all interrupts from adapter */
1098   outw(ETH16I_INTR_OFF, ioaddr + TX_INTR_REG); 
1099 
1100   dev->interrupt = 1;
1101 
1102   ioaddr = dev->base_addr;
1103   lp = (struct eth16i_local *)dev->priv;
1104   status = inw(ioaddr + TX_STATUS_REG);      /* Get the status */
1105   outw(status, ioaddr + TX_STATUS_REG);      /* Clear status bits */
1106   
1107   if(eth16i_debug > 3)
1108     printk("%s: Interrupt with status %04x.\n", dev->name, status);
1109 
1110   if( status & 0x00ff ) {          /* Let's check the transmit status reg */
1111     
1112     if(status & TX_DONE) {         /* The transmit has been done */
1113       lp->stats.tx_packets++;
1114 
1115       if(lp->tx_queue) {           /* Is there still packets ? */
1116           /* There was packet(s) so start transmitting and write also
1117            how many packets there is to be sended */
1118         outb(TX_START | lp->tx_queue, ioaddr + TRANSMIT_START_REG);
1119         lp->tx_queue = 0;
1120         lp->tx_queue_len = 0;
1121         dev->trans_start = jiffies;
1122         dev->tbusy = 0;
1123         mark_bh(NET_BH);
1124       }
1125       else {
1126         lp->tx_started = 0;
1127         dev->tbusy = 0;
1128         mark_bh(NET_BH);
1129       }
1130     }
1131   }
1132     
1133   if( ( status & 0xff00 ) || 
1134      ( (inb(ioaddr + RECEIVE_MODE_REG) & RX_BUFFER_EMPTY) == 0) ) {
1135     eth16i_rx(dev);  /* We have packet in receive buffer */
1136   }
1137 
1138   dev->interrupt = 0;
1139   
1140   /* Turn interrupts back on */
1141   outw(ETH16I_INTR_ON, ioaddr + TX_INTR_REG);
1142 
1143   return;
1144 }
1145 
1146 static void eth16i_multicast(struct device *dev, int num_addrs, void *addrs)
     /*  */
1147 {
1148   short ioaddr = dev->base_addr;
1149   
1150   if(num_addrs) {
1151     outb(3, ioaddr + RECEIVE_MODE_REG);    
1152   } else {
1153     outb(2, ioaddr + RECEIVE_MODE_REG);
1154   }
1155 }
1156 
1157 static struct enet_statistics *eth16i_get_stats(struct device *dev)
     /*  */
1158 {
1159   struct eth16i_local *lp = (struct eth16i_local *)dev->priv;
1160 
1161   return &lp->stats;
1162 }
1163 
1164 static void eth16i_select_regbank(unsigned char banknbr, short ioaddr)
     /*  */
1165 {
1166   unsigned char data;
1167 
1168   data = inb(ioaddr + CONFIG_REG_1);
1169   outb( ((data & 0xF3) | ( (banknbr & 0x03) << 2)), ioaddr + CONFIG_REG_1); 
1170 }
1171 
1172 #ifdef MODULE
1173 static char devicename[9] = { 0, };
1174 static struct device dev_eth16i = {
1175         devicename,
1176         0, 0, 0, 0,
1177         0, 0,
1178         0, 0, 0, NULL, eth16i_probe };
1179 
1180 int io = 0x2a0;
1181 int irq = 0;
1182 
1183 int init_module(void)
     /*  */
1184 {
1185         if(io == 0)
1186                 printk("eth16i: You should not use auto-probing with insmod!\n");
1187         
1188         dev_eth16i.base_addr = io;
1189         dev_eth16i.irq = irq;
1190         if( register_netdev( &dev_eth16i ) != 0 ) {
1191                 printk("eth16i: register_netdev() returned non-zero.\n");
1192                 return -EIO;
1193         }
1194 
1195         return 0;
1196 }
1197 
1198 void cleanup_module(void)
     /*  */
1199 {
1200         if (MOD_IN_USE)
1201                 printk("eth16i: Device busy, remove delayed\n");
1202         else
1203         {
1204                 unregister_netdev( &dev_eth16i );
1205 
1206                 free_irq( dev_eth16i.irq );
1207                 irq2dev_map[ dev_eth16i.irq ] = NULL;
1208                 release_region( dev_eth16i.base_addr, ETH16I_IO_EXTENT );
1209         }
1210 }
1211 
1212 #endif /* MODULE */
1213 
1214
/* */
root/drivers/net/eth16i.c

DEFINITIONS
