root/drivers/scsi/53c7,8xx.h

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   1 /*
   2  * NCR 53c{7,8}0x0 driver, header file
   3  *
   4  * Sponsored by
   5  *      iX Multiuser Multitasking Magazine
   6  *      Hannover, Germany
   7  *      hm@ix.de        
   8  *
   9  * Copyright 1993, Drew Eckhardt
  10  *      Visionary Computing 
  11  *      (Unix and Linux consulting and custom programming)
  12  *      drew@Colorado.EDU
  13  *      +1 (303) 786-7975
  14  *
  15  * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
  16  * 
  17  * PRE-ALPHA
  18  *
  19  * For more information, please consult 
  20  *
  21  * NCR 53C700/53C700-66
  22  * SCSI I/O Processor
  23  * Data Manual
  24  *
  25  * NCR 53C810
  26  * PCI-SCSI I/O Processor 
  27  * Data Manual
  28  *
  29  * NCR Microelectronics
  30  * 1635 Aeroplaza Drive
  31  * Colorado Springs, CO 80916
  32  * +1 (719) 578-3400
  33  *
  34  * Toll free literature number
  35  * +1 (800) 334-5454
  36  *
  37  */
  38 
  39 #ifndef NCR53c7x0_H
  40 #define NCR53c7x0_H
  41 
  42 #ifdef __alpha__
  43 
  44 # define ncr_readb(a)           ((unsigned int)readb((unsigned long)(a)))
  45 # define ncr_readw(a)           ((unsigned int)readw((unsigned long)(a)))
  46 # define ncr_readl(a)           ((unsigned int)readl((unsigned long)(a)))
  47 # define ncr_writeb(v,a)        (writeb((v), (unsigned long)(a)))
  48 # define ncr_writew(v,a)        (writew((v), (unsigned long)(a)))
  49 # define ncr_writel(v,a)        (writel((v), (unsigned long)(a)))
  50 
  51 #else
  52 
  53 # define ncr_readb(a)           (*(unsigned char*)(a))
  54 # define ncr_readw(a)           (*(unsigned short*)(a))
  55 # define ncr_readl(a)           (*(unsigned int*)(a))
  56 # define ncr_writeb(v,a)        (*(unsigned char*)(a) = (v))
  57 # define ncr_writew(v,a)        (*(unsigned short*)(a) = (v))
  58 # define ncr_writel(v,a)        (*(unsigned int*)(a) = (v))
  59 
  60 #endif
  61 
  62 /* 
  63  * Prevent name space pollution in hosts.c, and only provide the 
  64  * define we need to get the NCR53c7x0 driver into the host template
  65  * array.
  66  */
  67 
  68 #if defined(HOSTS_C) || defined(MODULE)
  69 #include <linux/scsicam.h>
  70 
  71 extern int NCR53c7xx_abort(Scsi_Cmnd *);
  72 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
  73 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  74 extern int NCR53c7xx_reset(Scsi_Cmnd *);
  75 #ifdef MODULE
  76 extern int NCR53c7xx_release(struct Scsi_Host *);
  77 #else
  78 #define NCR53c7xx_release NULL
  79 #endif
  80 
  81 #define NCR53c7xx {NULL, NULL, NULL, NULL,     \
  82         "NCR53c{7,8}xx (rel 4)", NCR53c7xx_detect,                      \
  83         NULL, /* info */ NULL, /* command, deprecated */ NULL,          \
  84         NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset,      \
  85         NULL /* slave attach */, scsicam_bios_param, /* can queue */ 1, \
  86         /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 1 ,         \
  87         /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING} 
  88 #endif /* defined(HOSTS_C) || defined(MODULE) */ 
  89 
  90 #ifndef HOSTS_C
  91 /* Register addresses, ordered numerically */
  92 
  93 
  94 /* SCSI control 0 rw, default = 0xc0 */ 
  95 #define SCNTL0_REG              0x00    
  96 #define SCNTL0_ARB1             0x80    /* 0 0 = simple arbitration */
  97 #define SCNTL0_ARB2             0x40    /* 1 1 = full arbitration */
  98 #define SCNTL0_STRT             0x20    /* Start Sequence */
  99 #define SCNTL0_WATN             0x10    /* Select with ATN */
 100 #define SCNTL0_EPC              0x08    /* Enable parity checking */
 101 /* Bit 2 is reserved on 800 series chips */
 102 #define SCNTL0_EPG_700          0x04    /* Enable parity generation */
 103 #define SCNTL0_AAP              0x02    /*  ATN/ on parity error */
 104 #define SCNTL0_TRG              0x01    /* Target mode */
 105 
 106 /* SCSI control 1 rw, default = 0x00 */
 107 
 108 #define SCNTL1_REG              0x01    
 109 #define SCNTL1_EXC              0x80    /* Extra Clock Cycle of Data setup */
 110 #define SCNTL1_ADB              0x40    /*  contents of SODL on bus */
 111 #define SCNTL1_ESR_700          0x20    /* Enable SIOP response to selection 
 112                                            and reselection */
 113 #define SCNTL1_DHP_800          0x20    /* Disable halt on parity error or ATN
 114                                            target mode only */
 115 #define SCNTL1_CON              0x10    /* Connected */
 116 #define SCNTL1_RST              0x08    /*  SCSI RST/ */
 117 #define SCNTL1_AESP             0x04    /* Force bad parity */
 118 #define SCNTL1_SND_700          0x02    /* Start SCSI send */
 119 #define SCNTL1_IARB_800         0x02    /* Immediate Arbitration, start
 120                                            arbitration immediately after
 121                                            busfree is detected */
 122 #define SCNTL1_RCV_700          0x01    /* Start SCSI receive */
 123 #define SCNTL1_SST_800          0x01    /* Start SCSI transfer */
 124 
 125 /* SCSI control 2 rw, */
 126 
 127 #define SCNTL2_REG_800          0x02    
 128 #define SCNTL2_800_SDU          0x80    /* SCSI disconnect unexpected */
 129 
 130 /* SCSI control 3 rw */
 131 
 132 #define SCNTL3_REG_800          0x03    
 133 #define SCNTL3_800_SCF_SHIFT    4
 134 #define SCNTL3_800_SCF_MASK     0x70
 135 #define SCNTL3_800_SCF2         0x40    /* Synchronous divisor */
 136 #define SCNTL3_800_SCF1         0x20    /* 0x00 = SCLK/3 */
 137 #define SCNTL3_800_SCF0         0x10    /* 0x10 = SCLK/1 */
 138                                         /* 0x20 = SCLK/1.5 
 139                                            0x30 = SCLK/2 
 140                                            0x40 = SCLK/3 */
 141             
 142 #define SCNTL3_800_CCF_SHIFT    0
 143 #define SCNTL3_800_CCF_MASK     0x07
 144 #define SCNTL3_800_CCF2         0x04    /* 0x00 50.01 to 66 */
 145 #define SCNTL3_800_CCF1         0x02    /* 0x01 16.67 to 25 */
 146 #define SCNTL3_800_CCF0         0x01    /* 0x02 25.01 - 37.5 
 147                                            0x03 37.51 - 50 
 148                                            0x04 50.01 - 66 */
 149 
 150 /*  
 151  * SCSI destination ID rw - the appropriate bit is set for the selected
 152  * target ID.  This is written by the SCSI SCRIPTS processor.
 153  * default = 0x00
 154  */
 155 #define SDID_REG_700            0x02    
 156 #define SDID_REG_800            0x06
 157 
 158 #define GP_REG_800              0x07    /* General purpose IO */
 159 #define GP_800_IO1              0x02
 160 #define GP_800_IO2              0x01
 161 
 162 
 163 /* SCSI interrupt enable rw, default = 0x00 */
 164 #define SIEN_REG_700            0x03    
 165 #define SIEN0_REG_800           0x40
 166 #define SIEN_MA                 0x80    /* Phase mismatch (ini) or ATN (tgt) */
 167 #define SIEN_FC                 0x40    /* Function complete */
 168 #define SIEN_700_STO            0x20    /* Selection or reselection timeout */
 169 #define SIEN_800_SEL            0x20    /* Selected */
 170 #define SIEN_700_SEL            0x10    /* Selected or reselected */
 171 #define SIEN_800_RESEL          0x10    /* Reselected */
 172 #define SIEN_SGE                0x08    /* SCSI gross error */
 173 #define SIEN_UDC                0x04    /* Unexpected disconnect */
 174 #define SIEN_RST                0x02    /* SCSI RST/ received */
 175 #define SIEN_PAR                0x01    /* Parity error */
 176 
 177 /* 
 178  * SCSI chip ID rw
 179  * NCR53c700 : 
 180  *      When arbitrating, the highest bit is used, when reselection or selection
 181  *      occurs, the chip responds to all IDs for which a bit is set.
 182  *      default = 0x00 
 183  * NCR53c810 : 
 184  *      Uses bit mapping
 185  */
 186 #define SCID_REG                0x04    
 187 /* Bit 7 is reserved on 800 series chips */
 188 #define SCID_800_RRE            0x40    /* Enable response to reselection */
 189 #define SCID_800_SRE            0x20    /* Enable response to selection */
 190 /* Bits four and three are reserved on 800 series chips */
 191 #define SCID_800_ENC_MASK       0x07    /* Encoded SCSI ID */
 192 
 193 /* SCSI transfer rw, default = 0x00 */
 194 #define SXFER_REG               0x05
 195 #define SXFER_DHP               0x80    /* Disable halt on parity */
 196 
 197 #define SXFER_TP2               0x40    /* Transfer period msb */
 198 #define SXFER_TP1               0x20
 199 #define SXFER_TP0               0x10    /* lsb */
 200 #define SXFER_TP_MASK           0x70
 201 #define SXFER_TP_SHIFT          4
 202 #define SXFER_TP_4              0x00    /* Divisors */
 203 #define SXFER_TP_5              0x10
 204 #define SXFER_TP_6              0x20
 205 #define SXFER_TP_7              0x30
 206 #define SXFER_TP_8              0x40
 207 #define SXFER_TP_9              0x50
 208 #define SXFER_TP_10             0x60
 209 #define SXFER_TP_11             0x70
 210 
 211 #define SXFER_MO3               0x08    /* Max offset msb */
 212 #define SXFER_MO2               0x04
 213 #define SXFER_MO1               0x02
 214 #define SXFER_MO0               0x01    /* lsb */
 215 #define SXFER_MO_MASK           0x0f
 216 #define SXFER_MO_SHIFT          0
 217 
 218 /* 
 219  * SCSI output data latch rw
 220  * The contents of this register are driven onto the SCSI bus when 
 221  * the Assert Data Bus bit of the SCNTL1 register is set and 
 222  * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
 223  */
 224 #define SODL_REG_700            0x06    
 225 #define SODL_REG_800            0x54
 226 
 227 
 228 /* 
 229  * SCSI output control latch rw, default = 0 
 230  * Note that when the chip is being manually programmed as an initiator,
 231  * the MSG, CD, and IO bits must be set correctly for the phase the target
 232  * is driving the bus in.  Otherwise no data transfer will occur due to 
 233  * phase mismatch.
 234  */
 235 
 236 #define SBCL_REG                0x0b
 237 #define SBCL_REQ                0x80    /*  REQ */
 238 #define SBCL_ACK                0x40    /*  ACK */
 239 #define SBCL_BSY                0x20    /*  BSY */
 240 #define SBCL_SEL                0x10    /*  SEL */
 241 #define SBCL_ATN                0x08    /*  ATN */
 242 #define SBCL_MSG                0x04    /*  MSG */
 243 #define SBCL_CD                 0x02    /*  C/D */
 244 #define SBCL_IO                 0x01    /*  I/O */
 245 #define SBCL_PHASE_CMDOUT       SBCL_CD
 246 #define SBCL_PHASE_DATAIN       SBCL_IO
 247 #define SBCL_PHASE_DATAOUT      0
 248 #define SBCL_PHASE_MSGIN        (SBCL_CD|SBCL_IO|SBCL_MSG)
 249 #define SBCL_PHASE_MSGOUT       (SBCL_CD|SBCL_MSG)
 250 #define SBCL_PHASE_STATIN       (SBCL_CD|SBCL_IO)
 251 #define SBCL_PHASE_MASK         (SBCL_CD|SBCL_IO|SBCL_MSG)
 252 
 253 /* 
 254  * SCSI first byte received latch ro 
 255  * This register contains the first byte received during a block MOVE 
 256  * SCSI SCRIPTS instruction, including
 257  * 
 258  * Initiator mode       Target mode
 259  * Message in           Command
 260  * Status               Message out
 261  * Data in              Data out
 262  *
 263  * It also contains the selecting or reselecting device's ID and our 
 264  * ID.
 265  *
 266  * Note that this is the register the various IF conditionals can 
 267  * operate on.
 268  */
 269 #define SFBR_REG                0x08    
 270 
 271 /* 
 272  * SCSI input data latch ro
 273  * In initiator mode, data is latched into this register on the rising
 274  * edge of REQ/. In target mode, data is latched on the rising edge of 
 275  * ACK/
 276  */
 277 #define SIDL_REG_700            0x09
 278 #define SIDL_REG_800            0x50
 279 
 280 /* 
 281  * SCSI bus data lines ro 
 282  * This register reflects the instantaneous status of the SCSI data 
 283  * lines.  Note that SCNTL0 must be set to disable parity checking, 
 284  * otherwise reading this register will latch new parity.
 285  */
 286 #define SBDL_REG_700            0x0a
 287 #define SBDL_REG_800            0x58
 288 
 289 #define SSID_REG_800            0x0a
 290 #define SSID_800_VAL            0x80    /* Exactly two bits asserted at sel */
 291 #define SSID_800_ENCID_MASK     0x07    /* Device which performed operation */
 292 
 293 
 294 /* 
 295  * SCSI bus control lines rw, 
 296  * instantaneous readout of control lines 
 297  */
 298 #define SOCL_REG                0x0b    
 299 #define SOCL_REQ                0x80    /*  REQ ro */
 300 #define SOCL_ACK                0x40    /*  ACK ro */
 301 #define SOCL_BSY                0x20    /*  BSY ro */
 302 #define SOCL_SEL                0x10    /*  SEL ro */
 303 #define SOCL_ATN                0x08    /*  ATN ro */
 304 #define SOCL_MSG                0x04    /*  MSG ro */
 305 #define SOCL_CD                 0x02    /*  C/D ro */
 306 #define SOCL_IO                 0x01    /*  I/O ro */
 307 /* 
 308  * Synchronous SCSI Clock Control bits 
 309  * 0 - set by DCNTL 
 310  * 1 - SCLK / 1.0
 311  * 2 - SCLK / 1.5
 312  * 3 - SCLK / 2.0 
 313  */
 314 #define SBCL_SSCF1              0x02    /* wo, -66 only */
 315 #define SBCL_SSCF0              0x01    /* wo, -66 only */
 316 #define SBCL_SSCF_MASK          0x03
 317 
 318 /* 
 319  * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
 320  * insure that 10 clocks elapse between the two  
 321  */
 322 /* DMA status ro */
 323 #define DSTAT_REG               0x0c    
 324 #define DSTAT_DFE               0x80    /* DMA FIFO empty */
 325 #define DSTAT_800_MDPE          0x40    /* Master Data Parity Error */
 326 #define DSTAT_800_BF            0x20    /* Bus Fault */
 327 #define DSTAT_ABRT              0x10    /* Aborted - set on error */
 328 #define DSTAT_SSI               0x08    /* SCRIPTS single step interrupt */
 329 #define DSTAT_SIR               0x04    /* SCRIPTS interrupt received - 
 330                                            set when INT instruction is 
 331                                            executed */
 332 #define DSTAT_WTD               0x02    /* Watchdog timeout detected */
 333 #define DSTAT_OPC               0x01    /* Illegal instruction */
 334 #define DSTAT_800_IID           0x01    /* Same thing, different name */
 335 
 336 
 337 #define SSTAT0_REG              0x0d    /* SCSI status 0 ro */
 338 #define SIST0_REG_800           0x42    
 339 #define SSTAT0_MA               0x80    /* ini : phase mismatch,
 340                                          * tgt : ATN/ asserted 
 341                                          */
 342 #define SSTAT0_CMP              0x40    /* function complete */
 343 #define SSTAT0_700_STO          0x20    /* Selection or reselection timeout */
 344 #define SIST0_800_SEL           0x20    /* Selected */
 345 #define SSTAT0_700_SEL          0x10    /* Selected or reselected */
 346 #define SIST0_800_RSL           0x10    /* Reselected */
 347 #define SSTAT0_SGE              0x08    /* SCSI gross error */
 348 #define SSTAT0_UDC              0x04    /* Unexpected disconnect */
 349 #define SSTAT0_RST              0x02    /* SCSI RST/ received */
 350 #define SSTAT0_PAR              0x01    /* Parity error */
 351 
 352 #define SSTAT1_REG              0x0e    /* SCSI status 1 ro */
 353 #define SSTAT1_ILF              0x80    /* SIDL full */
 354 #define SSTAT1_ORF              0x40    /* SODR full */
 355 #define SSTAT1_OLF              0x20    /* SODL full */
 356 #define SSTAT1_AIP              0x10    /* Arbitration in progress */
 357 #define SSTAT1_LOA              0x08    /* Lost arbitration */
 358 #define SSTAT1_WOA              0x04    /* Won arbitration */
 359 #define SSTAT1_RST              0x02    /* Instant readout of RST/ */
 360 #define SSTAT1_SDP              0x01    /* Instant readout of SDP/ */
 361 
 362 #define SSTAT2_REG              0x0f    /* SCSI status 2 ro */
 363 #define SSTAT2_FF3              0x80    /* number of bytes in synchronous */
 364 #define SSTAT2_FF2              0x40    /* data FIFO */
 365 #define SSTAT2_FF1              0x20    
 366 #define SSTAT2_FF0              0x10
 367 #define SSTAT2_FF_MASK          0xf0
 368 
 369 /* 
 370  * Latched signals, latched on the leading edge of REQ/ for initiators,
 371  * ACK/ for targets.
 372  */
 373 #define SSTAT2_SDP              0x08    /* SDP */
 374 #define SSTAT2_MSG              0x04    /* MSG */
 375 #define SSTAT2_CD               0x02    /* C/D */
 376 #define SSTAT2_IO               0x01    /* I/O */
 377 
 378 
 379 /* NCR53c700-66 only */
 380 #define SCRATCHA_REG_00         0x10    /* through  0x13 Scratch A rw */
 381 /* NCR53c710 and higher */
 382 #define DSA_REG                 0x10    /* DATA structure address */
 383 
 384 #define CTEST0_REG_700          0x14    /* Chip test 0 ro */
 385 #define CTEST0_REG_800          0x18    /* Chip test 0 rw, general purpose */
 386 /* 0x80 - 0x04 are reserved */
 387 #define CTEST0_700_RTRG         0x02    /* Real target mode */
 388 #define CTEST0_700_DDIR         0x01    /* Data direction, 1 = 
 389                                          * SCSI bus to host, 0  =
 390                                          * host to SCSI.
 391                                          */
 392 
 393 #define CTEST1_REG_700          0x15    /* Chip test 1 ro */
 394 #define CTEST1_REG_800          0x19    /* Chip test 1 ro */
 395 #define CTEST1_FMT3             0x80    /* Identify which byte lanes are empty */
 396 #define CTEST1_FMT2             0x40    /* in the DMA FIFO */
 397 #define CTEST1_FMT1             0x20
 398 #define CTEST1_FMT0             0x10
 399 
 400 #define CTEST1_FFL3             0x08    /* Identify which bytes lanes are full */
 401 #define CTEST1_FFL2             0x04    /* in the DMA FIFO */
 402 #define CTEST1_FFL1             0x02
 403 #define CTEST1_FFL0             0x01
 404 
 405 #define CTEST2_REG_700          0x16    /* Chip test 2 ro */
 406 #define CTEST2_REG_800          0x1a    /* Chip test 2 ro */
 407 
 408 #define CTEST2_800_DDIR         0x80    /* 1 = SCSI->host */
 409 #define CTEST2_800_SIGP         0x40    /* A copy of SIGP in ISTAT.
 410                                            Reading this register clears */
 411 #define CTEST2_800_CIO          0x20    /* Configured as IO */.
 412 #define CTEST2_800_CM           0x10    /* Configured as memory */
 413 
 414 /* 0x80 - 0x40 are reserved on 700 series chips */
 415 #define CTEST2_700_SOFF         0x20    /* SCSI Offset Compare,
 416                                          * As an initiator, this bit is 
 417                                          * one when the synchronous offset
 418                                          * is zero, as a target this bit 
 419                                          * is one when the synchronous 
 420                                          * offset is at the maximum
 421                                          * defined in SXFER
 422                                          */
 423 #define CTEST2_700_SFP          0x10    /* SCSI FIFO parity bit,
 424                                          * reading CTEST3 unloads a byte
 425                                          * from the FIFO and sets this
 426                                          */
 427 #define CTEST2_700_DFP          0x08    /* DMA FIFO parity bit,
 428                                          * reading CTEST6 unloads a byte
 429                                          * from the FIFO and sets this
 430                                          */
 431 #define CTEST2_TEOP             0x04    /* SCSI true end of process,
 432                                          * indicates a totally finished
 433                                          * transfer
 434                                          */
 435 #define CTEST2_DREQ             0x02    /* Data request signal */
 436 /* 0x01 is reserved on 700 series chips */
 437 #define CTEST2_800_DACK         0x01    
 438 
 439 /* 
 440  * Chip test 3 ro 
 441  * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
 442  * check SSTAT2 FIFO full bits to determine size.  Note that a GROSS
 443  * error results if a read is attempted on this register.  Also note 
 444  * that 16 and 32 bit reads of this register will cause corruption.
 445  */
 446 #define CTEST3_REG_700          0x17    
 447 /*  Chip test 3 rw */
 448 #define CTEST3_REG_800          0x1b
 449 #define CTEST3_800_V3           0x80    /* Chip revision */
 450 #define CTEST3_800_V2           0x40
 451 #define CTEST3_800_V1           0x20
 452 #define CTEST3_800_V0           0x10
 453 #define CTEST3_800_FLF          0x08    /* Flush DMA FIFO */
 454 #define CTEST3_800_CLF          0x04    /* Clear DMA FIFO */
 455 #define CTEST3_800_FM           0x02    /* Fetch mode pin */
 456 /* bit 0 is reserved on 800 series chips */
 457 
 458 #define CTEST4_REG_700          0x18    /* Chip test 4 rw */
 459 #define CTEST4_REG_800          0x21    /* Chip test 4 rw */
 460 /* 0x80 is reserved on 700 series chips */
 461 #define CTEST4_800_BDIS         0x80    /* Burst mode disable */
 462 #define CTEST4_ZMOD             0x40    /* High impedance mode */
 463 #define CTEST4_SZM              0x20    /* SCSI bus high impedance */
 464 #define CTEST4_700_SLBE         0x10    /* SCSI loopback enabled */
 465 #define CTEST4_800_SRTM         0x10    /* Shadow Register Test Mode */
 466 #define CTEST4_700_SFWR         0x08    /* SCSI FIFO write enable, 
 467                                          * redirects writes from SODL
 468                                          * to the SCSI FIFO.
 469                                          */
 470 #define CTEST4_800_MPEE         0x08    /* Enable parity checking
 471                                            during master cycles on PCI
 472                                            bus */
 473 
 474 /* 
 475  * These bits send the contents of the CTEST6 register to the appropriate
 476  * byte lane of the 32 bit DMA FIFO.  Normal operation is zero, otherwise 
 477  * the high bit means the low two bits select the byte lane.
 478  */
 479 #define CTEST4_FBL2             0x04    
 480 #define CTEST4_FBL1             0x02
 481 #define CTEST4_FBL0             0x01    
 482 #define CTEST4_FBL_MASK         0x07
 483 #define CTEST4_FBL_0            0x04    /* Select DMA FIFO byte lane 0 */
 484 #define CTEST4_FBL_1            0x05    /* Select DMA FIFO byte lane 1 */
 485 #define CTEST4_FBL_2            0x06    /* Select DMA FIFO byte lane 2 */
 486 #define CTEST4_FBL_3            0x07    /* Select DMA FIFO byte lane 3 */
 487 #define CTEST4_800_SAVE         (CTEST4_800_BDIS)
 488 
 489 
 490 #define CTEST5_REG_700          0x19    /* Chip test 5 rw */
 491 #define CTEST5_REG_800          0x22    /* Chip test 5 rw */
 492 /* 
 493  * Clock Address Incrementor.  When set, it increments the 
 494  * DNAD register to the next bus size boundary.  It automatically 
 495  * resets itself when the operation is complete.
 496  */
 497 #define CTEST5_ADCK             0x80
 498 /*
 499  * Clock Byte Counter.  When set, it decrements the DBC register to
 500  * the next bus size boundary.
 501  */
 502 #define CTEST5_BBCK             0x40
 503 /*
 504  * Reset SCSI Offset.  Setting this bit to 1 clears the current offset
 505  * pointer in the SCSI synchronous offset counter (SSTAT).  This bit
 506  * is set to 1 if a SCSI Gross Error Condition occurs.  The offset should
 507  * be cleared when a synchronous transfer fails.  When written, it is 
 508  * automatically cleared after the SCSI synchronous offset counter is 
 509  * reset.
 510  */
 511 /* Bit 5 is reserved on 800 series chips */
 512 #define CTEST5_700_ROFF         0x20
 513 /* 
 514  * Master Control for Set or Reset pulses. When 1, causes the low 
 515  * four bits of register to set when set, 0 causes the low bits to
 516  * clear when set.
 517  */
 518 #define CTEST5_MASR             0x10    
 519 #define CTEST5_DDIR             0x08    /* DMA direction */
 520 /*
 521  * Bits 2-0 are reserved on 800 series chips
 522  */
 523 #define CTEST5_700_EOP          0x04    /* End of process */
 524 #define CTEST5_700_DREQ         0x02    /* Data request */
 525 #define CTEST5_700_DACK         0x01    /* Data acknowledge */
 526 
 527 /* 
 528  * Chip test 6 rw - writing to this register writes to the byte 
 529  * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
 530  * register.
 531  */
 532 #define CTEST6_REG_700          0x1a
 533 #define CTEST6_REG_800          0x23
 534 
 535 #define CTEST7_REG              0x1b    /* Chip test 7 rw */
 536 /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
 537 #define CTEST7_10_CDIS          0x80    /* Cache burst disable */
 538 #define CTEST7_10_SC1           0x40    /* Snoop control bits */
 539 #define CTEST7_10_SC0           0x20    
 540 #define CTEST7_10_SC_MASK       0x60
 541 /* 0x20 is reserved on the NCR53c700 */
 542 #define CTEST7_0060_FM          0x20    /* Fetch mode */
 543 #define CTEST7_STD              0x10    /* Selection timeout disable */
 544 #define CTEST7_DFP              0x08    /* DMA FIFO parity bit for CTEST6 */
 545 #define CTEST7_EVP              0x04    /* 1 = host bus even parity, 0 = odd */
 546 #define CTEST7_10_TT1           0x02    /* Transfer type */
 547 #define CTEST7_00_DC            0x02    /* Set to drive DC low during instruction 
 548                                            fetch */
 549 #define CTEST7_DIFF             0x01    /* Differential mode */
 550 
 551 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
 552 
 553 
 554 #define TEMP_REG                0x1c    /* through 0x1f Temporary stack rw */
 555 
 556 #define DFIFO_REG               0x20    /* DMA FIFO rw */
 557 /* 
 558  * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
 559  * moved into the CTEST8 register.
 560  */
 561 #define DFIFO_00_FLF            0x80    /* Flush DMA FIFO to memory */
 562 #define DFIFO_00_CLF            0x40    /* Clear DMA and SCSI FIFOs */
 563 #define DFIFO_BO6               0x40
 564 #define DFIFO_BO5               0x20
 565 #define DFIFO_BO4               0x10
 566 #define DFIFO_BO3               0x08
 567 #define DFIFO_BO2               0x04 
 568 #define DFIFO_BO1               0x02
 569 #define DFIFO_BO0               0x01
 570 #define DFIFO_10_BO_MASK        0x7f    /* 7 bit counter */
 571 #define DFIFO_00_BO_MASK        0x3f    /* 6 bit counter */
 572 
 573 /* 
 574  * Interrupt status rw 
 575  * Note that this is the only register which can be read while SCSI
 576  * SCRIPTS are being executed.
 577  */
 578 #define ISTAT_REG_700           0x21
 579 #define ISTAT_REG_800           0x14
 580 #define ISTAT_ABRT              0x80    /* Software abort, write 
 581                                          *1 to abort, wait for interrupt. */
 582 /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
 583 #define ISTAT_10_SRST           0x40    /* software reset */
 584 #define ISTAT_10_SIGP           0x20    /* signal script */
 585 /* 0x10 is reserved on NCR53c700 series chips */
 586 #define ISTAT_800_SEM           0x10    /* semaphore */
 587 #define ISTAT_CON               0x08    /* 1 when connected */
 588 #define ISTAT_800_INTF          0x04    /* Interrupt on the fly */
 589 #define ISTAT_700_PRE           0x04    /* Pointer register empty.
 590                                          * Set to 1 when DSPS and DSP
 591                                          * registers are empty in pipeline
 592                                          * mode, always set otherwise.
 593                                          */
 594 #define ISTAT_SIP               0x02    /* SCSI interrupt pending from
 595                                          * SCSI portion of SIOP see
 596                                          * SSTAT0
 597                                          */
 598 #define ISTAT_DIP               0x01    /* DMA interrupt pending 
 599                                          * see DSTAT
 600                                          */
 601 
 602 /* NCR53c700-66 and NCR53c710 only */
 603 #define CTEST8_REG              0x22    /* Chip test 8 rw */
 604 #define CTEST8_0066_EAS         0x80    /* Enable alternate SCSI clock,
 605                                          * ie read from SCLK/ rather than CLK/
 606                                          */
 607 #define CTEST8_0066_EFM         0x40    /* Enable fetch and master outputs */
 608 #define CTEST8_0066_GRP         0x20    /* Generate Receive Parity for 
 609                                          * pass through.  This insures that 
 610                                          * bad parity won't reach the host 
 611                                          * bus.
 612                                          */
 613 #define CTEST8_0066_TE          0x10    /* TolerANT enable.  Enable 
 614                                          * active negation, should only
 615                                          * be used for slow SCSI 
 616                                          * non-differential.
 617                                          */
 618 #define CTEST8_0066_HSC         0x08    /* Halt SCSI clock */
 619 #define CTEST8_0066_SRA         0x04    /* Shorten REQ/ACK filtering,
 620                                          * must be set for fast SCSI-II
 621                                          * speeds.
 622                                          */
 623 #define CTEST8_0066_DAS         0x02    /* Disable automatic target/initiator
 624                                          * switching.
 625                                          */
 626 #define CTEST8_0066_LDE         0x01    /* Last disconnect enable.
 627                                          * The status of pending 
 628                                          * disconnect is maintained by
 629                                          * the core, eliminating
 630                                          * the possibility of missing a 
 631                                          * selection or reselection
 632                                          * while waiting to fetch a 
 633                                          * WAIT DISCONNECT opcode.
 634                                          */
 635 
 636 #define CTEST8_10_V3            0x80    /* Chip revision */
 637 #define CTEST8_10_V2            0x40
 638 #define CTEST8_10_V1            0x20    
 639 #define CTEST8_10_V0            0x10
 640 #define CTEST8_10_V_MASK        0xf0    
 641 #define CTEST8_10_FLF           0x08    /* Flush FIFOs */
 642 #define CTEST8_10_CLF           0x04    /* Clear FIFOs */
 643 #define CTEST8_10_FM            0x02    /* Fetch pin mode */
 644 #define CTEST8_10_SM            0x01    /* Snoop pin mode */
 645 
 646 
 647 /* 
 648  * The CTEST9 register may be used to differentiate between a
 649  * NCR53c700 and a NCR53c710.  
 650  *
 651  * Write 0xff to this register.
 652  * Read it.
 653  * If the contents are 0xff, it is a NCR53c700
 654  * If the contents are 0x00, it is a NCR53c700-66 first revision
 655  * If the contents are some other value, it is some other NCR53c700-66
 656  */
 657 #define CTEST9_REG_00           0x23    /* Chip test 9 ro */
 658 #define LCRC_REG_10             0x23    
 659 
 660 /*
 661  * 0x24 through 0x27 are the DMA byte counter register.  Instructions
 662  * write their high 8 bits into the DCMD register, the low 24 bits into
 663  * the DBC register.
 664  *
 665  * Function is dependent on the command type being executed.
 666  */
 667 
 668  
 669 #define DBC_REG                 0x24
 670 /* 
 671  * For Block Move Instructions, DBC is a 24 bit quantity representing 
 672  *     the number of bytes to transfer.
 673  * For Transfer Control Instructions, DBC is bit fielded as follows : 
 674  */
 675 /* Bits 20 - 23 should be clear */
 676 #define DBC_TCI_TRUE            (1 << 19)       /* Jump when true */
 677 #define DBC_TCI_COMPARE_DATA    (1 << 18)       /* Compare data */
 678 #define DBC_TCI_COMPARE_PHASE   (1 << 17)       /* Compare phase with DCMD field */
 679 #define DBC_TCI_WAIT_FOR_VALID  (1 << 16)       /* Wait for REQ */
 680 /* Bits 8 - 15 are reserved on some implementations ? */
 681 #define DBC_TCI_MASK_MASK       0xff00          /* Mask for data compare */
 682 #define DBC_TCI_MASK_SHIFT      8
 683 #define DBC_TCI_DATA_MASK       0xff            /* Data to be compared */ 
 684 #define DBC_TCI_DATA_SHIFT      0
 685 
 686 #define DBC_RWRI_IMMEDIATE_MASK 0xff00          /* Immediate data */
 687 #define DBC_RWRI_IMMEDIATE_SHIFT 8              /* Amount to shift */
 688 #define DBC_RWRI_ADDRESS_MASK   0x3f0000        /* Register address */
 689 #define DBC_RWRI_ADDRESS_SHIFT  16
 690 
 691 
 692 /*
 693  * DMA command r/w
 694  */
 695 #define DCMD_REG                0x27    
 696 #define DCMD_TYPE_MASK          0xc0    /* Masks off type */
 697 #define DCMD_TYPE_BMI           0x00    /* Indicates a Block Move instruction */
 698 #define DCMD_BMI_IO             0x01    /* I/O, CD, and MSG bits selecting   */
 699 #define DCMD_BMI_CD             0x02    /* the phase for the block MOVE      */
 700 #define DCMD_BMI_MSG            0x04    /* instruction                       */
 701 
 702 #define DCMD_BMI_OP_MASK        0x18    /* mask for opcode */
 703 #define DCMD_BMI_OP_MOVE_T      0x00    /* MOVE */
 704 #define DCMD_BMI_OP_MOVE_I      0x08    /* MOVE Initiator */
 705 
 706 #define DCMD_BMI_INDIRECT       0x20    /*  Indirect addressing */
 707 
 708 #define DCMD_TYPE_TCI           0x80    /* Indicates a Transfer Control 
 709                                            instruction */
 710 #define DCMD_TCI_IO             0x01    /* I/O, CD, and MSG bits selecting   */
 711 #define DCMD_TCI_CD             0x02    /* the phase for the block MOVE      */
 712 #define DCMD_TCI_MSG            0x04    /* instruction                       */
 713 #define DCMD_TCI_OP_MASK        0x38    /* mask for opcode */
 714 #define DCMD_TCI_OP_JUMP        0x00    /* JUMP */
 715 #define DCMD_TCI_OP_CALL        0x08    /* CALL */
 716 #define DCMD_TCI_OP_RETURN      0x10    /* RETURN */
 717 #define DCMD_TCI_OP_INT         0x18    /* INT */
 718 
 719 #define DCMD_TYPE_RWRI          0x40    /* Indicates I/O or register Read/Write
 720                                            instruction */
 721 #define DCMD_RWRI_OPC_MASK      0x38    /* Opcode mask */
 722 #define DCMD_RWRI_OPC_WRITE     0x28    /* Write SFBR to register */
 723 #define DCMD_RWRI_OPC_READ      0x30    /* Read register to SFBR */
 724 #define DCMD_RWRI_OPC_MODIFY    0x38    /* Modify in place */
 725 
 726 #define DCMD_RWRI_OP_MASK       0x07
 727 #define DCMD_RWRI_OP_MOVE       0x00
 728 #define DCMD_RWRI_OP_SHL        0x01
 729 #define DCMD_RWRI_OP_OR         0x02
 730 #define DCMD_RWRI_OP_XOR        0x03
 731 #define DCMD_RWRI_OP_AND        0x04
 732 #define DCMD_RWRI_OP_SHR        0x05
 733 #define DCMD_RWRI_OP_ADD        0x06
 734 #define DCMD_RWRI_OP_ADDC       0x07
 735 
 736 #define DCMD_TYPE_MMI           0xc0    /* Indicates a Memory Move instruction 
 737                                            (three words) */
 738 
 739 
 740 #define DNAD_REG                0x28    /* through 0x2b DMA next address for 
 741                                            data */
 742 #define DSP_REG                 0x2c    /* through 0x2f DMA SCRIPTS pointer rw */
 743 #define DSPS_REG                0x30    /* through 0x33 DMA SCRIPTS pointer 
 744                                            save rw */
 745 #define DMODE_REG_00            0x34    /* DMA mode rw */
 746 #define DMODE_00_BL1    0x80    /* Burst length bits */
 747 #define DMODE_00_BL0    0x40
 748 #define DMODE_BL_MASK   0xc0
 749 /* Burst lengths (800) */
 750 #define DMODE_BL_2      0x00    /* 2 transfer */
 751 #define DMODE_BL_4      0x40    /* 4 transfers */
 752 #define DMODE_BL_8      0x80    /* 8 transfers */
 753 #define DMODE_BL_16     0xc0    /* 16 transfers */
 754 
 755 #define DMODE_700_BW16  0x20    /* Host buswidth = 16 */
 756 #define DMODE_700_286   0x10    /* 286 mode */
 757 #define DMODE_700_IOM   0x08    /* Transfer to IO port */
 758 #define DMODE_700_FAM   0x04    /* Fixed address mode */
 759 #define DMODE_700_PIPE  0x02    /* Pipeline mode disables 
 760                                          * automatic fetch / exec 
 761                                          */
 762 #define DMODE_MAN       0x01            /* Manual start mode, 
 763                                          * requires a 1 to be written
 764                                          * to the start DMA bit in the DCNTL
 765                                          * register to run scripts 
 766                                          */
 767 
 768 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
 769 
 770 /* NCR53c800 series only */
 771 #define SCRATCHA_REG_800        0x34    /* through 0x37 Scratch A rw */
 772 /* NCR53c710 only */
 773 #define SCRATCB_REG_10          0x34    /* through 0x37 scratch B rw */
 774 
 775 #define DMODE_REG_10            0x38    /* DMA mode rw, NCR53c710 and newer */
 776 #define DMODE_800_SIOM          0x20    /* Source IO = 1 */
 777 #define DMODE_800_DIOM          0x10    /* Destination IO = 1 */
 778 #define DMODE_800_ERL           0x08    /* Enable Read Line */
 779 
 780 /* 35-38 are reserved on 700 and 700-66 series chips */
 781 #define DIEN_REG                0x39    /* DMA interrupt enable rw */
 782 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
 783 #define DIEN_800_MDPE           0x40    /* Master data parity error */
 784 #define DIEN_800_BF             0x20    /* BUS fault */
 785 #define DIEN_ABRT               0x10    /* Enable aborted interrupt */
 786 #define DIEN_SSI                0x08    /* Enable single step interrupt */
 787 #define DIEN_SIR                0x04    /* Enable SCRIPTS INT command 
 788                                          * interrupt
 789                                          */
 790 /* 0x02 is reserved on 800 series chips */
 791 #define DIEN_700_WTD            0x02    /* Enable watchdog timeout interrupt */
 792 #define DIEN_700_OPC            0x01    /* Enable illegal instruction 
 793                                          * interrupt 
 794                                          */
 795 #define DIEN_800_IID            0x01    /*  Same meaning, different name */ 
 796 
 797 /*
 798  * DMA watchdog timer rw
 799  * set in 16 CLK input periods.
 800  */
 801 #define DWT_REG                 0x3a
 802 
 803 /* DMA control rw */
 804 #define DCNTL_REG               0x3b
 805 #define DCNTL_700_CF1           0x80    /* Clock divisor bits */
 806 #define DCNTL_700_CF0           0x40
 807 #define DCNTL_700_CF_MASK       0xc0
 808 /* Clock divisors                          Divisor SCLK range (MHZ) */
 809 #define DCNTL_700_CF_2          0x00    /* 2.0     37.51-50.00 */
 810 #define DCNTL_700_CF_1_5        0x40    /* 1.5     25.01-37.50 */
 811 #define DCNTL_700_CF_1          0x80    /* 1.0     16.67-25.00 */
 812 #define DCNTL_700_CF_3          0xc0    /* 3.0     50.01-66.67 (53c700-66) */
 813 
 814 #define DCNTL_700_S16           0x20    /* Load scripts 16 bits at a time */
 815 #define DCNTL_SSM               0x10    /* Single step mode */
 816 #define DCNTL_700_LLM           0x08    /* Low level mode, can only be set 
 817                                          * after selection */
 818 #define DCNTL_800_IRQM          0x08    /* Totem pole IRQ pin */
 819 #define DCNTL_STD               0x04    /* Start DMA / SCRIPTS */
 820 /* 0x02 is reserved */
 821 #define DCNTL_00_RST            0x01    /* Software reset, resets everything
 822                                          * but 286 mode bit  in DMODE. On the
 823                                          * NCR53c710, this bit moved to CTEST8
 824                                          */
 825 #define DCNTL_10_COM            0x01    /* 700 software compatibility mode */
 826 
 827 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
 828 
 829 
 830 /* NCR53c700-66 only */
 831 #define SCRATCHB_REG_00         0x3c    /* through 0x3f scratch b rw */
 832 #define SCRATCHB_REG_800        0x5c    /* through 0x5f scratch b rw */
 833 /* NCR53c710 only */
 834 #define ADDER_REG_10            0x3c    /* Adder, NCR53c710 only */
 835 
 836 #define SIEN1_REG_800           0x41
 837 #define SIEN1_800_STO           0x04    /* selection/reselection timeout */
 838 #define SIEN1_800_GEN           0x02    /* general purpose timer */
 839 #define SIEN1_800_HTH           0x01    /* handshake to handshake */
 840 
 841 #define SIST1_REG_800           0x43
 842 #define SIST1_800_STO           0x04    /* selection/reselection timeout */
 843 #define SIST1_800_GEN           0x02    /* general purpose timer */
 844 #define SIST1_800_HTH           0x01    /* handshake to handshake */
 845 
 846 #define SLPAR_REG_800           0x44    /* Parity */
 847 
 848 #define MACNTL_REG_800          0x46    /* Memory access control */
 849 #define MACNTL_800_TYP3         0x80
 850 #define MACNTL_800_TYP2         0x40
 851 #define MACNTL_800_TYP1         0x20
 852 #define MACNTL_800_TYP0         0x10
 853 #define MACNTL_800_DWR          0x08
 854 #define MACNTL_800_DRD          0x04
 855 #define MACNTL_800_PSCPT        0x02
 856 #define MACNTL_800_SCPTS        0x01
 857 
 858 #define GPCNTL_REG_800          0x47    /* General Purpose Pin Control */
 859 
 860 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
 861 #define STIME0_REG_800          0x48    /* SCSI Timer Register 0 */
 862 #define STIME0_800_HTH_MASK     0xf0    /* Handshake to Handshake timeout */
 863 #define STIME0_800_HTH_SHIFT    4
 864 #define STIME0_800_SEL_MASK     0x0f    /* Selection timeout */
 865 #define STIME0_800_SEL_SHIFT    0
 866 
 867 #define STIME1_REG_800          0x49
 868 #define STIME1_800_GEN_MASK     0x0f    /* General purpose timer */
 869 
 870 #define RESPID_REG_800          0x4a    /* Response ID, bit fielded */
 871 
 872 #define STEST0_REG_800          0x4c    
 873 #define STEST0_800_SLT          0x08    /* Selection response logic test */
 874 #define STEST0_800_ART          0x04    /* Arbitration priority encoder test */
 875 #define STEST0_800_SOZ          0x02    /* Synchronous offset zero */
 876 #define STEST0_800_SOM          0x01    /* Synchronous offset maximum */
 877 
 878 #define STEST1_REG_800          0x4d
 879 #define STEST1_800_SCLK         0x80    /* Disable SCSI clock */
 880 
 881 #define STEST2_REG_800          0x4e    
 882 #define STEST2_800_SCE          0x80    /* Enable SOCL/SODL */
 883 #define STEST2_800_ROF          0x40    /* Reset SCSI sync offset */
 884 #define STEST2_800_SLB          0x10    /* Enable SCSI loopback mode */
 885 #define STEST2_800_SZM          0x08    /* SCSI high impedance mode */
 886 #define STEST2_800_EXT          0x02    /* Extend REQ/ACK filter 30 to 60ns */
 887 #define STEST2_800_LOW          0x01    /* SCSI low level mode */
 888 
 889 #define STEST3_REG_800          0x4f     
 890 #define STEST3_800_TE           0x80    /* Enable active negation */
 891 #define STEST3_800_STR          0x40    /* SCSI FIFO test read */
 892 #define STEST3_800_HSC          0x20    /* Halt SCSI clock */
 893 #define STEST3_800_DSI          0x10    /* Disable single initiator response */
 894 #define STEST3_800_TTM          0x04    /* Time test mode */
 895 #define STEST3_800_CSF          0x02    /* Clear SCSI FIFO */
 896 #define STEST3_800_STW          0x01    /* SCSI FIFO test write */
 897 
 898 
 899 
 900 
 901 
 902 #define OPTION_PARITY           0x1     /* Enable parity checking */
 903 #define OPTION_TAGGED_QUEUE     0x2     /* Enable SCSI-II tagged queuing */
 904 #define OPTION_700              0x8     /* Always run NCR53c700 scripts */
 905 #define OPTION_INTFLY           0x10    /* Use INTFLY interrupts */
 906 #define OPTION_DEBUG_INTR       0x20    /* Debug interrupts */
 907 #define OPTION_DEBUG_INIT_ONLY  0x40    /* Run initialization code and 
 908                                            simple test code, return
 909                                            DID_NO_CONNECT if any SCSI
 910                                            commands are attempted. */
 911 #define OPTION_DEBUG_READ_ONLY  0x80    /* Return DID_ERROR if any 
 912                                            SCSI write is attempted */
 913 #define OPTION_DEBUG_TRACE      0x100   /* Animated trace mode, print 
 914                                            each address and instruction 
 915                                            executed to debug buffer. */
 916 #define OPTION_DEBUG_SINGLE     0x200   /* stop after executing one 
 917                                            instruction */
 918 #define OPTION_SYNCHRONOUS      0x400   /* Enable sync SCSI.  */
 919 #define OPTION_MEMORY_MAPPED    0x800   /* NCR registers have valid 
 920                                            memory mapping */
 921 #define OPTION_IO_MAPPED        0x1000  /* NCR registers have valid
 922                                            I/O mapping */
 923 #define OPTION_DEBUG_PROBE_ONLY 0x2000  /* Probe only, don't even init */
 924 #define OPTION_DEBUG_TESTS_ONLY 0x4000  /* Probe, init, run selected tests */
 925 
 926 #define OPTION_DEBUG_TEST0      0x08000 /* Run test 0 */
 927 #define OPTION_DEBUG_TEST1      0x10000 /* Run test 1 */
 928 #define OPTION_DEBUG_TEST2      0x20000 /* Run test 2 */
 929 
 930 #define OPTION_DEBUG_DUMP       0x40000 /* Dump commands */
 931 #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
 932 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
 933 #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
 934 #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
 935 #define OPTION_DEBUG_DSA 0x800000
 936 #define OPTION_DEBUG_CORRUPTION 0x1000000       /* Detect script corruption */
 937 
 938 #if !defined(PERM_OPTIONS)
 939 #define PERM_OPTIONS 0
 940 #endif
 941                                 
 942 struct NCR53c7x0_synchronous {
 943     u32 select_indirect;                /* Value used for indirect selection */
 944     u32 script[6];                      /* Size ?? Script used when target is 
 945                                                 reselected */
 946     unsigned renegotiate:1;             /* Force renegotiation on next   
 947                                            select */
 948 };
 949 
 950 #define CMD_FLAG_SDTR           1       /* Initiating synchronous 
 951                                            transfer negotiation */
 952 #define CMD_FLAG_WDTR           2       /* Initiating wide transfer
 953                                            negotiation */
 954 #define CMD_FLAG_DID_SDTR       4       /* did SDTR */
 955 
 956 struct NCR53c7x0_table_indirect {
 957     u32 count;
 958     void *address;
 959 };
 960 
 961 struct NCR53c7x0_cmd {
 962     void *real;                         /* Real, unaligned address */
 963     void (* free)(void *);              /* Command to deallocate; NULL
 964                                            for structures allocated with
 965                                            scsi_register, etc. */
 966     Scsi_Cmnd *cmd;                     /* Associated Scsi_Cmnd 
 967                                            structure, Scsi_Cmnd points
 968                                            at NCR53c7x0_cmd using 
 969                                            host_scribble structure */
 970 
 971     int size;                           /* scsi_malloc'd size of this 
 972                                            structure */
 973 
 974     int flags;
 975 
 976     unsigned char select[11];           /* Select message, includes
 977                                            IDENTIFY
 978                                            (optional) QUEUE TAG
 979                                            (optional) SDTR or WDTR
 980                                          */
 981 
 982 
 983     volatile struct NCR53c7x0_cmd *next, *prev; 
 984                                         /* Linux maintained lists.  Note that
 985                                            hostdata->free is a singly linked
 986                                            list; the rest are doubly linked */
 987                                          
 988 
 989     long dsa_size; /* Size of DSA structure */
 990 
 991     u32 *data_transfer_start;           /* Start of data transfer routines */
 992     u32 *data_transfer_end;             /* Address after end of data transfer o
 993                                            routines */
 994 
 995     u32 residual[8];                    /* Residual data transfer
 996                                            shadow of data_transfer code.
 997 
 998                                            Has instruction with modified
 999                                            DBC field followed by jump to 
1000                                            CALL routine following command.
1001                                          */
1002              
1003     u32 dsa[0];                         /* Variable length (depending
1004                                            on host type, number of scatter /
1005                                            gather buffers, etc).  */
1006 };
1007 
1008 struct NCR53c7x0_break {
1009     u32 *address, old_instruction[2];
1010     struct NCR53c7x0_break *next;
1011     unsigned char old_size;             /* Size of old instruction */
1012 };
1013 
1014 /* Indicates that the NCR is not executing code */
1015 #define STATE_HALTED    0               
1016 /* 
1017  * Indicates that the NCR is executing the wait for select / reselect 
1018  * script.  Only used when running NCR53c700 compatible scripts, only 
1019  * state during which an ABORT is _not_ considered an error condition.
1020  */
1021 #define STATE_WAITING   1               
1022 /* Indicates that the NCR is executing other code. */
1023 #define STATE_RUNNING   2               
1024 /* 
1025  * Indicates that the NCR was being aborted.
1026  */
1027 #define STATE_ABORTING  3
1028 /* 
1029  * Indicates that the NCR was successfully aborted. */
1030 #define STATE_ABORTED 4
1031     
1032 
1033 /* 
1034  * Where knowledge of SCSI SCRIPT(tm) specified values are needed 
1035  * in an interrupt handler, an interrupt handler exists for each 
1036  * different SCSI script so we don't have name space problems.
1037  * 
1038  * Return values of these handlers are as follows : 
1039  */
1040 #define SPECIFIC_INT_NOTHING    0       /* don't even restart */
1041 #define SPECIFIC_INT_RESTART    1       /* restart at the next instruction */
1042 #define SPECIFIC_INT_ABORT      2       /* recoverable error, abort cmd */
1043 #define SPECIFIC_INT_PANIC      3       /* unrecoverable error, panic */
1044 #define SPECIFIC_INT_DONE       4       /* normal command completion */
1045 #define SPECIFIC_INT_BREAK      5       /* break point encountered */
1046 
1047 struct NCR53c7x0_hostdata {
1048     int size;                           /* Size of entire Scsi_Host
1049                                            structure */
1050     struct Scsi_Host *next;             /* next of this type */
1051     int board;                          /* set to board type, useful if 
1052                                            we have host specific things,
1053                                            ie, a general purpose I/O 
1054                                            bit is being used to enable
1055                                            termination, etc. */
1056 
1057     int chip;                           /* set to chip type */
1058         /*
1059          * NCR53c700 = 700
1060          * NCR53c700-66 = 70066
1061          * NCR53c710 = 710
1062          * NCR53c720 = 720 
1063          * NCR53c810 = 810
1064          */
1065 
1066     /*
1067      * PCI bus, device, function, only for NCR53c8x0 chips.
1068      * pci_valid indicates that the PCI configuration information
1069      * is valid, and we can twiddle MAX_LAT, etc. as recommended
1070      * for maximum performance in the NCR documentation.
1071      */
1072     unsigned char pci_bus, pci_device_fn;
1073     unsigned pci_valid:1;
1074 
1075     u32 *dsp;                           /* dsp to restart with after
1076                                            all stacked interrupts are
1077                                            handled. */
1078 
1079     unsigned dsp_changed:1;             /* Has dsp changed within this
1080                                            set of stacked interrupts ? */
1081 
1082     unsigned char dstat;                /* Most recent value of dstat */
1083     unsigned dstat_valid:1;
1084 
1085     unsigned expecting_iid:1;           /* Expect IID interrupt */
1086     unsigned expecting_sto:1;           /* Expect STO interrupt */
1087     
1088     /* 
1089      * The code stays cleaner if we use variables with function
1090      * pointers and offsets that are unique for the different
1091      * scripts rather than having a slew of switch(hostdata->chip) 
1092      * statements.
1093      * 
1094      * It also means that the #defines from the SCSI SCRIPTS(tm)
1095      * don't have to be visible outside of the script-specific
1096      * instructions, preventing name space pollution.
1097      */
1098 
1099     void (* init_fixup)(struct Scsi_Host *host);
1100     void (* init_save_regs)(struct Scsi_Host *host);
1101     void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1102     void (* soft_reset)(struct Scsi_Host *host);
1103     int (* run_tests)(struct Scsi_Host *host);
1104 
1105     /*
1106      * Called when DSTAT_SIR is set, indicating an interrupt generated
1107      * by the INT instruction, where values are unique for each SCSI
1108      * script.  Should return one of the SPEC_* values.
1109      */
1110 
1111     int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1112 
1113     long dsa_size; /* Size of DSA structure */
1114 
1115     /*
1116      * Location of DSA fields for the SCSI SCRIPT corresponding to this 
1117      * chip.  
1118      */
1119 
1120     s32 dsa_start;                      
1121     s32 dsa_end;                        
1122     s32 dsa_next;
1123     s32 dsa_prev;
1124     s32 dsa_cmnd;
1125     s32 dsa_select;
1126     s32 dsa_msgout;
1127     s32 dsa_cmdout;
1128     s32 dsa_dataout;
1129     s32 dsa_datain;
1130     s32 dsa_msgin;
1131     s32 dsa_msgout_other;
1132     s32 dsa_write_sync;
1133     s32 dsa_write_resume;
1134     s32 dsa_jump_resume;
1135     s32 dsa_check_reselect;
1136     s32 dsa_status;
1137 
1138     /* 
1139      * Important entry points that generic fixup code needs
1140      * to know about, fixed up.
1141      */
1142 
1143     s32 E_accept_message;
1144     s32 E_dsa_code_template;
1145     s32 E_dsa_code_template_end;
1146     s32 E_command_complete;             
1147     s32 E_msg_in;
1148     s32 E_initiator_abort;
1149     s32 E_other_transfer;
1150     s32 E_target_abort;
1151     s32 E_schedule;                     
1152     s32 E_debug_break;  
1153     s32 E_reject_message;
1154     s32 E_respond_message;
1155     s32 E_select;
1156     s32 E_select_msgout;
1157     s32 E_test_0;
1158     s32 E_test_1;
1159     s32 E_test_2;
1160     s32 E_test_3;
1161     s32 E_dsa_zero;
1162     s32 E_dsa_jump_resume;
1163 
1164     int options;                        /* Bitfielded set of options enabled */
1165     volatile u32 test_completed;        /* Test completed */
1166     int test_running;                   /* Test currently running */
1167     int test_source;
1168     volatile int test_dest;
1169 
1170     volatile int state;                 /* state of driver, only used for 
1171                                            OPTION_700 */
1172 
1173     unsigned char  dmode;               /* 
1174                                          * set to the address of the DMODE 
1175                                          * register for this chip.
1176                                          */
1177     unsigned char istat;                /* 
1178                                          * set to the address of the ISTAT 
1179                                          * register for this chip.
1180                                          */
1181   
1182     int scsi_clock;                     /* 
1183                                          * SCSI clock in HZ. 0 may be used 
1184                                          * for unknown, although this will
1185                                          * disable synchronous negotiation.
1186                                          */
1187 
1188     volatile int intrs;                 /* Number of interrupts */
1189     unsigned char saved_dmode;  
1190     unsigned char saved_ctest4;
1191     unsigned char saved_ctest7;
1192     unsigned char saved_dcntl;
1193     unsigned char saved_scntl3;
1194 
1195     unsigned char this_id_mask;
1196 
1197     /* Debugger information */
1198     struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1199         *breakpoint_current;            /* Current breakpoint being stepped 
1200                                            through, NULL if we are running 
1201                                            normally. */
1202 #ifdef NCR_DEBUG
1203     int debug_size;                     /* Size of debug buffer */
1204     volatile int debug_count;           /* Current data count */
1205     volatile char *debug_buf;           /* Output ring buffer */
1206     volatile char *debug_write;         /* Current write pointer */
1207     volatile char *debug_read;          /* Current read pointer */
1208 #endif /* def NCR_DEBUG */
1209 
1210     /* XXX - primitive debugging junk, remove when working ? */
1211     int debug_print_limit;              /* Number of commands to print
1212                                            out exhaustive debugging
1213                                            information for if 
1214                                            OPTION_DEBUG_DUMP is set */ 
1215 
1216     unsigned char debug_lun_limit[8];   /* If OPTION_DEBUG_TARGET_LIMIT
1217                                            set, puke if commands are sent
1218                                            to other target/lun combinations */
1219 
1220     int debug_count_limit;              /* Number of commands to execute
1221                                            before puking to limit debugging 
1222                                            output */
1223                                     
1224 
1225     volatile unsigned idle:1;                   /* set to 1 if idle */
1226 
1227     /* 
1228      * Table of synchronous transfer parameters set on a per-target
1229      * basis.
1230      * 
1231      * XXX - do we need to increase this to 16 for the WIDE-SCSI
1232      * flavors of the board?
1233      */
1234     
1235     volatile struct NCR53c7x0_synchronous sync[8];
1236 
1237     volatile struct NCR53c7x0_cmd *issue_queue;
1238                                                 /* waiting to be issued by
1239                                                    Linux driver */
1240     volatile struct NCR53c7x0_cmd *running_list;        
1241                                                 /* commands running, maintained
1242                                                    by Linux driver */
1243     volatile struct NCR53c7x0_cmd *current_cmd; /* currently connected 
1244                                                    nexus, ONLY valid for
1245                                                    NCR53c700/NCR53c700-66
1246                                                  */
1247 
1248     volatile struct NCR53c7x0_cmd *spare;       /* pointer to spare,
1249                                                    allocated at probe time,
1250                                                    which we can use for 
1251                                                    initialization */
1252     volatile struct NCR53c7x0_cmd *free;
1253     int max_cmd_size;                           /* Maximum size of NCR53c7x0_cmd
1254                                                    based on number of 
1255                                                    scatter/gather segments, etc.
1256                                                    */
1257     volatile int num_cmds;                      /* Number of commands 
1258                                                    allocated */
1259     volatile unsigned char cmd_allocated[8];    /* Have we allocated commands
1260                                                    for this target yet?  If not,
1261                                                    do so ASAP */
1262     volatile unsigned char busy[8][8];          /* number of commands 
1263                                                    executing on each target
1264                                                  */
1265     /* 
1266      * Eventually, I'll switch to a coroutine for calling 
1267      * cmd->done(cmd), etc. so that we can overlap interrupt
1268      * processing with this code for maximum performance.
1269      */
1270     
1271     volatile struct NCR53c7x0_cmd *finished_queue;      
1272                                                 
1273 
1274     /* Shared variables between SCRIPT and host driver */
1275     volatile u32 issue_dsa_head;
1276                                                 /* commands waiting to be 
1277                                                    issued, insertions are 
1278                                                    done by Linux driver,
1279                                                    deletions are done by
1280                                                    NCR */
1281     u32 *issue_dsa_tail;                        /* issue queue tail pointer;
1282                                                    used by Linux driver only */
1283     volatile unsigned char msg_buf[16];         /* buffer for messages
1284                                                    other than the command
1285                                                    complete message */
1286     volatile u32 reconnect_dsa_head;
1287                                                 /* disconnected commands,
1288                                                    maintained by NCR */
1289     /* Data identifying nexus we are trying to match during reselection */
1290     volatile unsigned char reselected_identify; /* IDENTIFY message */
1291     volatile unsigned char reselected_tag;      /* second byte of queue tag 
1292                                                    message or 0 */
1293     /* These were static variables before we moved them */
1294 
1295     s32 NCR53c7xx_zero;
1296     s32 NCR53c7xx_sink;
1297     char NCR53c7xx_msg_reject;
1298     char NCR53c7xx_msg_abort;
1299     char NCR53c7xx_msg_nop;
1300 
1301     int script_count;                           /* Size of script in words */
1302     u32 script[0];                              /* Relocated SCSI script */
1303 
1304 };
1305 
1306 #define IRQ_NONE        255
1307 #define DMA_NONE        255
1308 #define IRQ_AUTO        254
1309 #define DMA_AUTO        254
1310 
1311 #define BOARD_GENERIC   0
1312 
1313 #define NCR53c7x0_insn_size(insn)                                       \
1314     (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1315     
1316 
1317 #define NCR53c7x0_local_declare()                                       \
1318     volatile unsigned char *NCR53c7x0_address_memory;                   \
1319     unsigned int NCR53c7x0_address_io;                                  \
1320     int NCR53c7x0_memory_mapped
1321 
1322 #define NCR53c7x0_local_setup(host)                                     \
1323     NCR53c7x0_address_memory = (void *) (host)->base;                   \
1324     NCR53c7x0_address_io = (unsigned int) (host)->io_port;              \
1325     NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *)            \
1326         host->hostdata)-> options & OPTION_MEMORY_MAPPED 
1327 
1328 #define NCR53c7x0_read8(address)                                        \
1329     (NCR53c7x0_memory_mapped ?                                          \
1330         ncr_readb(NCR53c7x0_address_memory + (address))  :              \
1331         inb(NCR53c7x0_address_io + (address)))
1332 
1333 #define NCR53c7x0_read16(address)                                       \
1334     (NCR53c7x0_memory_mapped ?                                          \
1335         ncr_readw(NCR53c7x0_address_memory + (address))  :              \
1336         inw(NCR53c7x0_address_io + (address)))
1337 
1338 #define NCR53c7x0_read32(address)                                       \
1339     (NCR53c7x0_memory_mapped ?                                          \
1340         ncr_readl(NCR53c7x0_address_memory + (address))  :              \
1341         inl(NCR53c7x0_address_io + (address)))
1342 
1343 #define NCR53c7x0_write8(address,value)                                 \
1344     (NCR53c7x0_memory_mapped ?                                          \
1345         ncr_writeb((value), NCR53c7x0_address_memory + (address)) :     \
1346         outb((value), NCR53c7x0_address_io + (address)))
1347 
1348 #define NCR53c7x0_write16(address,value)                                \
1349     (NCR53c7x0_memory_mapped ?                                          \
1350         ncr_writew((value), NCR53c7x0_address_memory + (address)) :     \
1351         outw((value), NCR53c7x0_address_io + (address)))
1352 
1353 #define NCR53c7x0_write32(address,value)                                \
1354     (NCR53c7x0_memory_mapped ?                                          \
1355         ncr_writel((value), NCR53c7x0_address_memory + (address)) :     \
1356         outl((value), NCR53c7x0_address_io + (address)))
1357 
1358 #define patch_abs_32(script, offset, symbol, value)                     \
1359         for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof            \
1360             (u32)); ++i) {                                              \
1361             (script)[A_##symbol##_used[i] - (offset)] += (value);       \
1362             if (hostdata->options & OPTION_DEBUG_FIXUP)                 \
1363               printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1364                 host->host_no, #symbol, i, A_##symbol##_used[i] -       \
1365                 (int)(offset), #script, (script)[A_##symbol##_used[i] - \
1366                 (offset)]);                                             \
1367         }
1368 
1369 #define patch_abs_rwri_data(script, offset, symbol, value)              \
1370         for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof            \
1371             (u32)); ++i)                                                \
1372             (script)[A_##symbol##_used[i] - (offset)] =                 \
1373                 ((script)[A_##symbol##_used[i] - (offset)] &            \
1374                 ~DBC_RWRI_IMMEDIATE_MASK) |                             \
1375                 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) &                \
1376                  DBC_RWRI_IMMEDIATE_MASK)
1377 
1378 #define patch_dsa_32(dsa, symbol, word, value)                          \
1379         {                                                               \
1380         (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(u32)  \
1381                 + (word)] = (value);                                    \
1382         if (hostdata->options & OPTION_DEBUG_DSA)                       \
1383             printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n",    \
1384                 #dsa, #symbol, hostdata->##symbol,                      \
1385                 (word), (u32)(value));                          \
1386         }
1387     
1388 
1389 
1390 #endif /* NCR53c7x0_C */
1391 #endif /* NCR53c7x0_H */

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