This source file includes following definitions.
- virt_to_bus
- bus_to_virt
- __inb
- __outb
- __inw
- __outw
- __inl
- __outl
- __readb
- __readw
- __readl
- __writeb
- __writew
- __writel
1 #ifndef __ALPHA_LCA__H__
2 #define __ALPHA_LCA__H__
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55 #include <asm/system.h>
56
57 #define LCA_DMA_WIN_BASE (1024*1024*1024)
58 #define LCA_DMA_WIN_SIZE (1024*1024*1024)
59
60
61
62
63 #define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL)
64 #define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL)
65 #define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL)
66 #define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL)
67 #define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL)
68 #define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL)
69 #define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL)
70 #define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL)
71 #define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL)
72 #define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL)
73 #define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL)
74 #define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL)
75 #define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL)
76 #define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL)
77 #define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL)
78 #define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL)
79 #define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL)
80 #define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL)
81 #define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL)
82
83
84
85
86 #define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL)
87 #define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL)
88 #define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL)
89 #define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL)
90 #define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL)
91 #define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL)
92 #define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
93 #define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL)
94 #define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL)
95 #define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL)
96 #define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL)
97 #define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL)
98 #define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL)
99 #define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL)
100 #define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL)
101 #define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL)
102 #define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL)
103 #define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL)
104 #define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL)
105 #define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL)
106 #define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL)
107 #define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL)
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112 #define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL)
113 #define LCA_CONF (IDENT_ADDR + 0x1e0000000UL)
114 #define LCA_IO (IDENT_ADDR + 0x1c0000000UL)
115 #define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
116 #define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
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120
121 #define LCA_IOC_STAT0_CMD 0xf
122 #define LCA_IOC_STAT0_ERR (1<<4)
123 #define LCA_IOC_STAT0_LOST (1<<5)
124 #define LCA_IOC_STAT0_THIT (1<<6)
125 #define LCA_IOC_STAT0_TREF (1<<7)
126 #define LCA_IOC_STAT0_CODE_SHIFT 8
127 #define LCA_IOC_STAT0_CODE_MASK 0x7
128 #define LCA_IOC_STAT0_P_NBR_SHIFT 13
129 #define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff
130
131 #define HAE_ADDRESS LCA_IOC_HAE
132
133 #ifdef __KERNEL__
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138
139 extern inline unsigned long virt_to_bus(void * address)
140 {
141 return virt_to_phys(address) + LCA_DMA_WIN_BASE;
142 }
143
144 extern inline void * bus_to_virt(unsigned long address)
145 {
146 return phys_to_virt(address - LCA_DMA_WIN_BASE);
147 }
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159
160 #define vuip volatile unsigned int *
161
162 extern inline unsigned int __inb(unsigned long addr)
163 {
164 long result = *(vuip) ((addr << 5) + LCA_IO + 0x00);
165 result >>= (addr & 3) * 8;
166 return 0xffUL & result;
167 }
168
169 extern inline void __outb(unsigned char b, unsigned long addr)
170 {
171 unsigned int w;
172
173 asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
174 *(vuip) ((addr << 5) + LCA_IO + 0x00) = w;
175 mb();
176 }
177
178 extern inline unsigned int __inw(unsigned long addr)
179 {
180 long result = *(vuip) ((addr << 5) + LCA_IO + 0x08);
181 result >>= (addr & 3) * 8;
182 return 0xffffUL & result;
183 }
184
185 extern inline void __outw(unsigned short b, unsigned long addr)
186 {
187 unsigned int w;
188
189 asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
190 *(vuip) ((addr << 5) + LCA_IO + 0x08) = w;
191 mb();
192 }
193
194 extern inline unsigned int __inl(unsigned long addr)
195 {
196 return *(vuip) ((addr << 5) + LCA_IO + 0x18);
197 }
198
199 extern inline void __outl(unsigned int b, unsigned long addr)
200 {
201 *(vuip) ((addr << 5) + LCA_IO + 0x18) = b;
202 mb();
203 }
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209
210 extern inline unsigned long __readb(unsigned long addr)
211 {
212 unsigned long result, shift, msb;
213
214 shift = (addr & 0x3) * 8;
215 if (addr >= (1UL << 24)) {
216 msb = addr & 0xf8000000;
217 addr -= msb;
218 if (msb != hae.cache) {
219 set_hae(msb);
220 }
221 }
222 result = *(vuip) ((addr << 5) + LCA_SPARSE_MEM + 0x00);
223 result >>= shift;
224 return 0xffUL & result;
225 }
226
227 extern inline unsigned long __readw(unsigned long addr)
228 {
229 unsigned long result, shift, msb;
230
231 shift = (addr & 0x3) * 8;
232 if (addr >= (1UL << 24)) {
233 msb = addr & 0xf8000000;
234 addr -= msb;
235 if (msb != hae.cache) {
236 set_hae(msb);
237 }
238 }
239 result = *(vuip) ((addr << 5) + LCA_SPARSE_MEM + 0x08);
240 result >>= shift;
241 return 0xffffUL & result;
242 }
243
244 extern inline unsigned long __readl(unsigned long addr)
245 {
246 return *(vuip) (addr + LCA_DENSE_MEM);
247 }
248
249 extern inline void __writeb(unsigned char b, unsigned long addr)
250 {
251 unsigned long msb;
252 unsigned int w;
253
254 if (addr >= (1UL << 24)) {
255 msb = addr & 0xf8000000;
256 addr -= msb;
257 if (msb != hae.cache) {
258 set_hae(msb);
259 }
260 }
261 asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
262 *(vuip) ((addr << 5) + LCA_SPARSE_MEM + 0x00) = w;
263 }
264
265 extern inline void __writew(unsigned short b, unsigned long addr)
266 {
267 unsigned long msb;
268 unsigned int w;
269
270 if (addr >= (1UL << 24)) {
271 msb = addr & 0xf8000000;
272 addr -= msb;
273 if (msb != hae.cache) {
274 set_hae(msb);
275 }
276 }
277 asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
278 *(vuip) ((addr << 5) + LCA_SPARSE_MEM + 0x08) = w;
279 }
280
281 extern inline void __writel(unsigned int b, unsigned long addr)
282 {
283 *(vuip) (addr + LCA_DENSE_MEM) = b;
284 }
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291 #define inb(port) \
292 (__builtin_constant_p((port))?__inb(port):_inb(port))
293
294 #define outb(x, port) \
295 (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
296
297 #define readl(a) __readl((unsigned long)(a))
298 #define writel(v,a) __writel((v),(unsigned long)(a))
299
300 #undef vuip
301
302 extern unsigned long lca_init (unsigned long mem_start, unsigned long mem_end);
303
304 #endif
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308
309
310 struct el_lca_mcheck_short {
311 struct el_common h;
312 unsigned long reason;
313 unsigned long esr;
314 unsigned long ear;
315 unsigned long dc_stat;
316 unsigned long ioc_stat0;
317 unsigned long ioc_stat1;
318 };
319
320 struct el_lca_mcheck_long {
321 struct el_common h;
322 unsigned long pt[32];
323 unsigned long exc_addr;
324 unsigned long pad1[3];
325 unsigned long pal_base;
326 unsigned long hier;
327 unsigned long hirr;
328 unsigned long mm_csr;
329 unsigned long dc_stat;
330 unsigned long dc_addr;
331 unsigned long abox_ctl;
332 unsigned long esr;
333 unsigned long ear;
334 unsigned long car;
335 unsigned long ioc_stat0;
336 unsigned long ioc_stat1;
337 unsigned long va;
338 };
339
340 union el_lca {
341 struct el_common * c;
342 struct el_lca_mcheck_long * l;
343 struct el_lca_mcheck_short * s;
344 };
345
346 #define RTC_PORT(x) (0x70 + (x))
347 #define RTC_ADDR(x) (0x80 | (x))
348 #define RTC_ALWAYS_BCD 0
349
350 #endif