include/asm-alpha/apecs.h

/* */
This source file includes following definitions.
virt_to_bus
bus_to_virt
__inb
__outb
__inw
__outw
__inl
__outl
__readb
__readw
__readl
__writeb
__writew
__writel
   1 #ifndef __ALPHA_APECS__H__
   2 #define __ALPHA_APECS__H__
   3 
   4 #include <linux/types.h>
   5 
   6 /*
   7  * APECS is the internal name for the 2107x chipset which provides
   8  * memory controller and PCI access for the 21064 chip based systems.
   9  *
  10  * This file is based on:
  11  *
  12  * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
  13  * Data Sheet
  14  *
  15  * EC-N0648-72
  16  *
  17  *
  18  * david.rusling@reo.mts.dec.com Initial Version.
  19  *
  20  */
  21 
  22 #define APECS_DMA_WIN_BASE      (1024*1024*1024)
  23 #define APECS_DMA_WIN_SIZE      (1024*1024*1024)
  24 
  25 /*
  26  * 21071-DA Control and Status registers.
  27  * These are used for PCI memory access.
  28  */
  29 #define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)
  30 #define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)
  31 #define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)
  32 #define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)
  33 #define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)
  34 #define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)
  35 
  36 #define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)
  37 #define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)
  38 
  39 #define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)
  40 #define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)
  41 
  42 #define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)
  43 #define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)
  44 
  45 #define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)
  46 #define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)
  47 #define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)
  48 
  49 #define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)
  50 
  51 #define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)
  52 #define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)
  53 #define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)
  54 #define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)
  55 #define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)
  56 #define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)
  57 #define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)
  58 #define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)
  59 
  60 #define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)
  61 #define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)
  62 #define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)
  63 #define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)
  64 #define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)
  65 #define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)
  66 #define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)
  67 #define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)
  68 
  69 #define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)
  70 
  71 
  72 /*
  73  * 21071-CA Control and Status registers.
  74  * These are used to program memory timing,
  75  *  configure memory and initialise the B-Cache.
  76  */
  77 #define APECS_IOC_GCR                   (IDENT_ADDR + 0x180000000UL)
  78 #define APECS_IOC_EDSR                  (IDENT_ADDR + 0x180000040UL)
  79 #define APECS_IOC_TAR                   (IDENT_ADDR + 0x180000060UL)
  80 #define APECS_IOC_ELAR                  (IDENT_ADDR + 0x180000080UL)
  81 #define APECS_IOC_EHAR                  (IDENT_ADDR + 0x1800000a0UL)
  82 #define APECS_IOC_SFT_RST               (IDENT_ADDR + 0x1800000c0UL)
  83 #define APECS_IOC_LDxLAR                (IDENT_ADDR + 0x1800000e0UL)
  84 #define APECS_IOC_LDxHAR                (IDENT_ADDR + 0x180000100UL)
  85 #define APECS_IOC_GTR                   (IDENT_ADDR + 0x180000200UL)
  86 #define APECS_IOC_RTR                   (IDENT_ADDR + 0x180000220UL)
  87 #define APECS_IOC_VFPR                  (IDENT_ADDR + 0x180000240UL)
  88 #define APECS_IOC_PDLDR                 (IDENT_ADDR + 0x180000260UL)
  89 #define APECS_IOC_PDhDR                 (IDENT_ADDR + 0x180000280UL)
  90 
  91 /* Bank x Base Address Register */
  92 #define APECS_IOC_B0BAR                 (IDENT_ADDR + 0x180000800UL)
  93 #define APECS_IOC_B1BAR                 (IDENT_ADDR + 0x180000820UL)
  94 #define APECS_IOC_B2BAR                 (IDENT_ADDR + 0x180000840UL)
  95 #define APECS_IOC_B3BAR                 (IDENT_ADDR + 0x180000860UL)
  96 #define APECS_IOC_B4BAR                 (IDENT_ADDR + 0x180000880UL)
  97 #define APECS_IOC_B5BAR                 (IDENT_ADDR + 0x1800008A0UL)
  98 #define APECS_IOC_B6BAR                 (IDENT_ADDR + 0x1800008C0UL)
  99 #define APECS_IOC_B7BAR                 (IDENT_ADDR + 0x1800008E0UL)
 100 #define APECS_IOC_B8BAR                 (IDENT_ADDR + 0x180000900UL)
 101 
 102 /* Bank x Configuration Register */
 103 #define APECS_IOC_B0BCR                 (IDENT_ADDR + 0x180000A00UL)
 104 #define APECS_IOC_B1BCR                 (IDENT_ADDR + 0x180000A20UL)
 105 #define APECS_IOC_B2BCR                 (IDENT_ADDR + 0x180000A40UL)
 106 #define APECS_IOC_B3BCR                 (IDENT_ADDR + 0x180000A60UL)
 107 #define APECS_IOC_B4BCR                 (IDENT_ADDR + 0x180000A80UL)
 108 #define APECS_IOC_B5BCR                 (IDENT_ADDR + 0x180000AA0UL)
 109 #define APECS_IOC_B6BCR                 (IDENT_ADDR + 0x180000AC0UL)
 110 #define APECS_IOC_B7BCR                 (IDENT_ADDR + 0x180000AE0UL)
 111 #define APECS_IOC_B8BCR                 (IDENT_ADDR + 0x180000B00UL)
 112 
 113 /* Bank x Timing Register A */
 114 #define APECS_IOC_B0TRA                 (IDENT_ADDR + 0x180000C00UL)
 115 #define APECS_IOC_B1TRA                 (IDENT_ADDR + 0x180000C20UL)
 116 #define APECS_IOC_B2TRA                 (IDENT_ADDR + 0x180000C40UL)
 117 #define APECS_IOC_B3TRA                 (IDENT_ADDR + 0x180000C60UL)
 118 #define APECS_IOC_B4TRA                 (IDENT_ADDR + 0x180000C80UL)
 119 #define APECS_IOC_B5TRA                 (IDENT_ADDR + 0x180000CA0UL)
 120 #define APECS_IOC_B6TRA                 (IDENT_ADDR + 0x180000CC0UL)
 121 #define APECS_IOC_B7TRA                 (IDENT_ADDR + 0x180000CE0UL)
 122 #define APECS_IOC_B8TRA                 (IDENT_ADDR + 0x180000D00UL)
 123 
 124 /* Bank x Timing Register B */
 125 #define APECS_IOC_B0TRB                 (IDENT_ADDR + 0x180000E00UL)
 126 #define APECS_IOC_B1TRB                 (IDENT_ADDR + 0x180000E20UL)
 127 #define APECS_IOC_B2TRB                 (IDENT_ADDR + 0x180000E40UL)
 128 #define APECS_IOC_B3TRB                 (IDENT_ADDR + 0x180000E60UL)
 129 #define APECS_IOC_B4TRB                 (IDENT_ADDR + 0x180000E80UL)
 130 #define APECS_IOC_B5TRB                 (IDENT_ADDR + 0x180000EA0UL)
 131 #define APECS_IOC_B6TRB                 (IDENT_ADDR + 0x180000EC0UL)
 132 #define APECS_IOC_B7TRB                 (IDENT_ADDR + 0x180000EE0UL)
 133 #define APECS_IOC_B8TRB                 (IDENT_ADDR + 0x180000F00UL)
 134 
 135 
 136 /*
 137  * Memory spaces:
 138  */
 139 #define APECS_IACK_SC                   (IDENT_ADDR + 0x1b0000000UL)
 140 #define APECS_CONF                      (IDENT_ADDR + 0x1e0000000UL)
 141 #define APECS_IO                        (IDENT_ADDR + 0x1c0000000UL)
 142 #define APECS_SPARSE_MEM                (IDENT_ADDR + 0x200000000UL)
 143 #define APECS_DENSE_MEM                 (IDENT_ADDR + 0x300000000UL)
 144 
 145 /*
 146  * Bit definitions for I/O Controller status register 0:
 147  */
 148 #define APECS_IOC_STAT0_CMD             0xf
 149 #define APECS_IOC_STAT0_ERR             (1<<4)
 150 #define APECS_IOC_STAT0_LOST            (1<<5)
 151 #define APECS_IOC_STAT0_THIT            (1<<6)
 152 #define APECS_IOC_STAT0_TREF            (1<<7)
 153 #define APECS_IOC_STAT0_CODE_SHIFT      8
 154 #define APECS_IOC_STAT0_CODE_MASK       0x7
 155 #define APECS_IOC_STAT0_P_NBR_SHIFT     13
 156 #define APECS_IOC_STAT0_P_NBR_MASK      0x7ffff
 157 
 158 #define HAE_ADDRESS     APECS_IOC_HAXR1
 159 
 160 #ifdef __KERNEL__
 161 
 162 /*
 163  * Translate physical memory address as seen on (PCI) bus into
 164  * a kernel virtual address and vv.
 165  */
 166 extern inline unsigned long virt_to_bus(void * address)
     /*  */
 167 {
 168         return virt_to_phys(address) + APECS_DMA_WIN_BASE;
 169 }
 170 
 171 extern inline void * bus_to_virt(unsigned long address)
     /*  */
 172 {
 173         return phys_to_virt(address - APECS_DMA_WIN_BASE);
 174 }
 175 
 176 /*
 177  * I/O functions:
 178  *
 179  * Unlike Jensen, the APECS machines have no concept of local
 180  * I/O---everything goes over the PCI bus.
 181  *
 182  * There is plenty room for optimization here.  In particular,
 183  * the Alpha's insb/insw/extb/extw should be useful in moving
 184  * data to/from the right byte-lanes.
 185  */
 186 
 187 #define vuip    volatile unsigned int *
 188 
 189 extern inline unsigned int __inb(unsigned long addr)
     /*  */
 190 {
 191         long result = *(vuip) ((addr << 5) + APECS_IO + 0x00);
 192         result >>= (addr & 3) * 8;
 193         return 0xffUL & result;
 194 }
 195 
 196 extern inline void __outb(unsigned char b, unsigned long addr)
     /*  */
 197 {
 198         unsigned int w;
 199 
 200         asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
 201         *(vuip) ((addr << 5) + APECS_IO + 0x00) = w;
 202         mb();
 203 }
 204 
 205 extern inline unsigned int __inw(unsigned long addr)
     /*  */
 206 {
 207         long result = *(vuip) ((addr << 5) + APECS_IO + 0x08);
 208         result >>= (addr & 3) * 8;
 209         return 0xffffUL & result;
 210 }
 211 
 212 extern inline void __outw(unsigned short b, unsigned long addr)
     /*  */
 213 {
 214         unsigned int w;
 215 
 216         asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
 217         *(vuip) ((addr << 5) + APECS_IO + 0x08) = w;
 218         mb();
 219 }
 220 
 221 extern inline unsigned int __inl(unsigned long addr)
     /*  */
 222 {
 223         return *(vuip) ((addr << 5) + APECS_IO + 0x18);
 224 }
 225 
 226 extern inline void __outl(unsigned int b, unsigned long addr)
     /*  */
 227 {
 228         *(vuip) ((addr << 5) + APECS_IO + 0x18) = b;
 229         mb();
 230 }
 231 
 232 
 233 /*
 234  * Memory functions.  64-bit and 32-bit accesses are done through
 235  * dense memory space, everything else through sparse space.
 236  */
 237 extern inline unsigned long __readb(unsigned long addr)
     /*  */
 238 {
 239         unsigned long result, shift, msb;
 240 
 241         shift = (addr & 0x3) * 8;
 242         if (addr >= (1UL << 24)) {
 243                 msb = addr & 0xf8000000;
 244                 addr -= msb;
 245                 if (msb != hae.cache) {
 246                         set_hae(msb);
 247                 }
 248         }
 249         result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00);
 250         result >>= shift;
 251         return 0xffUL & result;
 252 }
 253 
 254 extern inline unsigned long __readw(unsigned long addr)
     /*  */
 255 {
 256         unsigned long result, shift, msb;
 257 
 258         shift = (addr & 0x3) * 8;
 259         if (addr >= (1UL << 24)) {
 260                 msb = addr & 0xf8000000;
 261                 addr -= msb;
 262                 if (msb != hae.cache) {
 263                         set_hae(msb);
 264                 }
 265         }
 266         result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08);
 267         result >>= shift;
 268         return 0xffffUL & result;
 269 }
 270 
 271 extern inline unsigned long __readl(unsigned long addr)
     /*  */
 272 {
 273         return *(vuip) (addr + APECS_DENSE_MEM);
 274 }
 275 
 276 extern inline void __writeb(unsigned char b, unsigned long addr)
     /*  */
 277 {
 278         unsigned long msb;
 279 
 280         if (addr >= (1UL << 24)) {
 281                 msb = addr & 0xf8000000;
 282                 addr -= msb;
 283                 if (msb != hae.cache) {
 284                         set_hae(msb);
 285                 }
 286         }
 287         *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00) = b * 0x01010101;
 288 }
 289 
 290 extern inline void __writew(unsigned short b, unsigned long addr)
     /*  */
 291 {
 292         unsigned long msb;
 293 
 294         if (addr >= (1UL << 24)) {
 295                 msb = addr & 0xf8000000;
 296                 addr -= msb;
 297                 if (msb != hae.cache) {
 298                         set_hae(msb);
 299                 }
 300         }
 301         *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08) = b * 0x00010001;
 302 }
 303 
 304 extern inline void __writel(unsigned int b, unsigned long addr)
     /*  */
 305 {
 306         *(vuip) (addr + APECS_DENSE_MEM) = b;
 307 }
 308 
 309 #define inb(port) \
 310 (__builtin_constant_p((port))?__inb(port):_inb(port))
 311 
 312 #define outb(x, port) \
 313 (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
 314 
 315 #define readl(a)        __readl((unsigned long)(a))
 316 #define writel(v,a)     __writel((v),(unsigned long)(a))
 317 
 318 #undef vuip
 319 
 320 extern unsigned long apecs_init (unsigned long mem_start,
 321                                  unsigned long mem_end);
 322 
 323 #endif /* __KERNEL__ */
 324 
 325 /*
 326  * Data structure for handling APECS machine checks:
 327  */
 328 struct el_apecs_sysdata_mcheck {
 329     u_long      coma_gcr;                       
 330     u_long      coma_edsr;                      
 331     u_long      coma_ter;                       
 332     u_long      coma_elar;                      
 333     u_long      coma_ehar;                      
 334     u_long      coma_ldlr;                      
 335     u_long      coma_ldhr;                      
 336     u_long      coma_base0;                     
 337     u_long      coma_base1;                     
 338     u_long      coma_base2;                     
 339     u_long      coma_cnfg0;                     
 340     u_long      coma_cnfg1;                     
 341     u_long      coma_cnfg2;                     
 342     u_long      epic_dcsr;                      
 343     u_long      epic_pear;                      
 344     u_long      epic_sear;                      
 345     u_long      epic_tbr1;                      
 346     u_long      epic_tbr2;                      
 347     u_long      epic_pbr1;                      
 348     u_long      epic_pbr2;                      
 349     u_long      epic_pmr1;                      
 350     u_long      epic_pmr2;                      
 351     u_long      epic_harx1;                     
 352     u_long      epic_harx2;                     
 353     u_long      epic_pmlt;                      
 354     u_long      epic_tag0;                      
 355     u_long      epic_tag1;                      
 356     u_long      epic_tag2;                      
 357     u_long      epic_tag3;                      
 358     u_long      epic_tag4;                      
 359     u_long      epic_tag5;                      
 360     u_long      epic_tag6;                      
 361     u_long      epic_tag7;                      
 362     u_long      epic_data0;                     
 363     u_long      epic_data1;                     
 364     u_long      epic_data2;                     
 365     u_long      epic_data3;                     
 366     u_long      epic_data4;                     
 367     u_long      epic_data5;                     
 368     u_long      epic_data6;                     
 369     u_long      epic_data7;                     
 370 };
 371 
 372 #define RTC_PORT(x)     (0x70 + (x))
 373 #define RTC_ADDR(x)     (0x80 | (x))
 374 #define RTC_ALWAYS_BCD  0
 375 
 376 #endif /* __ALPHA_APECS__H__ */
/* */
root/include/asm-alpha/apecs.h

INCLUDED FROM

DEFINITIONS
