This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
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129 static const char *version = "ewrk3.c:v0.32 1/16/95 davies@wanton.lkg.dec.com\n";
130
131 #include <linux/module.h>
132
133 #include <stdarg.h>
134
135 #include <linux/kernel.h>
136 #include <linux/sched.h>
137 #include <linux/string.h>
138 #include <linux/ptrace.h>
139 #include <linux/errno.h>
140 #include <linux/ioport.h>
141 #include <linux/malloc.h>
142 #include <linux/interrupt.h>
143 #include <linux/netdevice.h>
144 #include <linux/etherdevice.h>
145 #include <linux/skbuff.h>
146 #include <linux/time.h>
147 #include <linux/types.h>
148 #include <linux/unistd.h>
149
150 #include <asm/bitops.h>
151 #include <asm/io.h>
152 #include <asm/dma.h>
153 #include <asm/segment.h>
154
155 #include "ewrk3.h"
156
157 #ifdef EWRK3_DEBUG
158 static int ewrk3_debug = EWRK3_DEBUG;
159 #else
160 static int ewrk3_debug = 1;
161 #endif
162
163 #ifndef PROBE_LENGTH
164 #define PROBE_LENGTH 32
165 #endif
166
167 #ifndef PROBE_SEQUENCE
168 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
169 #endif
170
171 #ifndef EWRK3_SIGNATURE
172 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
173 #define EWRK3_NAME_LENGTH 8
174 #endif
175
176 #ifndef EWRK3_RAM_BASE_ADDRESSES
177 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
178 #endif
179
180
181
182
183
184
185
186
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190
191
192
193
194 #define EWRK3_IO_BASE 0x100
195 #define EWRK3_IOP_INC 0x20
196 #define EWRK3_TOTAL_SIZE 0x20
197 #define EWRK3_IO_SEARCH 0x007dff7f
198 static long mem_chkd = EWRK3_IO_SEARCH;
199
200
201 #ifndef MAX_NUM_EWRK3S
202 #define MAX_NUM_EWRK3S 21
203 #endif
204
205 #ifndef EWRK3_EISA_IO_PORTS
206 #define EWRK3_EISA_IO_PORTS 0x0c00
207 #endif
208
209 #ifndef MAX_EISA_SLOTS
210 #define MAX_EISA_SLOTS 8
211 #define EISA_SLOT_INC 0x1000
212 #endif
213
214 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
215 #define CRC_POLYNOMIAL_LE 0xedb88320UL
216
217
218
219
220 #define IO_ONLY 0x00
221 #define SHMEM_2K 0x800
222 #define SHMEM_32K 0x8000
223 #define SHMEM_64K 0x10000
224
225
226
227
228 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
229
230 #define ENABLE_IRQs \
231 icr |= irq_mask;\
232 outb(icr, EWRK3_ICR)
233
234 #define DISABLE_IRQs \
235 icr = inb(EWRK3_ICR);\
236 icr &= ~irq_mask;\
237 outb(icr, EWRK3_ICR)
238
239
240
241
242 #define START_EWRK3 \
243 csr = inb(EWRK3_CSR);\
244 csr &= ~(TXD|RXD);\
245 outb(csr, EWRK3_CSR)
246
247 #define STOP_EWRK3 \
248 csr = (TXD|RXD);\
249 outb(csr, EWRK3_CSR)
250
251
252
253
254 #define EWRK3_PKT_STAT_SZ 16
255 #define EWRK3_PKT_BIN_SZ 128
256
257
258 struct ewrk3_private {
259 long shmem_base;
260 long shmem_length;
261 struct enet_statistics stats;
262 struct {
263 unsigned long bins[EWRK3_PKT_STAT_SZ];
264 unsigned long unicast;
265 unsigned long multicast;
266 unsigned long broadcast;
267 unsigned long excessive_collisions;
268 unsigned long tx_underruns;
269 unsigned long excessive_underruns;
270 } pktStats;
271 short mPage;
272 unsigned char lemac;
273 unsigned char hard_strapped;
274 unsigned char lock;
275 unsigned char txc;
276 };
277
278
279
280
281 #define FORCE_2K_MODE \
282 shmem_length = SHMEM_2K;\
283 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
284
285
286
287
288 static int ewrk3_open(struct device *dev);
289 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
290 static void ewrk3_interrupt(int irq, struct pt_regs *regs);
291 static int ewrk3_close(struct device *dev);
292 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
293 static void set_multicast_list(struct device *dev);
294 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
295
296
297
298
299 static int ewrk3_hw_init(struct device *dev, short iobase);
300 static void ewrk3_init(struct device *dev);
301 static int ewrk3_rx(struct device *dev);
302 static int ewrk3_tx(struct device *dev);
303
304 static void EthwrkSignature(char * name, char *eeprom_image);
305 static int DevicePresent(short iobase);
306 static void SetMulticastFilter(struct device *dev, int num_addr, char *multicast_table);
307
308 static int Read_EEPROM(short iobase, unsigned char eaddr);
309 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
310 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
311
312 #ifndef MODULE
313 static struct device *isa_probe(struct device *dev);
314 static struct device *eisa_probe(struct device *dev);
315 static struct device *alloc_device(struct device *dev, int iobase);
316
317 static int num_ewrk3s = 0, num_eth = 0;
318 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
319
320 #else
321 int init_module(void);
322 void cleanup_module(void);
323
324 #endif
325
326 static int autoprobed = 0;
327
328
329
330
331 #define INIT_EWRK3 {\
332 int i;\
333 outb(EEPROM_INIT, EWRK3_IOPR);\
334 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
335 }
336
337
338
339
340 int ewrk3_probe(struct device *dev)
341 {
342 int base_addr = dev->base_addr;
343 int status = -ENODEV;
344 #ifndef MODULE
345 struct device *eth0;
346 #endif
347
348 if (base_addr > 0x0ff) {
349 if (!autoprobed) {
350 if (!check_region(base_addr, EWRK3_TOTAL_SIZE)) {
351 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==1) {
352 if (DevicePresent(base_addr) == 0) {
353
354 request_region(base_addr, EWRK3_IOP_INC, "ewrk3");
355 status = ewrk3_hw_init(dev, base_addr);
356 } else {
357 printk("ewrk3_probe(): No device found\n");
358 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
359 }
360 }
361 } else {
362 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, base_addr);
363 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
364 }
365 } else {
366 status = ewrk3_hw_init(dev, base_addr);
367 }
368 } else if (base_addr > 0) {
369 status = -ENXIO;
370
371 #ifdef MODULE
372 } else {
373 printk("Autoprobing is not supported when loading a module based driver.\n");
374 status = -EIO;
375 #else
376 } else if (!autoprobed) {
377
378 eth0=isa_probe(dev);
379 eth0=eisa_probe(eth0);
380 if (dev->priv) status=0;
381 autoprobed = 1;
382 } else {
383 status = -ENXIO;
384 #endif
385
386 }
387
388 if (status) dev->base_addr = base_addr;
389
390 return status;
391 }
392
393 static int
394 ewrk3_hw_init(struct device *dev, short iobase)
395 {
396 struct ewrk3_private *lp;
397 int i, status=0;
398 unsigned long mem_start, shmem_length;
399 char name[EWRK3_NAME_LENGTH + 1];
400 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
401 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
402
403
404
405
406
407 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
408 INIT_EWRK3;
409
410 nicsr = inb(EWRK3_CSR);
411
412
413
414
415 DISABLE_IRQs;
416
417 if (nicsr == (TXD|RXD)) {
418
419
420
421
422 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
423 union {
424 short val;
425 char c[2];
426 } tmp;
427
428 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
429 eeprom_image[i] = tmp.c[0];
430 eeprom_image[i+1] = tmp.c[1];
431
432 chksum += eeprom_image[i] + eeprom_image[i+1];
433 }
434
435 if (chksum != 0) {
436 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
437 status = -ENXIO;
438 } else {
439
440
441
442 EthwrkSignature(name, eeprom_image);
443
444 if (*name != '\0') {
445 dev->base_addr = iobase;
446
447 if (iobase > 0x400) {
448 outb(eisa_cr, EISA_CR);
449 }
450
451 lemac = eeprom_image[EEPROM_CHIPVER];
452 cmr = inb(EWRK3_CMR);
453
454 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
455 ((lemac == LeMAC2) && !(cmr & HS))) {
456 printk("%s: %s at %#3x", dev->name, name, iobase);
457 hard_strapped = 1;
458 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
459
460 printk("%s: %s at %#3x (EISA slot %d)",
461 dev->name, name, iobase, ((iobase>>12)&0x0f));
462 } else {
463 printk("%s: %s at %#3x", dev->name, name, iobase);
464 }
465
466 if (!status) {
467 printk(", h/w address ");
468 if (lemac == LeMAC2) {
469 for (i = 0;i < ETH_ALEN - 1;i++) {
470 printk("%2.2x:", dev->dev_addr[i] =
471 eeprom_image[EEPROM_PADDR0 + i]);
472 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
473 }
474 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
475 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
476 } else {
477 DevicePresent(iobase);
478 for (i = 0; i < ETH_ALEN - 1; i++) {
479 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
480 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
481 }
482 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
483 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
484 }
485
486 if (aprom_crc(dev, eeprom_image, lemac)) {
487 printk(" which has an EEPROM CRC error.\n");
488 status = -ENXIO;
489 } else {
490 if (lemac == LeMAC2) {
491 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
492 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
493 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
494 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
495 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
496 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
497 }
498 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
499 outb(cmr, EWRK3_CMR);
500
501 cr = inb(EWRK3_CR);
502 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
503 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
504 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
505 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
506 outb(cr, EWRK3_CR);
507
508
509
510
511
512 mem_start = inb(EWRK3_MBR);
513 shmem_length = 0;
514 if (mem_start != 0) {
515 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
516 mem_start *= SHMEM_64K;
517 shmem_length = SHMEM_64K;
518 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
519 mem_start *= SHMEM_32K;
520 shmem_length = SHMEM_32K;
521 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
522 mem_start = mem_start * SHMEM_2K + 0x80000;
523 shmem_length = SHMEM_2K;
524 } else {
525 status = -ENXIO;
526 }
527 }
528
529
530
531
532
533
534
535 if (!status) {
536 if (hard_strapped) {
537 printk(" is hard strapped.\n");
538 } else if (mem_start) {
539 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
540 printk(" at 0x%.5lx", mem_start);
541 } else {
542 printk(" is in I/O only mode");
543 }
544
545
546 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
547 GFP_KERNEL);
548 if (dev->priv == NULL)
549 return -ENOMEM;
550 lp = (struct ewrk3_private *)dev->priv;
551 memset(dev->priv, 0, sizeof(struct ewrk3_private));
552 lp->shmem_base = mem_start;
553 lp->shmem_length = shmem_length;
554 lp->lemac = lemac;
555 lp->hard_strapped = hard_strapped;
556
557 lp->mPage = 64;
558 if (cmr & DRAM) lp->mPage <<= 1 ;
559
560 if (!hard_strapped) {
561
562
563
564 icr |= IE;
565 outb(icr, EWRK3_ICR);
566
567
568 dev->dma = 0;
569
570
571
572 if (dev->irq < 2) {
573 #ifndef MODULE
574 unsigned char irqnum;
575
576 autoirq_setup(0);
577
578
579
580
581 icr |=TNEM;
582 outb(1,EWRK3_TDQ);
583 outb(icr, EWRK3_ICR);
584
585 irqnum = irq[((icr & IRQ_SEL) >> 4)];
586
587 dev->irq = autoirq_report(1);
588 if ((dev->irq) && (irqnum == dev->irq)) {
589 printk(" and uses IRQ%d.\n", dev->irq);
590 } else {
591 if (!dev->irq) {
592 printk(" and failed to detect IRQ line.\n");
593 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
594 printk(" and an illegal IRQ line detected.\n");
595 } else {
596 printk(", but incorrect IRQ line detected.\n");
597 }
598 status = -ENXIO;
599 }
600
601 DISABLE_IRQs;
602
603 #endif
604 } else {
605 printk(" and requires IRQ%d.\n", dev->irq);
606 }
607 }
608 } else {
609 status = -ENXIO;
610 }
611 }
612 }
613 } else {
614 status = -ENXIO;
615 }
616 }
617
618 if (!status) {
619 if (ewrk3_debug > 0) {
620 printk(version);
621 }
622
623
624 dev->open = &ewrk3_open;
625 dev->hard_start_xmit = &ewrk3_queue_pkt;
626 dev->stop = &ewrk3_close;
627 dev->get_stats = &ewrk3_get_stats;
628 #ifdef HAVE_MULTICAST
629 dev->set_multicast_list = &set_multicast_list;
630 #endif
631 dev->do_ioctl = &ewrk3_ioctl;
632
633 dev->mem_start = 0;
634
635
636 ether_setup(dev);
637 }
638 } else {
639 status = -ENXIO;
640 }
641
642 return status;
643 }
644
645
646 static int
647 ewrk3_open(struct device *dev)
648 {
649 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
650 int i, iobase = dev->base_addr;
651 int status = 0;
652 unsigned char icr, csr;
653
654
655
656
657 STOP_EWRK3;
658
659 if (!lp->hard_strapped) {
660 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
661 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
662 status = -EAGAIN;
663 } else {
664
665 irq2dev_map[dev->irq] = dev;
666
667
668
669
670 ewrk3_init(dev);
671
672 if (ewrk3_debug > 1){
673 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
674 printk("\tphysical address: ");
675 for (i=0;i<6;i++){
676 printk("%2.2x:",(short)dev->dev_addr[i]);
677 }
678 printk("\n");
679 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
680 if (lp->shmem_length == 0) {
681 printk("\tno shared memory, I/O only mode\n");
682 } else {
683 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
684 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
685 }
686 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
687 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
688 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
689 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
690 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
691 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
692 }
693
694 dev->tbusy = 0;
695 dev->start = 1;
696 dev->interrupt = UNMASK_INTERRUPTS;
697
698
699
700
701 icr = inb(EWRK3_ICR);
702 ENABLE_IRQs;
703
704 }
705 } else {
706 dev->start = 0;
707 dev->tbusy = 1;
708 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
709 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
710 }
711
712 MOD_INC_USE_COUNT;
713
714 return status;
715 }
716
717
718
719
720 static void
721 ewrk3_init(struct device *dev)
722 {
723 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
724 char csr, page;
725 short iobase = dev->base_addr;
726 int flags=dev->flags;
727
728
729
730
731
732 dev->flags|=IFF_ALLMULTI;
733 set_multicast_list(dev);
734 dev->flags=flags;
735
736
737
738
739 while (inb(EWRK3_TQ));
740 while (inb(EWRK3_TDQ));
741 while (inb(EWRK3_RQ));
742 while (inb(EWRK3_FMQ));
743
744
745
746
747 for (page=1;page<lp->mPage;page++) {
748 outb(page, EWRK3_FMQ);
749 }
750
751 lp->lock = 0;
752
753 START_EWRK3;
754 }
755
756
757
758
759 static int
760 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
761 {
762 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
763 int iobase = dev->base_addr;
764 int status = 0;
765 unsigned char icr, csr;
766
767
768 if (dev->tbusy || lp->lock) {
769 int tickssofar = jiffies - dev->trans_start;
770 if (tickssofar < 10) {
771 status = -1;
772 } else if (!lp->hard_strapped) {
773 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
774 dev->name, inb(EWRK3_CSR));
775
776
777
778
779 DISABLE_IRQs;
780
781
782
783
784 STOP_EWRK3;
785
786 ewrk3_init(dev);
787
788
789
790
791 ENABLE_IRQs;
792
793 dev->tbusy=0;
794 dev->trans_start = jiffies;
795 }
796 } else if (skb == NULL) {
797 dev_tint(dev);
798 } else if (skb->len > 0) {
799
800
801
802
803
804 if (set_bit(0, (void*)&dev->tbusy) != 0)
805 printk("%s: Transmitter access conflict.\n", dev->name);
806
807 DISABLE_IRQs;
808
809
810
811
812 if (inb(EWRK3_FMQC) > 0) {
813 unsigned char *buf;
814 unsigned char page;
815
816 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
817 buf = NULL;
818
819
820
821
822 while (set_bit(0, (void *)&lp->lock) != 0);
823 if (lp->shmem_length == IO_ONLY) {
824 outb(page, EWRK3_IOPR);
825 } else if (lp->shmem_length == SHMEM_2K) {
826 buf = (char *) lp->shmem_base;
827 outb(page, EWRK3_MPR);
828 } else if (lp->shmem_length == SHMEM_32K) {
829 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
830 outb((page >> 4), EWRK3_MPR);
831 } else if (lp->shmem_length == SHMEM_64K) {
832 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
833 outb((page >> 5), EWRK3_MPR);
834 } else {
835 status = -1;
836 printk("%s: Oops - your private data area is hosed!\n",dev->name);
837 }
838
839 if (!status) {
840
841
842
843
844
845
846 if (lp->shmem_length == IO_ONLY) {
847 int i;
848 unsigned char *p = skb->data;
849
850 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
851 outb((char)(skb->len & 0xff), EWRK3_DATA);
852 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
853 outb((char)0x04, EWRK3_DATA);
854 for (i=0; i<skb->len; i++) {
855 outb(*p++, EWRK3_DATA);
856 }
857 outb(page, EWRK3_TQ);
858 } else {
859 *buf++ = (char)(QMODE | PAD | IFC);
860 *buf++ = (char)(skb->len & 0xff);
861 if (lp->txc) {
862 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
863 *buf++ = 0x04;
864 *(buf + skb->len) = 0x00;
865 memcpy(buf, skb->data, PRELOAD);
866 outb(page, EWRK3_TQ);
867 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
868 *(buf + skb->len) = 0xff;
869 } else {
870 *buf++ = (char)((skb->len >> 8) & 0xff);
871 *buf++ = 0x04;
872 memcpy(buf, skb->data, skb->len);
873 outb(page, EWRK3_TQ);
874 }
875 }
876
877 dev->trans_start = jiffies;
878
879 dev_kfree_skb (skb, FREE_WRITE);
880
881 } else {
882 outb(page, EWRK3_FMQ);
883 }
884 lp->lock = 0;
885 } else {
886 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
887 (unsigned char) page);
888 }
889 } else {
890 printk("ewrk3_queue_pkt(): No free resources...\n");
891 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
892 }
893
894
895 if (inb(EWRK3_FMQC) > 0) {
896 dev->tbusy = 0;
897 }
898
899 ENABLE_IRQs;
900 }
901
902 return status;
903 }
904
905
906
907
908 static void
909 ewrk3_interrupt(int irq, struct pt_regs * regs)
910 {
911 struct device *dev = (struct device *)(irq2dev_map[irq]);
912 struct ewrk3_private *lp;
913 int iobase;
914 unsigned char icr, cr, csr;
915
916 if (dev == NULL) {
917 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
918 } else {
919 lp = (struct ewrk3_private *)dev->priv;
920 iobase = dev->base_addr;
921
922 if (dev->interrupt)
923 printk("%s: Re-entering the interrupt handler.\n", dev->name);
924
925 dev->interrupt = MASK_INTERRUPTS;
926
927
928 csr = inb(EWRK3_CSR);
929
930
931
932
933 DISABLE_IRQs;
934
935 cr = inb(EWRK3_CR);
936 cr |= LED;
937 outb(cr, EWRK3_CR);
938
939 if (csr & RNE)
940 ewrk3_rx(dev);
941
942 if (csr & TNE)
943 ewrk3_tx(dev);
944
945
946
947
948
949
950
951 if (inb(EWRK3_FMQC)) {
952 irq_mask |= TXDM|RXDM;
953 csr &= ~(TXD|RXD);
954 outb(csr, EWRK3_CSR);
955 dev->tbusy = 0;
956 mark_bh(NET_BH);
957 } else {
958 irq_mask &= ~(TXDM|RXDM);
959 }
960
961
962 cr &= ~LED;
963 outb(cr, EWRK3_CR);
964
965 dev->interrupt = UNMASK_INTERRUPTS;
966
967 ENABLE_IRQs;
968 }
969
970 return;
971 }
972
973 static int
974 ewrk3_rx(struct device *dev)
975 {
976 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
977 int i, iobase = dev->base_addr;
978 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
979 int status = 0;
980
981 while (inb(EWRK3_RQC) && !status) {
982 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
983 buf = NULL;
984
985
986
987
988
989 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
990 if (lp->shmem_length == IO_ONLY) {
991 tmpPage = inb(EWRK3_IOPR);
992 } else {
993 tmpPage = inb(EWRK3_MPR);
994 }
995 }
996
997
998
999
1000 if (lp->shmem_length == IO_ONLY) {
1001 outb(page, EWRK3_IOPR);
1002 } else if (lp->shmem_length == SHMEM_2K) {
1003 buf = (char *) lp->shmem_base;
1004 outb(page, EWRK3_MPR);
1005 } else if (lp->shmem_length == SHMEM_32K) {
1006 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
1007 outb((page >> 4), EWRK3_MPR);
1008 } else if (lp->shmem_length == SHMEM_64K) {
1009 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
1010 outb((page >> 5), EWRK3_MPR);
1011 } else {
1012 status = -1;
1013 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1014 }
1015
1016 if (!status) {
1017 char rx_status;
1018 int pkt_len;
1019
1020 if (lp->shmem_length == IO_ONLY) {
1021 rx_status = inb(EWRK3_DATA);
1022 pkt_len = inb(EWRK3_DATA);
1023 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1024 } else {
1025 rx_status = (char)(*buf++);
1026 pkt_len = (short)(*buf+((*(buf+1))<<8));
1027 buf+=3;
1028 }
1029
1030 if (!(rx_status & ROK)) {
1031 lp->stats.rx_errors++;
1032 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1033 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1034 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1035 } else {
1036 struct sk_buff *skb;
1037
1038 if ((skb = dev_alloc_skb(pkt_len+2)) != NULL) {
1039 unsigned char *p;
1040 skb->dev = dev;
1041 skb_reserve(skb,2);
1042 p = skb_put(skb,pkt_len);
1043
1044 if (lp->shmem_length == IO_ONLY) {
1045 *p = inb(EWRK3_DATA);
1046 for (i=0; i<pkt_len; i++) {
1047 *p++ = inb(EWRK3_DATA);
1048 }
1049 } else {
1050 memcpy(p, buf, pkt_len);
1051 }
1052
1053
1054
1055
1056
1057
1058 skb->protocol=eth_type_trans(skb,dev);
1059 netif_rx(skb);
1060
1061
1062
1063
1064 lp->stats.rx_packets++;
1065 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1066 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1067 lp->pktStats.bins[i]++;
1068 i = EWRK3_PKT_STAT_SZ;
1069 }
1070 }
1071 buf = skb->data;
1072 if (buf[0] & 0x01) {
1073 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1074 lp->pktStats.broadcast++;
1075 } else {
1076 lp->pktStats.multicast++;
1077 }
1078 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1079 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1080 lp->pktStats.unicast++;
1081 }
1082
1083 lp->pktStats.bins[0]++;
1084 if (lp->pktStats.bins[0] == 0) {
1085 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1086 }
1087 } else {
1088 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1089 lp->stats.rx_dropped++;
1090 break;
1091 }
1092 }
1093 }
1094
1095
1096
1097 outb(page, EWRK3_FMQ);
1098
1099 if (tmpLock) {
1100 if (lp->shmem_length == IO_ONLY) {
1101 outb(tmpPage, EWRK3_IOPR);
1102 } else {
1103 outb(tmpPage, EWRK3_MPR);
1104 }
1105 }
1106 lp->lock = 0;
1107 } else {
1108 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1109 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1110 }
1111 }
1112 return status;
1113 }
1114
1115
1116
1117
1118 static int
1119 ewrk3_tx(struct device *dev)
1120 {
1121 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1122 int iobase = dev->base_addr;
1123 unsigned char tx_status;
1124
1125 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1126 if (tx_status & VSTS) {
1127 if (tx_status & MAC_TXE) {
1128 lp->stats.tx_errors++;
1129 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1130 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1131 if (tx_status & MAC_CTU) {
1132 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1133 lp->pktStats.tx_underruns++;
1134 } else {
1135 lp->pktStats.excessive_underruns++;
1136 }
1137 } else if (tx_status & MAC_COLL) {
1138 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1139 lp->stats.collisions++;
1140 } else {
1141 lp->pktStats.excessive_collisions++;
1142 }
1143 }
1144 } else {
1145 lp->stats.tx_packets++;
1146 }
1147 }
1148 }
1149
1150 return 0;
1151 }
1152
1153 static int
1154 ewrk3_close(struct device *dev)
1155 {
1156 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1157 int iobase = dev->base_addr;
1158 unsigned char icr, csr;
1159
1160 dev->start = 0;
1161 dev->tbusy = 1;
1162
1163 if (ewrk3_debug > 1) {
1164 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1165 dev->name, inb(EWRK3_CSR));
1166 }
1167
1168
1169
1170
1171 DISABLE_IRQs;
1172
1173 STOP_EWRK3;
1174
1175
1176
1177
1178
1179
1180
1181 while (inb(EWRK3_TQ));
1182 while (inb(EWRK3_TDQ));
1183 while (inb(EWRK3_RQ));
1184
1185 if (!lp->hard_strapped) {
1186 free_irq(dev->irq);
1187
1188 irq2dev_map[dev->irq] = 0;
1189 }
1190
1191 MOD_DEC_USE_COUNT;
1192
1193 return 0;
1194 }
1195
1196 static struct enet_statistics *
1197 ewrk3_get_stats(struct device *dev)
1198 {
1199 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1200
1201
1202
1203 return &lp->stats;
1204 }
1205
1206
1207
1208
1209
1210
1211
1212
1213 static void
1214 set_multicast_list(struct device *dev)
1215 {
1216 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1217 int iobase = dev->base_addr;
1218 char *multicast_table;
1219 unsigned char csr;
1220
1221 csr = inb(EWRK3_CSR);
1222
1223 if (lp->shmem_length == IO_ONLY)
1224 {
1225 multicast_table = (char *) PAGE0_HTE;
1226 } else {
1227 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1228 }
1229
1230 if (dev->flags&(IFF_ALLMULTI|IFF_PROMISC))
1231 {
1232 csr |= PME;
1233 csr &= ~MCE;
1234 outb(csr, EWRK3_CSR);
1235 dev->flags|=IFF_PROMISC;
1236 } else {
1237 SetMulticastFilter(dev, dev->mc_count, multicast_table);
1238 csr &= ~PME;
1239 csr |= MCE;
1240 outb(csr, EWRK3_CSR);
1241 }
1242 }
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252 static void SetMulticastFilter(struct device *dev, int num_addrs, char *multicast_table)
1253 {
1254 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1255 char *addrs;
1256 struct dev_mc_list *dmi=dev->mc_list;
1257 int i, iobase = dev->base_addr;
1258 char j, bit, byte;
1259 short *p = (short *) multicast_table;
1260 u_short hashcode;
1261 u_long crc, poly = CRC_POLYNOMIAL_LE;
1262
1263 while (set_bit(0, (void *)&lp->lock) != 0);
1264
1265 if (lp->shmem_length == IO_ONLY)
1266 {
1267 outb(0, EWRK3_IOPR);
1268 outw((short)((long)multicast_table), EWRK3_PIR1);
1269 }
1270 else
1271 {
1272 outb(0, EWRK3_MPR);
1273 }
1274
1275 if (num_addrs >= HASH_TABLE_LEN)
1276 {
1277 for (i=0; i<(HASH_TABLE_LEN >> 3); i++)
1278 {
1279 if (lp->shmem_length == IO_ONLY)
1280 {
1281 outb(0xff, EWRK3_DATA);
1282 }
1283 else
1284 {
1285 *p++ = 0xffff;
1286 i++;
1287 }
1288 }
1289 }
1290 else
1291 {
1292
1293 if (lp->shmem_length == IO_ONLY)
1294 {
1295 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++)
1296 {
1297 outb(0x00, EWRK3_DATA);
1298 }
1299 outb(0x80, EWRK3_DATA); i++;
1300 for (; i<(HASH_TABLE_LEN >> 3); i++)
1301 {
1302 outb(0x00, EWRK3_DATA);
1303 }
1304 }
1305 else
1306 {
1307 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1308 *(multicast_table + (HASH_TABLE_LEN >> 4) - 1) = 0x80;
1309 }
1310
1311
1312
1313 for (i=0;i<dev->mc_count;i++)
1314 {
1315
1316 addrs=dmi->dmi_addr;
1317 dmi=dmi->next;
1318
1319 if ((*addrs & 0x01) == 1)
1320 {
1321 crc = 0xffffffff;
1322 for (byte=0;byte<ETH_ALEN;byte++)
1323 {
1324
1325 for (bit = *addrs++,j=0;j<8;j++, bit>>=1)
1326 {
1327 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1328 }
1329 }
1330 hashcode = crc & ((1 << 9) - 1);
1331
1332 byte = hashcode >> 3;
1333 bit = 1 << (hashcode & 0x07);
1334
1335 if (lp->shmem_length == IO_ONLY)
1336 {
1337 unsigned char tmp;
1338
1339 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1340 tmp = inb(EWRK3_DATA);
1341 tmp |= bit;
1342 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1343 outb(tmp, EWRK3_DATA);
1344 }
1345 else
1346 {
1347 multicast_table[byte] |= bit;
1348 }
1349 }
1350 }
1351 }
1352
1353 lp->lock = 0;
1354
1355 return;
1356 }
1357
1358 #ifndef MODULE
1359
1360
1361
1362 static struct device *isa_probe(struct device *dev)
1363 {
1364 int i, iobase, status;
1365 unsigned long int tmp = mem_chkd;
1366
1367 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1368 i < 24;
1369 iobase += EWRK3_IOP_INC, i++) {
1370 if (tmp & 0x01) {
1371
1372 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1373 if (DevicePresent(iobase) == 0) {
1374
1375
1376
1377
1378 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1379 if (num_ewrk3s > 0) {
1380 dev = alloc_device(dev, iobase);
1381 } else {
1382 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1383 num_ewrk3s++;
1384 }
1385 }
1386 num_eth++;
1387 } else {
1388 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1389 }
1390 } else {
1391 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, iobase);
1392 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1393 }
1394 }
1395 tmp >>= 1;
1396 }
1397
1398 return dev;
1399 }
1400
1401
1402
1403
1404
1405 static struct device *eisa_probe(struct device *dev)
1406 {
1407 int i, iobase = EWRK3_EISA_IO_PORTS;
1408 int status;
1409
1410 iobase+=EISA_SLOT_INC;
1411 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1412
1413
1414 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1415 if (DevicePresent(iobase) == 0) {
1416
1417
1418
1419
1420 mem_chkd |= (0x01 << (i + 24));
1421 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1422 if (num_ewrk3s > 0) {
1423 dev = alloc_device(dev, iobase);
1424 } else {
1425 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1426 num_ewrk3s++;
1427 }
1428 }
1429 num_eth++;
1430 }
1431 }
1432 }
1433 return dev;
1434 }
1435
1436
1437
1438
1439
1440 static struct device *alloc_device(struct device *dev, int iobase)
1441 {
1442
1443
1444
1445 while (dev->next != NULL) {
1446 if (dev->next->base_addr == 0xffe0) break;
1447 dev = dev->next;
1448 num_eth++;
1449 }
1450
1451
1452
1453
1454
1455 if (dev->next == NULL) {
1456 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1457 GFP_KERNEL);
1458 if (dev->next == NULL) {
1459 printk("eth%d: Device not initialised, insufficient memory\n",
1460 num_eth);
1461 }
1462 }
1463
1464
1465
1466
1467
1468
1469 if ((dev->next != NULL) &&
1470 (num_eth > 0) && (num_eth < 9999)) {
1471 dev = dev->next;
1472 dev->name = (char *)(dev + sizeof(struct device));
1473 sprintf(dev->name,"eth%d", num_eth);
1474 dev->base_addr = iobase;
1475 dev->next = NULL;
1476 dev->init = &ewrk3_probe;
1477 num_ewrk3s++;
1478 }
1479
1480 return dev;
1481 }
1482 #endif
1483
1484
1485
1486
1487 static int Read_EEPROM(short iobase, unsigned char eaddr)
1488 {
1489 int i;
1490
1491 outb((eaddr & 0x3f), EWRK3_PIR1);
1492 outb(EEPROM_RD, EWRK3_IOPR);
1493 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1494
1495 return inw(EWRK3_EPROM1);
1496 }
1497
1498
1499
1500
1501 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1502 {
1503 int i;
1504
1505 outb(EEPROM_WR_EN, EWRK3_IOPR);
1506 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1507 outw(data, EWRK3_EPROM1);
1508 outb((eaddr & 0x3f), EWRK3_PIR1);
1509 outb(EEPROM_WR, EWRK3_IOPR);
1510 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1511 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1512 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1513
1514 return 0;
1515 }
1516
1517
1518
1519
1520 static void EthwrkSignature(char *name, char *eeprom_image)
1521 {
1522 unsigned long i,j,k;
1523 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1524
1525 strcpy(name, "");
1526 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1527 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1528 if (signatures[i][k] == eeprom_image[j]) {
1529 k++;
1530 } else {
1531 k=0;
1532 }
1533 }
1534 if (k == strlen(signatures[i])) {
1535 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1536 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1537 name[EWRK3_NAME_LENGTH] = '\0';
1538 }
1539 }
1540 }
1541
1542 return;
1543 }
1544
1545
1546
1547
1548
1549
1550 static int DevicePresent(short iobase)
1551 {
1552 static short fp=1,sigLength=0;
1553 static char devSig[] = PROBE_SEQUENCE;
1554 char data;
1555 int i, j, status = 0;
1556 static char asc2hex(char value);
1557
1558
1559
1560
1561 if (fp) {
1562 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1563 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1564 devSig[i]<<=4;
1565 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1566 devSig[j]=devSig[i]+devSig[i+1];
1567 } else {
1568 status= -1;
1569 }
1570 } else {
1571 status= -1;
1572 }
1573 }
1574 sigLength=j;
1575 fp = 0;
1576 }
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586 if (!status) {
1587 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1588 data = inb(EWRK3_APROM);
1589 if (devSig[j] == data) {
1590 j++;
1591 } else {
1592 j=0;
1593 }
1594 }
1595
1596 if (j!=sigLength) {
1597 status = -ENODEV;
1598 }
1599 }
1600
1601 return status;
1602 }
1603
1604 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1605 {
1606 long k;
1607 unsigned short j,chksum;
1608 unsigned char crc, lfsr, sd, status = 0;
1609 int iobase = dev->base_addr;
1610
1611 if (chipType == LeMAC2) {
1612 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1613 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1614 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1615 crc = (crc >> 1) + lfsr;
1616 }
1617 }
1618 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1619 } else {
1620 for (k=0,j=0;j<3;j++) {
1621 k <<= 1 ;
1622 if (k > 0xffff) k-=0xffff;
1623 k += inw(EWRK3_PAR0 + (j<<1));
1624 if (k > 0xffff) k-=0xffff;
1625 }
1626 if (k == 0xffff) k=0;
1627 chksum = inb(EWRK3_APROM);
1628 chksum |= (inb(EWRK3_APROM)<<8);
1629 if (k != chksum) status = -1;
1630 }
1631
1632 return status;
1633 }
1634
1635
1636
1637
1638
1639 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1640 {
1641 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1642 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1643 int i, j, iobase = dev->base_addr, status = 0;
1644 unsigned char csr;
1645 union {
1646 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1647 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1648 } tmp;
1649 int err;
1650
1651 switch(ioc->cmd) {
1652 case EWRK3_GET_HWADDR:
1653 for (i=0; i<ETH_ALEN; i++) {
1654 tmp.addr[i] = dev->dev_addr[i];
1655 }
1656 ioc->len = ETH_ALEN;
1657
1658 err = verify_area(VERIFY_WRITE, (void *)ioc->data, ETH_ALEN);
1659 if (err) return err;
1660 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1661
1662 break;
1663 case EWRK3_SET_HWADDR:
1664 if (suser()) {
1665 csr = inb(EWRK3_CSR);
1666 csr |= (TXD|RXD);
1667 outb(csr, EWRK3_CSR);
1668
1669 err = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
1670 if (err) return err;
1671 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1672 for (i=0; i<ETH_ALEN; i++) {
1673 dev->dev_addr[i] = tmp.addr[i];
1674 outb(tmp.addr[i], EWRK3_PAR0 + i);
1675 }
1676
1677 csr &= ~(TXD|RXD);
1678 outb(csr, EWRK3_CSR);
1679 } else {
1680 status = -EPERM;
1681 }
1682
1683 break;
1684 case EWRK3_SET_PROM:
1685 if (suser()) {
1686 csr = inb(EWRK3_CSR);
1687 csr |= PME;
1688 csr &= ~MCE;
1689 outb(csr, EWRK3_CSR);
1690 } else {
1691 status = -EPERM;
1692 }
1693
1694 break;
1695 case EWRK3_CLR_PROM:
1696 if (suser()) {
1697 csr = inb(EWRK3_CSR);
1698 csr &= ~PME;
1699 outb(csr, EWRK3_CSR);
1700 } else {
1701 status = -EPERM;
1702 }
1703
1704 break;
1705 case EWRK3_SAY_BOO:
1706 if(suser())
1707 printk("%s: Boo!\n", dev->name);
1708
1709 break;
1710 case EWRK3_GET_MCA:
1711 err = verify_area(VERIFY_WRITE, (void *)ioc->data, HASH_TABLE_LEN >> 3);
1712 if (err) return err;
1713
1714 while (set_bit(0, (void *)&lp->lock) != 0);
1715 if (lp->shmem_length == IO_ONLY) {
1716 outb(0, EWRK3_IOPR);
1717 outw(PAGE0_HTE, EWRK3_PIR1);
1718 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1719 tmp.addr[i] = inb(EWRK3_DATA);
1720 }
1721 } else {
1722 outb(0, EWRK3_MPR);
1723 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1724 }
1725 ioc->len = (HASH_TABLE_LEN >> 3);
1726 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1727 lp->lock = 0;
1728
1729 break;
1730
1731 #if 0
1732 case EWRK3_SET_MCA:
1733 if (suser()) {
1734 err = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN * ioc->len);
1735 if (err) return err;
1736
1737 if (ioc->len != HASH_TABLE_LEN) {
1738 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1739 }
1740 set_multicast_list(dev, ioc->len, tmp.addr);
1741 } else {
1742 status = -EPERM;
1743 }
1744
1745 break;
1746 case EWRK3_CLR_MCA:
1747 if (suser()) {
1748 set_multicast_list(dev, 0, NULL);
1749 } else {
1750 status = -EPERM;
1751 }
1752
1753 break;
1754 case EWRK3_MCA_EN:
1755 if (suser()) {
1756 csr = inb(EWRK3_CSR);
1757 csr |= MCE;
1758 csr &= ~PME;
1759 outb(csr, EWRK3_CSR);
1760 } else {
1761 status = -EPERM;
1762 }
1763
1764 break;
1765 #endif
1766 case EWRK3_GET_STATS:
1767 err = verify_area(VERIFY_WRITE, (void *)ioc->data, sizeof(lp->pktStats));
1768 if (err) return err;
1769
1770 cli();
1771 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1772 ioc->len = EWRK3_PKT_STAT_SZ;
1773 sti();
1774
1775 break;
1776 case EWRK3_CLR_STATS:
1777 if (suser()) {
1778 cli();
1779 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1780 sti();
1781 } else {
1782 status = -EPERM;
1783 }
1784
1785 break;
1786 case EWRK3_GET_CSR:
1787 err = verify_area(VERIFY_WRITE, (void *)ioc->data, 1);
1788 if (err) return err;
1789
1790 tmp.addr[0] = inb(EWRK3_CSR);
1791 memcpy_tofs(ioc->data, tmp.addr, 1);
1792
1793 break;
1794 case EWRK3_SET_CSR:
1795 err = verify_area(VERIFY_READ, (void *)ioc->data, 1);
1796 if (err) return err;
1797
1798 if (suser()) {
1799 memcpy_fromfs(tmp.addr, ioc->data, 1);
1800 outb(tmp.addr[0], EWRK3_CSR);
1801 } else {
1802 status = -EPERM;
1803 }
1804
1805 break;
1806 case EWRK3_GET_EEPROM:
1807 if (suser()) {
1808 err = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
1809 if (err) return err;
1810
1811 for (i=0; i<(EEPROM_MAX>>1); i++) {
1812 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1813 }
1814 i = EEPROM_MAX;
1815 tmp.addr[i++] = inb(EWRK3_CMR);
1816 for (j=0;j<ETH_ALEN;j++) {
1817 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1818 }
1819 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1820 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1821 } else {
1822 status = -EPERM;
1823 }
1824
1825 break;
1826 case EWRK3_SET_EEPROM:
1827 if (suser()) {
1828 err = verify_area(VERIFY_READ, (void *)ioc->data, EEPROM_MAX);
1829 if (err) return err;
1830
1831 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1832 for (i=0; i<(EEPROM_MAX>>1); i++) {
1833 Write_EEPROM(tmp.val[i], iobase, i);
1834 }
1835 } else {
1836 status = -EPERM;
1837 }
1838
1839 break;
1840 case EWRK3_GET_CMR:
1841 err = verify_area(VERIFY_WRITE, (void *)ioc->data, 1);
1842 if (err) return err;
1843
1844 tmp.addr[0] = inb(EWRK3_CMR);
1845 memcpy_tofs(ioc->data, tmp.addr, 1);
1846
1847 break;
1848 case EWRK3_SET_TX_CUT_THRU:
1849 if (suser()) {
1850 lp->txc = 1;
1851 } else {
1852 status = -EPERM;
1853 }
1854
1855 break;
1856 case EWRK3_CLR_TX_CUT_THRU:
1857 if (suser()) {
1858 lp->txc = 0;
1859 } else {
1860 status = -EPERM;
1861 }
1862
1863 break;
1864 default:
1865 status = -EOPNOTSUPP;
1866 }
1867
1868 return status;
1869 }
1870
1871 static char asc2hex(char value)
1872 {
1873 value -= 0x30;
1874 if (value >= 0) {
1875 if (value > 9) {
1876 value &= 0x1f;
1877 value -= 0x07;
1878 if ((value < 0x0a) || (value > 0x0f)) {
1879 value = -1;
1880 }
1881 }
1882 } else {
1883 value = -1;
1884 }
1885 return value;
1886 }
1887
1888 #ifdef MODULE
1889 static char devicename[9] = { 0, };
1890 static struct device thisEthwrk = {
1891 devicename,
1892 0, 0, 0, 0,
1893 0x300, 5,
1894 0, 0, 0, NULL, ewrk3_probe };
1895
1896 static int io=0x300;
1897 static int irq=5;
1898
1899 int
1900 init_module(void)
1901 {
1902 thisEthwrk.base_addr=io;
1903 thisEthwrk.irq=irq;
1904 if (register_netdev(&thisEthwrk) != 0)
1905 return -EIO;
1906 return 0;
1907 }
1908
1909 void
1910 cleanup_module(void)
1911 {
1912 release_region(thisEthwrk.base_addr, EWRK3_TOTAL_SIZE);
1913 unregister_netdev(&thisEthwrk);
1914 kfree(thisEthwrk.priv);
1915 thisEthwrk.priv = NULL;
1916 }
1917 #endif
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929