taglinefilesource code
cardbase256drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
cardbase272drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
cardbase275drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1,
cardbase318drivers/net/pi2.cport = lp->cardbase + TMR1;
cardbase322drivers/net/pi2.cport = lp->cardbase + TMR2;
cardbase323drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
cardbase327drivers/net/pi2.coutb_p(sc | LSB_MSB | MODE0, lp->cardbase + TMRCMD);
cardbase334drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R15, CTSIE);
cardbase335drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R0, RES_EXT_INT);
cardbase367drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase368drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase369drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
cardbase373drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
cardbase384drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
cardbase407drivers/net/pi2.cst = rdscc(lp->cardbase, lp->base + CTL, R0);  /* Fetch status */
cardbase410drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
cardbase438drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
cardbase455drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
cardbase458drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, TxUIE);
cardbase461drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
cardbase464drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
cardbase474drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase475drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase476drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
cardbase480drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
cardbase491drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
cardbase519drivers/net/pi2.crse = rdscc(lp->cardbase, cmd, R1);  /* Get special condition bits from R1 */
cardbase576drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R0, ERR_RES);  /* error reset */
cardbase594drivers/net/pi2.crse = rdscc(lp->cardbase, cmd, R1);  /* get status byte from R1 */
cardbase596drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0)) & Rx_CH_AV) {
cardbase618drivers/net/pi2.c*lp->rcp++ = rdscc(lp->cardbase, cmd, R8);  /* char to rcv buff */
cardbase622drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase623drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, ERR_RES);  /* reset err latch */
cardbase708drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase709drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase710drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
cardbase714drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
cardbase735drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);
cardbase741drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
cardbase746drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
cardbase755drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
cardbase757drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS);
cardbase759drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Tx_P);  /* reset Tx Int Pend */
cardbase784drivers/net/pi2.cst = rdscc(lp->cardbase, cmd, R0);  /* Fetch status */
cardbase786drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase793drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
cardbase821drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);  /* reset for next frame */
cardbase825drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
cardbase827drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
cardbase830drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);  /* First char out now */
cardbase831drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EOM_L);  /* Reset end of message latch */
cardbase839drivers/net/pi2.cwhile((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
cardbase841drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);
cardbase847drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
cardbase848drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase849drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);  /* Tx/Ext ints */
cardbase859drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase860drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase861drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
cardbase865drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
cardbase886drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);  /* reset for next frame */
cardbase890drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
cardbase892drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
cardbase895drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);  /* First char out now */
cardbase896drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EOM_L);  /* Reset end of message latch */
cardbase904drivers/net/pi2.cwhile((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
cardbase906drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);
cardbase912drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
cardbase913drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase915drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
cardbase928drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase929drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase930drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase1011drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, 0);
cardbase1012drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, Rx8);  /* Rx off */
cardbase1016drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
cardbase1018drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, 0);  /* No interrupts */
cardbase1025drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
cardbase1026drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);  /* upper byte */
cardbase1029drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
cardbase1033drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);  /*  TX off */
cardbase1039drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC);
cardbase1043drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
cardbase1044drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);  /* upper byte */
cardbase1046drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
cardbase1048drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
cardbase1052drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, Rx8);  /* Make sure rx is off */
cardbase1053drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, ERR_RES);  /* reset err latch */
cardbase1054drivers/net/pi2.cdummy = rdscc(lp->cardbase, cmd, R1);  /* get status byte from R1 */
cardbase1055drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase1056drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase1058drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase1061drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, RxENABLE | Rx8);
cardbase1070drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
cardbase1072drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, BRKIE);  /* allow ABORT int */
cardbase1107drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R9, CHRA);  /* Reset channel A */
cardbase1108drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R2, 0xff);  /* Initialize interrupt vector */
cardbase1111drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R9, CHRB);  /* Reset channel B */
cardbase1116drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, 0);
cardbase1119drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, 0);
cardbase1122drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
cardbase1126drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
cardbase1129drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
cardbase1132drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R11, TCDPLL | RCDPLL | TRxCBR | TRxCOI);
cardbase1134drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS);
cardbase1136drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R11, TCTRxCP);
cardbase1140drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R6, 0);
cardbase1143drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R7, FLAG);
cardbase1148drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
cardbase1151drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, Rx8);  /* 8 bits/char */
cardbase1154drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC);  /* BRG off, keep Pclk source */
cardbase1165drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
cardbase1166drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);  /* upper byte */
cardbase1173drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
cardbase1176drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);
cardbase1178drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);  /* SEARCH mode, keep BRG src */
cardbase1179drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);  /* Enable the BRG */
cardbase1182drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
cardbase1184drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, BRKIE);  /* ABORT int */
cardbase1187drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | Rx8);
cardbase1194drivers/net/pi2.cint cardbase;
cardbase1197drivers/net/pi2.ccardbase = dev->base_addr & 0x3f0;
cardbase1201drivers/net/pi2.cwrtscc(cardbase, dev->base_addr + CTL, R9, FHWRES);  /* Hardware reset */
cardbase1203drivers/net/pi2.cwrtscc(cardbase, dev->base_addr + CTL, R9, 0);
cardbase1338drivers/net/pi2.clp->cardbase = dev->base_addr & 0x3f0;
cardbase1375drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R1, EXT_INT_ENAB);
cardbase1377drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
cardbase1388drivers/net/pi2.cwrtscc(lp->cardbase, dev->base_addr + CTL, R9, FHWRES);  /* Hardware reset */
cardbase1390drivers/net/pi2.cwrtscc(lp->cardbase, dev->base_addr + CTL, R9, 0);
cardbase1481drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
cardbase1531drivers/net/pi2.cwhile ((st = rdscc(lp->cardbase, pi0a.base_addr | CHANA | CTL, R3)) != 0) {
cardbase1560drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
cardbase120drivers/net/pi2.hint cardbase;     /* Base address of card */