1 #ifndef _AHA152X_H
2 #define _AHA152X_H
3
4
5
6
7
8 #if defined(__KERNEL__)
9
10 #include "../block/blk.h"
11 #include "scsi.h"
12 #include <asm/io.h>
13
14 int aha152x_detect(Scsi_Host_Template *);
15 int aha152x_command(Scsi_Cmnd *);
16 int aha152x_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
17 int aha152x_abort(Scsi_Cmnd *);
18 int aha152x_reset(Scsi_Cmnd *);
19 int aha152x_biosparam(Disk *, int, int*);
20
21 extern int generic_proc_info(char *, char **, off_t, int, int, int);
22
23
24
25 #define AHA152X_MAXQUEUE 7
26
27 #define AHA152X_REVID "Adaptec 152x SCSI driver; $Revision: 1.9 $"
28
29
30 #define AHA152X { NULL, \
31 NULL, \
32 generic_proc_info, \
33 "aha152x", \
34 PROC_SCSI_AHA152X, \
35 AHA152X_REVID, \
36 aha152x_detect, \
37 NULL, \
38 NULL, \
39 aha152x_command, \
40 aha152x_queue, \
41 aha152x_abort, \
42 aha152x_reset, \
43 0, \
44 aha152x_biosparam, \
45 1, \
46 7, \
47 SG_ALL, \
48 1, \
49 0, \
50 0, \
51 DISABLE_CLUSTERING }
52 #endif
53
54
55
56 #define SCSISEQ (port_base+0x00)
57 #define SXFRCTL0 (port_base+0x01)
58 #define SXFRCTL1 (port_base+0x02)
59 #define SCSISIG (port_base+0x03)
60 #define SCSIRATE (port_base+0x04)
61 #define SELID (port_base+0x05)
62 #define SCSIID SELID
63 #define SCSIDAT (port_base+0x06)
64 #define SCSIBUS (port_base+0x07)
65 #define STCNT0 (port_base+0x08)
66 #define STCNT1 (port_base+0x09)
67 #define STCNT2 (port_base+0x0a)
68 #define SSTAT0 (port_base+0x0b)
69 #define SSTAT1 (port_base+0x0c)
70 #define SSTAT2 (port_base+0x0d)
71 #define SCSITEST (port_base+0x0e)
72 #define SSTAT4 (port_base+0x0f)
73 #define SIMODE0 (port_base+0x10)
74 #define SIMODE1 (port_base+0x11)
75 #define DMACNTRL0 (port_base+0x12)
76 #define DMACNTRL1 (port_base+0x13)
77 #define DMASTAT (port_base+0x14)
78 #define FIFOSTAT (port_base+0x15)
79 #define DATAPORT (port_base+0x16)
80 #define BRSTCNTRL (port_base+0x18)
81 #define PORTA (port_base+0x1a)
82 #define PORTB (port_base+0x1b)
83 #define REV (port_base+0x1c)
84 #define STACK (port_base+0x1d)
85 #define TEST (port_base+0x1e)
86
87
88
89
90
91 #define TEMODEO 0x80
92 #define ENSELO 0x40
93 #define ENSELI 0x20
94 #define ENRESELI 0x10
95 #define ENAUTOATNO 0x08
96 #define ENAUTOATNI 0x04
97 #define ENAUTOATNP 0x02
98 #define SCSIRSTO 0x01
99
100
101 #define SCSIEN 0x80
102 #define DMAEN 0x40
103 #define CH1 0x20
104 #define CLRSTCNT 0x10
105 #define SPIOEN 0x08
106 #define CLRCH1 0x02
107
108
109 #define BITBUCKET 0x80
110 #define SWRAPEN 0x40
111 #define ENSPCHK 0x20
112 #define STIMESEL 0x18
113 #define STIMESEL_ 3
114 #define ENSTIMER 0x04
115 #define BYTEALIGN 0x02
116
117
118 #define CDI 0x80
119 #define IOI 0x40
120 #define MSGI 0x20
121 #define ATNI 0x10
122 #define SELI 0x08
123 #define BSYI 0x04
124 #define REQI 0x02
125 #define ACKI 0x01
126
127
128 #define P_MASK (MSGI|CDI|IOI)
129 #define P_DATAO (0)
130 #define P_DATAI (IOI)
131 #define P_CMD (CDI)
132 #define P_STATUS (CDI|IOI)
133 #define P_MSGO (MSGI|CDI)
134 #define P_MSGI (MSGI|CDI|IOI)
135
136
137 #define CDO 0x80
138 #define IOO 0x40
139 #define MSGO 0x20
140 #define ATNO 0x10
141 #define SELO 0x08
142 #define BSYO 0x04
143 #define REQO 0x02
144 #define ACKO 0x01
145
146
147 #define SXFR 0x70
148 #define SXFR_ 4
149 #define SOFS 0x0f
150
151
152 #define OID 0x70
153 #define OID_ 4
154 #define TID 0x07
155
156
157 #define GETSTCNT() ( (GETPORT(STCNT2)<<16) \
158 + (GETPORT(STCNT1)<< 8) \
159 + GETPORT(STCNT0) )
160
161 #define SETSTCNT(X) { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \
162 SETPORT(STCNT1, ((X) & 0x00FF00) >> 8); \
163 SETPORT(STCNT0, ((X) & 0x0000FF) ); }
164
165
166 #define TARGET 0x80
167 #define SELDO 0x40
168 #define SELDI 0x20
169 #define SELINGO 0x10
170 #define SWRAP 0x08
171 #define SDONE 0x04
172 #define SPIORDY 0x02
173 #define DMADONE 0x01
174
175 #define SETSDONE 0x80
176 #define CLRSELDO 0x40
177 #define CLRSELDI 0x20
178 #define CLRSELINGO 0x10
179 #define CLRSWRAP 0x08
180 #define CLRSDONE 0x04
181 #define CLRSPIORDY 0x02
182 #define CLRDMADONE 0x01
183
184
185 #define SELTO 0x80
186 #define ATNTARG 0x40
187 #define SCSIRSTI 0x20
188 #define PHASEMIS 0x10
189 #define BUSFREE 0x08
190 #define SCSIPERR 0x04
191 #define PHASECHG 0x02
192 #define REQINIT 0x01
193
194 #define CLRSELTIMO 0x80
195 #define CLRATNO 0x40
196 #define CLRSCSIRSTI 0x20
197 #define CLRBUSFREE 0x08
198 #define CLRSCSIPERR 0x04
199 #define CLRPHASECHG 0x02
200 #define CLRREQINIT 0x01
201
202
203 #define SOFFSET 0x20
204 #define SEMPTY 0x10
205 #define SFULL 0x08
206 #define SFCNT 0x07
207
208
209 #define SCSICNT 0xf0
210 #define SCSICNT_ 4
211 #define OFFCNT 0x0f
212
213
214 #define SCTESTU 0x08
215 #define SCTESTD 0x04
216 #define STCTEST 0x01
217
218
219 #define SYNCERR 0x04
220 #define FWERR 0x02
221 #define FRERR 0x01
222
223 #define CLRSYNCERR 0x04
224 #define CLRFWERR 0x02
225 #define CLRFRERR 0x01
226
227
228 #define ENSELDO 0x40
229 #define ENSELDI 0x20
230 #define ENSELINGO 0x10
231 #define ENSWRAP 0x08
232 #define ENSDONE 0x04
233 #define ENSPIORDY 0x02
234 #define ENDMADONE 0x01
235
236
237 #define ENSELTIMO 0x80
238 #define ENATNTARG 0x40
239 #define ENSCSIRST 0x20
240 #define ENPHASEMIS 0x10
241 #define ENBUSFREE 0x08
242 #define ENSCSIPERR 0x04
243 #define ENPHASECHG 0x02
244 #define ENREQINIT 0x01
245
246
247 #define ENDMA 0x80
248 #define _8BIT 0x40
249 #define DMA 0x20
250 #define WRITE_READ 0x08
251 #define INTEN 0x04
252 #define RSTFIFO 0x02
253 #define SWINT 0x01
254
255
256 #define PWRDWN 0x80
257 #define STK 0x07
258
259
260 #define ATDONE 0x80
261 #define WORDRDY 0x40
262 #define INTSTAT 0x20
263 #define DFIFOFULL 0x10
264 #define DFIFOEMP 0x08
265
266
267 #define BON 0xf0
268 #define BOFF 0x0f
269
270
271 #define BOFFTMR 0x40
272 #define BONTMR 0x20
273 #define STCNTH 0x10
274 #define STCNTM 0x08
275 #define STCNTL 0x04
276 #define SCSIBLK 0x02
277 #define DMABLK 0x01
278
279
280
281 typedef union {
282 struct {
283 unsigned reserved:2;
284 unsigned tardisc:1;
285 unsigned syncneg:1;
286 unsigned msgclasses:2;
287
288
289
290
291
292 unsigned boot:1;
293 unsigned dma:1;
294 unsigned id:3;
295 unsigned irq:2;
296 unsigned dmachan:2;
297 unsigned parity:1;
298 } fields;
299 unsigned short port;
300 } aha152x_config ;
301
302 #define cf_parity fields.parity
303 #define cf_dmachan fields.dmachan
304 #define cf_irq fields.irq
305 #define cf_id fields.id
306 #define cf_dma fields.dma
307 #define cf_boot fields.boot
308 #define cf_msgclasses fields.msgclasses
309 #define cf_syncneg fields.syncneg
310 #define cf_tardisc fields.tardisc
311 #define cf_port port
312
313
314
315 #define SETPORT(PORT, VAL) \
316 outb( (VAL), (PORT) )
317
318 #define SETPORTP(PORT, VAL) \
319 outb_p( (VAL), (PORT) )
320
321 #define SETPORTW(PORT, VAL) \
322 outw( (VAL), (PORT) )
323
324 #define GETPORT(PORT) \
325 inb( PORT )
326
327 #define GETPORTW(PORT) \
328 inw( PORT )
329
330 #define SETBITS(PORT, BITS) \
331 outb( (inb(PORT) | (BITS)), (PORT) )
332
333 #define CLRBITS(PORT, BITS) \
334 outb( (inb(PORT) & ~(BITS)), (PORT) )
335
336 #define CLRSETBITS(PORT, CLR, SET) \
337 outb( (inb(PORT) & ~(CLR)) | (SET) , (PORT) )
338
339 #define TESTHI(PORT, BITS) \
340 ((inb(PORT) & (BITS)) == BITS)
341
342 #define TESTLO(PORT, BITS) \
343 ((inb(PORT) & (BITS)) == 0)
344
345 #ifdef DEBUG_AHA152X
346 enum {
347 debug_skipports =0x0001,
348 debug_queue =0x0002,
349 debug_intr =0x0004,
350 debug_selection =0x0008,
351 debug_msgo =0x0010,
352 debug_msgi =0x0020,
353 debug_status =0x0040,
354 debug_cmd =0x0080,
355 debug_datai =0x0100,
356 debug_datao =0x0200,
357 debug_abort =0x0400,
358 debug_done =0x0800,
359 debug_biosparam =0x1000,
360 debug_phases =0x2000,
361 debug_queues =0x4000,
362 debug_reset =0x8000,
363 };
364 #endif
365
366 #endif