root/drivers/scsi/53c7,8xx.h

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   1 /*
   2  * NCR 53c{7,8}0x0 driver, header file
   3  *
   4  * Sponsored by
   5  *      iX Multiuser Multitasking Magazine
   6  *      Hannover, Germany
   7  *      hm@ix.de        
   8  *
   9  * Copyright 1993, Drew Eckhardt
  10  *      Visionary Computing 
  11  *      (Unix and Linux consulting and custom programming)
  12  *      drew@Colorado.EDU
  13  *      +1 (303) 786-7975
  14  *
  15  * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
  16  * 
  17  * PRE-ALPHA
  18  *
  19  * For more information, please consult 
  20  *
  21  * NCR 53C700/53C700-66
  22  * SCSI I/O Processor
  23  * Data Manual
  24  *
  25  * NCR 53C810
  26  * PCI-SCSI I/O Processor 
  27  * Data Manual
  28  *
  29  * NCR Microelectronics
  30  * 1635 Aeroplaza Drive
  31  * Colorado Springs, CO 80916
  32  * +1 (719) 578-3400
  33  *
  34  * Toll free literature number
  35  * +1 (800) 334-5454
  36  *
  37  */
  38 
  39 #ifndef NCR53c7x0_H
  40 #define NCR53c7x0_H
  41 
  42 #ifdef __alpha__
  43 
  44 # define ncr_readb(a)           ((unsigned int)readb((unsigned long)(a)))
  45 # define ncr_readw(a)           ((unsigned int)readw((unsigned long)(a)))
  46 # define ncr_readl(a)           ((unsigned int)readl((unsigned long)(a)))
  47 # define ncr_writeb(v,a)        (writeb((v), (unsigned long)(a)))
  48 # define ncr_writew(v,a)        (writew((v), (unsigned long)(a)))
  49 # define ncr_writel(v,a)        (writel((v), (unsigned long)(a)))
  50 
  51 #else
  52 
  53 # define ncr_readb(a)           (*(unsigned char*)(a))
  54 # define ncr_readw(a)           (*(unsigned short*)(a))
  55 # define ncr_readl(a)           (*(unsigned int*)(a))
  56 # define ncr_writeb(v,a)        (*(unsigned char*)(a) = (v))
  57 # define ncr_writew(v,a)        (*(unsigned short*)(a) = (v))
  58 # define ncr_writel(v,a)        (*(unsigned int*)(a) = (v))
  59 
  60 #endif
  61 
  62 
  63 /* 
  64  * Prevent name space pollution in hosts.c, and only provide the 
  65  * define we need to get the NCR53c7x0 driver into the host template
  66  * array.
  67  */
  68 
  69 #if defined(HOSTS_C) || defined(MODULE)
  70 #include <linux/scsicam.h>
  71 extern int NCR53c7xx_abort(Scsi_Cmnd *);
  72 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
  73 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  74 extern int NCR53c7xx_reset(Scsi_Cmnd *);
  75 #ifdef MODULE
  76 extern int NCR53c7xx_release(struct Scsi_Host *);
  77 #else
  78 #define NCR53c7xx_release NULL
  79 #endif
  80 
  81 extern int generic_proc_info(char *, char **, off_t, int, int, int);
  82 
  83 #define NCR53c7xx {NULL, NULL, generic_proc_info, "NCR53c7xx",          \
  84         PROC_SCSI_NCR53C7xx, "NCR53c{7,8}xx (rel 4)", NCR53c7xx_detect, \
  85         NULL, /* info */ NULL, /* command, deprecated */ NULL,          \
  86         NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset,      \
  87         NULL /* slave attach */, scsicam_bios_param, /* can queue */ 1, \
  88         /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 1 ,         \
  89         /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING} 
  90 #endif /* defined(HOSTS_C) || defined(MODULE) */ 
  91 
  92 #ifndef HOSTS_C
  93 /* Register addresses, ordered numerically */
  94 
  95 
  96 /* SCSI control 0 rw, default = 0xc0 */ 
  97 #define SCNTL0_REG              0x00    
  98 #define SCNTL0_ARB1             0x80    /* 0 0 = simple arbitration */
  99 #define SCNTL0_ARB2             0x40    /* 1 1 = full arbitration */
 100 #define SCNTL0_STRT             0x20    /* Start Sequence */
 101 #define SCNTL0_WATN             0x10    /* Select with ATN */
 102 #define SCNTL0_EPC              0x08    /* Enable parity checking */
 103 /* Bit 2 is reserved on 800 series chips */
 104 #define SCNTL0_EPG_700          0x04    /* Enable parity generation */
 105 #define SCNTL0_AAP              0x02    /*  ATN/ on parity error */
 106 #define SCNTL0_TRG              0x01    /* Target mode */
 107 
 108 /* SCSI control 1 rw, default = 0x00 */
 109 
 110 #define SCNTL1_REG              0x01    
 111 #define SCNTL1_EXC              0x80    /* Extra Clock Cycle of Data setup */
 112 #define SCNTL1_ADB              0x40    /*  contents of SODL on bus */
 113 #define SCNTL1_ESR_700          0x20    /* Enable SIOP response to selection 
 114                                            and reselection */
 115 #define SCNTL1_DHP_800          0x20    /* Disable halt on parity error or ATN
 116                                            target mode only */
 117 #define SCNTL1_CON              0x10    /* Connected */
 118 #define SCNTL1_RST              0x08    /*  SCSI RST/ */
 119 #define SCNTL1_AESP             0x04    /* Force bad parity */
 120 #define SCNTL1_SND_700          0x02    /* Start SCSI send */
 121 #define SCNTL1_IARB_800         0x02    /* Immediate Arbitration, start
 122                                            arbitration immediately after
 123                                            busfree is detected */
 124 #define SCNTL1_RCV_700          0x01    /* Start SCSI receive */
 125 #define SCNTL1_SST_800          0x01    /* Start SCSI transfer */
 126 
 127 /* SCSI control 2 rw, */
 128 
 129 #define SCNTL2_REG_800          0x02    
 130 #define SCNTL2_800_SDU          0x80    /* SCSI disconnect unexpected */
 131 
 132 /* SCSI control 3 rw */
 133 
 134 #define SCNTL3_REG_800          0x03    
 135 #define SCNTL3_800_SCF_SHIFT    4
 136 #define SCNTL3_800_SCF_MASK     0x70
 137 #define SCNTL3_800_SCF2         0x40    /* Synchronous divisor */
 138 #define SCNTL3_800_SCF1         0x20    /* 0x00 = SCLK/3 */
 139 #define SCNTL3_800_SCF0         0x10    /* 0x10 = SCLK/1 */
 140                                         /* 0x20 = SCLK/1.5 
 141                                            0x30 = SCLK/2 
 142                                            0x40 = SCLK/3 */
 143             
 144 #define SCNTL3_800_CCF_SHIFT    0
 145 #define SCNTL3_800_CCF_MASK     0x07
 146 #define SCNTL3_800_CCF2         0x04    /* 0x00 50.01 to 66 */
 147 #define SCNTL3_800_CCF1         0x02    /* 0x01 16.67 to 25 */
 148 #define SCNTL3_800_CCF0         0x01    /* 0x02 25.01 - 37.5 
 149                                            0x03 37.51 - 50 
 150                                            0x04 50.01 - 66 */
 151 
 152 /*  
 153  * SCSI destination ID rw - the appropriate bit is set for the selected
 154  * target ID.  This is written by the SCSI SCRIPTS processor.
 155  * default = 0x00
 156  */
 157 #define SDID_REG_700            0x02    
 158 #define SDID_REG_800            0x06
 159 
 160 #define GP_REG_800              0x07    /* General purpose IO */
 161 #define GP_800_IO1              0x02
 162 #define GP_800_IO2              0x01
 163 
 164 
 165 /* SCSI interrupt enable rw, default = 0x00 */
 166 #define SIEN_REG_700            0x03    
 167 #define SIEN0_REG_800           0x40
 168 #define SIEN_MA                 0x80    /* Phase mismatch (ini) or ATN (tgt) */
 169 #define SIEN_FC                 0x40    /* Function complete */
 170 #define SIEN_700_STO            0x20    /* Selection or reselection timeout */
 171 #define SIEN_800_SEL            0x20    /* Selected */
 172 #define SIEN_700_SEL            0x10    /* Selected or reselected */
 173 #define SIEN_800_RESEL          0x10    /* Reselected */
 174 #define SIEN_SGE                0x08    /* SCSI gross error */
 175 #define SIEN_UDC                0x04    /* Unexpected disconnect */
 176 #define SIEN_RST                0x02    /* SCSI RST/ received */
 177 #define SIEN_PAR                0x01    /* Parity error */
 178 
 179 /* 
 180  * SCSI chip ID rw
 181  * NCR53c700 : 
 182  *      When arbitrating, the highest bit is used, when reselection or selection
 183  *      occurs, the chip responds to all IDs for which a bit is set.
 184  *      default = 0x00 
 185  * NCR53c810 : 
 186  *      Uses bit mapping
 187  */
 188 #define SCID_REG                0x04    
 189 /* Bit 7 is reserved on 800 series chips */
 190 #define SCID_800_RRE            0x40    /* Enable response to reselection */
 191 #define SCID_800_SRE            0x20    /* Enable response to selection */
 192 /* Bits four and three are reserved on 800 series chips */
 193 #define SCID_800_ENC_MASK       0x07    /* Encoded SCSI ID */
 194 
 195 /* SCSI transfer rw, default = 0x00 */
 196 #define SXFER_REG               0x05
 197 #define SXFER_DHP               0x80    /* Disable halt on parity */
 198 
 199 #define SXFER_TP2               0x40    /* Transfer period msb */
 200 #define SXFER_TP1               0x20
 201 #define SXFER_TP0               0x10    /* lsb */
 202 #define SXFER_TP_MASK           0x70
 203 #define SXFER_TP_SHIFT          4
 204 #define SXFER_TP_4              0x00    /* Divisors */
 205 #define SXFER_TP_5              0x10
 206 #define SXFER_TP_6              0x20
 207 #define SXFER_TP_7              0x30
 208 #define SXFER_TP_8              0x40
 209 #define SXFER_TP_9              0x50
 210 #define SXFER_TP_10             0x60
 211 #define SXFER_TP_11             0x70
 212 
 213 #define SXFER_MO3               0x08    /* Max offset msb */
 214 #define SXFER_MO2               0x04
 215 #define SXFER_MO1               0x02
 216 #define SXFER_MO0               0x01    /* lsb */
 217 #define SXFER_MO_MASK           0x0f
 218 #define SXFER_MO_SHIFT          0
 219 
 220 /* 
 221  * SCSI output data latch rw
 222  * The contents of this register are driven onto the SCSI bus when 
 223  * the Assert Data Bus bit of the SCNTL1 register is set and 
 224  * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
 225  */
 226 #define SODL_REG_700            0x06    
 227 #define SODL_REG_800            0x54
 228 
 229 
 230 /* 
 231  * SCSI output control latch rw, default = 0 
 232  * Note that when the chip is being manually programmed as an initiator,
 233  * the MSG, CD, and IO bits must be set correctly for the phase the target
 234  * is driving the bus in.  Otherwise no data transfer will occur due to 
 235  * phase mismatch.
 236  */
 237 
 238 #define SBCL_REG                0x0b
 239 #define SBCL_REQ                0x80    /*  REQ */
 240 #define SBCL_ACK                0x40    /*  ACK */
 241 #define SBCL_BSY                0x20    /*  BSY */
 242 #define SBCL_SEL                0x10    /*  SEL */
 243 #define SBCL_ATN                0x08    /*  ATN */
 244 #define SBCL_MSG                0x04    /*  MSG */
 245 #define SBCL_CD                 0x02    /*  C/D */
 246 #define SBCL_IO                 0x01    /*  I/O */
 247 #define SBCL_PHASE_CMDOUT       SBCL_CD
 248 #define SBCL_PHASE_DATAIN       SBCL_IO
 249 #define SBCL_PHASE_DATAOUT      0
 250 #define SBCL_PHASE_MSGIN        (SBCL_CD|SBCL_IO|SBCL_MSG)
 251 #define SBCL_PHASE_MSGOUT       (SBCL_CD|SBCL_MSG)
 252 #define SBCL_PHASE_STATIN       (SBCL_CD|SBCL_IO)
 253 #define SBCL_PHASE_MASK         (SBCL_CD|SBCL_IO|SBCL_MSG)
 254 
 255 /* 
 256  * SCSI first byte received latch ro 
 257  * This register contains the first byte received during a block MOVE 
 258  * SCSI SCRIPTS instruction, including
 259  * 
 260  * Initiator mode       Target mode
 261  * Message in           Command
 262  * Status               Message out
 263  * Data in              Data out
 264  *
 265  * It also contains the selecting or reselecting device's ID and our 
 266  * ID.
 267  *
 268  * Note that this is the register the various IF conditionals can 
 269  * operate on.
 270  */
 271 #define SFBR_REG                0x08    
 272 
 273 /* 
 274  * SCSI input data latch ro
 275  * In initiator mode, data is latched into this register on the rising
 276  * edge of REQ/. In target mode, data is latched on the rising edge of 
 277  * ACK/
 278  */
 279 #define SIDL_REG_700            0x09
 280 #define SIDL_REG_800            0x50
 281 
 282 /* 
 283  * SCSI bus data lines ro 
 284  * This register reflects the instantaneous status of the SCSI data 
 285  * lines.  Note that SCNTL0 must be set to disable parity checking, 
 286  * otherwise reading this register will latch new parity.
 287  */
 288 #define SBDL_REG_700            0x0a
 289 #define SBDL_REG_800            0x58
 290 
 291 #define SSID_REG_800            0x0a
 292 #define SSID_800_VAL            0x80    /* Exactly two bits asserted at sel */
 293 #define SSID_800_ENCID_MASK     0x07    /* Device which performed operation */
 294 
 295 
 296 /* 
 297  * SCSI bus control lines rw, 
 298  * instantaneous readout of control lines 
 299  */
 300 #define SOCL_REG                0x0b    
 301 #define SOCL_REQ                0x80    /*  REQ ro */
 302 #define SOCL_ACK                0x40    /*  ACK ro */
 303 #define SOCL_BSY                0x20    /*  BSY ro */
 304 #define SOCL_SEL                0x10    /*  SEL ro */
 305 #define SOCL_ATN                0x08    /*  ATN ro */
 306 #define SOCL_MSG                0x04    /*  MSG ro */
 307 #define SOCL_CD                 0x02    /*  C/D ro */
 308 #define SOCL_IO                 0x01    /*  I/O ro */
 309 /* 
 310  * Synchronous SCSI Clock Control bits 
 311  * 0 - set by DCNTL 
 312  * 1 - SCLK / 1.0
 313  * 2 - SCLK / 1.5
 314  * 3 - SCLK / 2.0 
 315  */
 316 #define SBCL_SSCF1              0x02    /* wo, -66 only */
 317 #define SBCL_SSCF0              0x01    /* wo, -66 only */
 318 #define SBCL_SSCF_MASK          0x03
 319 
 320 /* 
 321  * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
 322  * insure that 10 clocks elapse between the two  
 323  */
 324 /* DMA status ro */
 325 #define DSTAT_REG               0x0c    
 326 #define DSTAT_DFE               0x80    /* DMA FIFO empty */
 327 #define DSTAT_800_MDPE          0x40    /* Master Data Parity Error */
 328 #define DSTAT_800_BF            0x20    /* Bus Fault */
 329 #define DSTAT_ABRT              0x10    /* Aborted - set on error */
 330 #define DSTAT_SSI               0x08    /* SCRIPTS single step interrupt */
 331 #define DSTAT_SIR               0x04    /* SCRIPTS interrupt received - 
 332                                            set when INT instruction is 
 333                                            executed */
 334 #define DSTAT_WTD               0x02    /* Watchdog timeout detected */
 335 #define DSTAT_OPC               0x01    /* Illegal instruction */
 336 #define DSTAT_800_IID           0x01    /* Same thing, different name */
 337 
 338 
 339 #define SSTAT0_REG              0x0d    /* SCSI status 0 ro */
 340 #define SIST0_REG_800           0x42    
 341 #define SSTAT0_MA               0x80    /* ini : phase mismatch,
 342                                          * tgt : ATN/ asserted 
 343                                          */
 344 #define SSTAT0_CMP              0x40    /* function complete */
 345 #define SSTAT0_700_STO          0x20    /* Selection or reselection timeout */
 346 #define SIST0_800_SEL           0x20    /* Selected */
 347 #define SSTAT0_700_SEL          0x10    /* Selected or reselected */
 348 #define SIST0_800_RSL           0x10    /* Reselected */
 349 #define SSTAT0_SGE              0x08    /* SCSI gross error */
 350 #define SSTAT0_UDC              0x04    /* Unexpected disconnect */
 351 #define SSTAT0_RST              0x02    /* SCSI RST/ received */
 352 #define SSTAT0_PAR              0x01    /* Parity error */
 353 
 354 #define SSTAT1_REG              0x0e    /* SCSI status 1 ro */
 355 #define SSTAT1_ILF              0x80    /* SIDL full */
 356 #define SSTAT1_ORF              0x40    /* SODR full */
 357 #define SSTAT1_OLF              0x20    /* SODL full */
 358 #define SSTAT1_AIP              0x10    /* Arbitration in progress */
 359 #define SSTAT1_LOA              0x08    /* Lost arbitration */
 360 #define SSTAT1_WOA              0x04    /* Won arbitration */
 361 #define SSTAT1_RST              0x02    /* Instant readout of RST/ */
 362 #define SSTAT1_SDP              0x01    /* Instant readout of SDP/ */
 363 
 364 #define SSTAT2_REG              0x0f    /* SCSI status 2 ro */
 365 #define SSTAT2_FF3              0x80    /* number of bytes in synchronous */
 366 #define SSTAT2_FF2              0x40    /* data FIFO */
 367 #define SSTAT2_FF1              0x20    
 368 #define SSTAT2_FF0              0x10
 369 #define SSTAT2_FF_MASK          0xf0
 370 
 371 /* 
 372  * Latched signals, latched on the leading edge of REQ/ for initiators,
 373  * ACK/ for targets.
 374  */
 375 #define SSTAT2_SDP              0x08    /* SDP */
 376 #define SSTAT2_MSG              0x04    /* MSG */
 377 #define SSTAT2_CD               0x02    /* C/D */
 378 #define SSTAT2_IO               0x01    /* I/O */
 379 
 380 
 381 /* NCR53c700-66 only */
 382 #define SCRATCHA_REG_00         0x10    /* through  0x13 Scratch A rw */
 383 /* NCR53c710 and higher */
 384 #define DSA_REG                 0x10    /* DATA structure address */
 385 
 386 #define CTEST0_REG_700          0x14    /* Chip test 0 ro */
 387 #define CTEST0_REG_800          0x18    /* Chip test 0 rw, general purpose */
 388 /* 0x80 - 0x04 are reserved */
 389 #define CTEST0_700_RTRG         0x02    /* Real target mode */
 390 #define CTEST0_700_DDIR         0x01    /* Data direction, 1 = 
 391                                          * SCSI bus to host, 0  =
 392                                          * host to SCSI.
 393                                          */
 394 
 395 #define CTEST1_REG_700          0x15    /* Chip test 1 ro */
 396 #define CTEST1_REG_800          0x19    /* Chip test 1 ro */
 397 #define CTEST1_FMT3             0x80    /* Identify which byte lanes are empty */
 398 #define CTEST1_FMT2             0x40    /* in the DMA FIFO */
 399 #define CTEST1_FMT1             0x20
 400 #define CTEST1_FMT0             0x10
 401 
 402 #define CTEST1_FFL3             0x08    /* Identify which bytes lanes are full */
 403 #define CTEST1_FFL2             0x04    /* in the DMA FIFO */
 404 #define CTEST1_FFL1             0x02
 405 #define CTEST1_FFL0             0x01
 406 
 407 #define CTEST2_REG_700          0x16    /* Chip test 2 ro */
 408 #define CTEST2_REG_800          0x1a    /* Chip test 2 ro */
 409 
 410 #define CTEST2_800_DDIR         0x80    /* 1 = SCSI->host */
 411 #define CTEST2_800_SIGP         0x40    /* A copy of SIGP in ISTAT.
 412                                            Reading this register clears */
 413 #define CTEST2_800_CIO          0x20    /* Configured as IO */.
 414 #define CTEST2_800_CM           0x10    /* Configured as memory */
 415 
 416 /* 0x80 - 0x40 are reserved on 700 series chips */
 417 #define CTEST2_700_SOFF         0x20    /* SCSI Offset Compare,
 418                                          * As an initiator, this bit is 
 419                                          * one when the synchronous offset
 420                                          * is zero, as a target this bit 
 421                                          * is one when the synchronous 
 422                                          * offset is at the maximum
 423                                          * defined in SXFER
 424                                          */
 425 #define CTEST2_700_SFP          0x10    /* SCSI FIFO parity bit,
 426                                          * reading CTEST3 unloads a byte
 427                                          * from the FIFO and sets this
 428                                          */
 429 #define CTEST2_700_DFP          0x08    /* DMA FIFO parity bit,
 430                                          * reading CTEST6 unloads a byte
 431                                          * from the FIFO and sets this
 432                                          */
 433 #define CTEST2_TEOP             0x04    /* SCSI true end of process,
 434                                          * indicates a totally finished
 435                                          * transfer
 436                                          */
 437 #define CTEST2_DREQ             0x02    /* Data request signal */
 438 /* 0x01 is reserved on 700 series chips */
 439 #define CTEST2_800_DACK         0x01    
 440 
 441 /* 
 442  * Chip test 3 ro 
 443  * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
 444  * check SSTAT2 FIFO full bits to determine size.  Note that a GROSS
 445  * error results if a read is attempted on this register.  Also note 
 446  * that 16 and 32 bit reads of this register will cause corruption.
 447  */
 448 #define CTEST3_REG_700          0x17    
 449 /*  Chip test 3 rw */
 450 #define CTEST3_REG_800          0x1b
 451 #define CTEST3_800_V3           0x80    /* Chip revision */
 452 #define CTEST3_800_V2           0x40
 453 #define CTEST3_800_V1           0x20
 454 #define CTEST3_800_V0           0x10
 455 #define CTEST3_800_FLF          0x08    /* Flush DMA FIFO */
 456 #define CTEST3_800_CLF          0x04    /* Clear DMA FIFO */
 457 #define CTEST3_800_FM           0x02    /* Fetch mode pin */
 458 /* bit 0 is reserved on 800 series chips */
 459 
 460 #define CTEST4_REG_700          0x18    /* Chip test 4 rw */
 461 #define CTEST4_REG_800          0x21    /* Chip test 4 rw */
 462 /* 0x80 is reserved on 700 series chips */
 463 #define CTEST4_800_BDIS         0x80    /* Burst mode disable */
 464 #define CTEST4_ZMOD             0x40    /* High impedance mode */
 465 #define CTEST4_SZM              0x20    /* SCSI bus high impedance */
 466 #define CTEST4_700_SLBE         0x10    /* SCSI loopback enabled */
 467 #define CTEST4_800_SRTM         0x10    /* Shadow Register Test Mode */
 468 #define CTEST4_700_SFWR         0x08    /* SCSI FIFO write enable, 
 469                                          * redirects writes from SODL
 470                                          * to the SCSI FIFO.
 471                                          */
 472 #define CTEST4_800_MPEE         0x08    /* Enable parity checking
 473                                            during master cycles on PCI
 474                                            bus */
 475 
 476 /* 
 477  * These bits send the contents of the CTEST6 register to the appropriate
 478  * byte lane of the 32 bit DMA FIFO.  Normal operation is zero, otherwise 
 479  * the high bit means the low two bits select the byte lane.
 480  */
 481 #define CTEST4_FBL2             0x04    
 482 #define CTEST4_FBL1             0x02
 483 #define CTEST4_FBL0             0x01    
 484 #define CTEST4_FBL_MASK         0x07
 485 #define CTEST4_FBL_0            0x04    /* Select DMA FIFO byte lane 0 */
 486 #define CTEST4_FBL_1            0x05    /* Select DMA FIFO byte lane 1 */
 487 #define CTEST4_FBL_2            0x06    /* Select DMA FIFO byte lane 2 */
 488 #define CTEST4_FBL_3            0x07    /* Select DMA FIFO byte lane 3 */
 489 #define CTEST4_800_SAVE         (CTEST4_800_BDIS)
 490 
 491 
 492 #define CTEST5_REG_700          0x19    /* Chip test 5 rw */
 493 #define CTEST5_REG_800          0x22    /* Chip test 5 rw */
 494 /* 
 495  * Clock Address Incrementor.  When set, it increments the 
 496  * DNAD register to the next bus size boundary.  It automatically 
 497  * resets itself when the operation is complete.
 498  */
 499 #define CTEST5_ADCK             0x80
 500 /*
 501  * Clock Byte Counter.  When set, it decrements the DBC register to
 502  * the next bus size boundary.
 503  */
 504 #define CTEST5_BBCK             0x40
 505 /*
 506  * Reset SCSI Offset.  Setting this bit to 1 clears the current offset
 507  * pointer in the SCSI synchronous offset counter (SSTAT).  This bit
 508  * is set to 1 if a SCSI Gross Error Condition occurs.  The offset should
 509  * be cleared when a synchronous transfer fails.  When written, it is 
 510  * automatically cleared after the SCSI synchronous offset counter is 
 511  * reset.
 512  */
 513 /* Bit 5 is reserved on 800 series chips */
 514 #define CTEST5_700_ROFF         0x20
 515 /* 
 516  * Master Control for Set or Reset pulses. When 1, causes the low 
 517  * four bits of register to set when set, 0 causes the low bits to
 518  * clear when set.
 519  */
 520 #define CTEST5_MASR             0x10    
 521 #define CTEST5_DDIR             0x08    /* DMA direction */
 522 /*
 523  * Bits 2-0 are reserved on 800 series chips
 524  */
 525 #define CTEST5_700_EOP          0x04    /* End of process */
 526 #define CTEST5_700_DREQ         0x02    /* Data request */
 527 #define CTEST5_700_DACK         0x01    /* Data acknowledge */
 528 
 529 /* 
 530  * Chip test 6 rw - writing to this register writes to the byte 
 531  * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
 532  * register.
 533  */
 534 #define CTEST6_REG_700          0x1a
 535 #define CTEST6_REG_800          0x23
 536 
 537 #define CTEST7_REG              0x1b    /* Chip test 7 rw */
 538 /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
 539 #define CTEST7_10_CDIS          0x80    /* Cache burst disable */
 540 #define CTEST7_10_SC1           0x40    /* Snoop control bits */
 541 #define CTEST7_10_SC0           0x20    
 542 #define CTEST7_10_SC_MASK       0x60
 543 /* 0x20 is reserved on the NCR53c700 */
 544 #define CTEST7_0060_FM          0x20    /* Fetch mode */
 545 #define CTEST7_STD              0x10    /* Selection timeout disable */
 546 #define CTEST7_DFP              0x08    /* DMA FIFO parity bit for CTEST6 */
 547 #define CTEST7_EVP              0x04    /* 1 = host bus even parity, 0 = odd */
 548 #define CTEST7_10_TT1           0x02    /* Transfer type */
 549 #define CTEST7_00_DC            0x02    /* Set to drive DC low during instruction 
 550                                            fetch */
 551 #define CTEST7_DIFF             0x01    /* Differential mode */
 552 
 553 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
 554 
 555 
 556 #define TEMP_REG                0x1c    /* through 0x1f Temporary stack rw */
 557 
 558 #define DFIFO_REG               0x20    /* DMA FIFO rw */
 559 /* 
 560  * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
 561  * moved into the CTEST8 register.
 562  */
 563 #define DFIFO_00_FLF            0x80    /* Flush DMA FIFO to memory */
 564 #define DFIFO_00_CLF            0x40    /* Clear DMA and SCSI FIFOs */
 565 #define DFIFO_BO6               0x40
 566 #define DFIFO_BO5               0x20
 567 #define DFIFO_BO4               0x10
 568 #define DFIFO_BO3               0x08
 569 #define DFIFO_BO2               0x04 
 570 #define DFIFO_BO1               0x02
 571 #define DFIFO_BO0               0x01
 572 #define DFIFO_10_BO_MASK        0x7f    /* 7 bit counter */
 573 #define DFIFO_00_BO_MASK        0x3f    /* 6 bit counter */
 574 
 575 /* 
 576  * Interrupt status rw 
 577  * Note that this is the only register which can be read while SCSI
 578  * SCRIPTS are being executed.
 579  */
 580 #define ISTAT_REG_700           0x21
 581 #define ISTAT_REG_800           0x14
 582 #define ISTAT_ABRT              0x80    /* Software abort, write 
 583                                          *1 to abort, wait for interrupt. */
 584 /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
 585 #define ISTAT_10_SRST           0x40    /* software reset */
 586 #define ISTAT_10_SIGP           0x20    /* signal script */
 587 /* 0x10 is reserved on NCR53c700 series chips */
 588 #define ISTAT_800_SEM           0x10    /* semaphore */
 589 #define ISTAT_CON               0x08    /* 1 when connected */
 590 #define ISTAT_800_INTF          0x04    /* Interrupt on the fly */
 591 #define ISTAT_700_PRE           0x04    /* Pointer register empty.
 592                                          * Set to 1 when DSPS and DSP
 593                                          * registers are empty in pipeline
 594                                          * mode, always set otherwise.
 595                                          */
 596 #define ISTAT_SIP               0x02    /* SCSI interrupt pending from
 597                                          * SCSI portion of SIOP see
 598                                          * SSTAT0
 599                                          */
 600 #define ISTAT_DIP               0x01    /* DMA interrupt pending 
 601                                          * see DSTAT
 602                                          */
 603 
 604 /* NCR53c700-66 and NCR53c710 only */
 605 #define CTEST8_REG              0x22    /* Chip test 8 rw */
 606 #define CTEST8_0066_EAS         0x80    /* Enable alternate SCSI clock,
 607                                          * ie read from SCLK/ rather than CLK/
 608                                          */
 609 #define CTEST8_0066_EFM         0x40    /* Enable fetch and master outputs */
 610 #define CTEST8_0066_GRP         0x20    /* Generate Receive Parity for 
 611                                          * pass through.  This insures that 
 612                                          * bad parity won't reach the host 
 613                                          * bus.
 614                                          */
 615 #define CTEST8_0066_TE          0x10    /* TolerANT enable.  Enable 
 616                                          * active negation, should only
 617                                          * be used for slow SCSI 
 618                                          * non-differential.
 619                                          */
 620 #define CTEST8_0066_HSC         0x08    /* Halt SCSI clock */
 621 #define CTEST8_0066_SRA         0x04    /* Shorten REQ/ACK filtering,
 622                                          * must be set for fast SCSI-II
 623                                          * speeds.
 624                                          */
 625 #define CTEST8_0066_DAS         0x02    /* Disable automatic target/initiator
 626                                          * switching.
 627                                          */
 628 #define CTEST8_0066_LDE         0x01    /* Last disconnect enable.
 629                                          * The status of pending 
 630                                          * disconnect is maintained by
 631                                          * the core, eliminating
 632                                          * the possibility of missing a 
 633                                          * selection or reselection
 634                                          * while waiting to fetch a 
 635                                          * WAIT DISCONNECT opcode.
 636                                          */
 637 
 638 #define CTEST8_10_V3            0x80    /* Chip revision */
 639 #define CTEST8_10_V2            0x40
 640 #define CTEST8_10_V1            0x20    
 641 #define CTEST8_10_V0            0x10
 642 #define CTEST8_10_V_MASK        0xf0    
 643 #define CTEST8_10_FLF           0x08    /* Flush FIFOs */
 644 #define CTEST8_10_CLF           0x04    /* Clear FIFOs */
 645 #define CTEST8_10_FM            0x02    /* Fetch pin mode */
 646 #define CTEST8_10_SM            0x01    /* Snoop pin mode */
 647 
 648 
 649 /* 
 650  * The CTEST9 register may be used to differentiate between a
 651  * NCR53c700 and a NCR53c710.  
 652  *
 653  * Write 0xff to this register.
 654  * Read it.
 655  * If the contents are 0xff, it is a NCR53c700
 656  * If the contents are 0x00, it is a NCR53c700-66 first revision
 657  * If the contents are some other value, it is some other NCR53c700-66
 658  */
 659 #define CTEST9_REG_00           0x23    /* Chip test 9 ro */
 660 #define LCRC_REG_10             0x23    
 661 
 662 /*
 663  * 0x24 through 0x27 are the DMA byte counter register.  Instructions
 664  * write their high 8 bits into the DCMD register, the low 24 bits into
 665  * the DBC register.
 666  *
 667  * Function is dependent on the command type being executed.
 668  */
 669 
 670  
 671 #define DBC_REG                 0x24
 672 /* 
 673  * For Block Move Instructions, DBC is a 24 bit quantity representing 
 674  *     the number of bytes to transfer.
 675  * For Transfer Control Instructions, DBC is bit fielded as follows : 
 676  */
 677 /* Bits 20 - 23 should be clear */
 678 #define DBC_TCI_TRUE            (1 << 19)       /* Jump when true */
 679 #define DBC_TCI_COMPARE_DATA    (1 << 18)       /* Compare data */
 680 #define DBC_TCI_COMPARE_PHASE   (1 << 17)       /* Compare phase with DCMD field */
 681 #define DBC_TCI_WAIT_FOR_VALID  (1 << 16)       /* Wait for REQ */
 682 /* Bits 8 - 15 are reserved on some implementations ? */
 683 #define DBC_TCI_MASK_MASK       0xff00          /* Mask for data compare */
 684 #define DBC_TCI_MASK_SHIFT      8
 685 #define DBC_TCI_DATA_MASK       0xff            /* Data to be compared */ 
 686 #define DBC_TCI_DATA_SHIFT      0
 687 
 688 #define DBC_RWRI_IMMEDIATE_MASK 0xff00          /* Immediate data */
 689 #define DBC_RWRI_IMMEDIATE_SHIFT 8              /* Amount to shift */
 690 #define DBC_RWRI_ADDRESS_MASK   0x3f0000        /* Register address */
 691 #define DBC_RWRI_ADDRESS_SHIFT  16
 692 
 693 
 694 /*
 695  * DMA command r/w
 696  */
 697 #define DCMD_REG                0x27    
 698 #define DCMD_TYPE_MASK          0xc0    /* Masks off type */
 699 #define DCMD_TYPE_BMI           0x00    /* Indicates a Block Move instruction */
 700 #define DCMD_BMI_IO             0x01    /* I/O, CD, and MSG bits selecting   */
 701 #define DCMD_BMI_CD             0x02    /* the phase for the block MOVE      */
 702 #define DCMD_BMI_MSG            0x04    /* instruction                       */
 703 
 704 #define DCMD_BMI_OP_MASK        0x18    /* mask for opcode */
 705 #define DCMD_BMI_OP_MOVE_T      0x00    /* MOVE */
 706 #define DCMD_BMI_OP_MOVE_I      0x08    /* MOVE Initiator */
 707 
 708 #define DCMD_BMI_INDIRECT       0x20    /*  Indirect addressing */
 709 
 710 #define DCMD_TYPE_TCI           0x80    /* Indicates a Transfer Control 
 711                                            instruction */
 712 #define DCMD_TCI_IO             0x01    /* I/O, CD, and MSG bits selecting   */
 713 #define DCMD_TCI_CD             0x02    /* the phase for the block MOVE      */
 714 #define DCMD_TCI_MSG            0x04    /* instruction                       */
 715 #define DCMD_TCI_OP_MASK        0x38    /* mask for opcode */
 716 #define DCMD_TCI_OP_JUMP        0x00    /* JUMP */
 717 #define DCMD_TCI_OP_CALL        0x08    /* CALL */
 718 #define DCMD_TCI_OP_RETURN      0x10    /* RETURN */
 719 #define DCMD_TCI_OP_INT         0x18    /* INT */
 720 
 721 #define DCMD_TYPE_RWRI          0x40    /* Indicates I/O or register Read/Write
 722                                            instruction */
 723 #define DCMD_RWRI_OPC_MASK      0x38    /* Opcode mask */
 724 #define DCMD_RWRI_OPC_WRITE     0x28    /* Write SFBR to register */
 725 #define DCMD_RWRI_OPC_READ      0x30    /* Read register to SFBR */
 726 #define DCMD_RWRI_OPC_MODIFY    0x38    /* Modify in place */
 727 
 728 #define DCMD_RWRI_OP_MASK       0x07
 729 #define DCMD_RWRI_OP_MOVE       0x00
 730 #define DCMD_RWRI_OP_SHL        0x01
 731 #define DCMD_RWRI_OP_OR         0x02
 732 #define DCMD_RWRI_OP_XOR        0x03
 733 #define DCMD_RWRI_OP_AND        0x04
 734 #define DCMD_RWRI_OP_SHR        0x05
 735 #define DCMD_RWRI_OP_ADD        0x06
 736 #define DCMD_RWRI_OP_ADDC       0x07
 737 
 738 #define DCMD_TYPE_MMI           0xc0    /* Indicates a Memory Move instruction 
 739                                            (three words) */
 740 
 741 
 742 #define DNAD_REG                0x28    /* through 0x2b DMA next address for 
 743                                            data */
 744 #define DSP_REG                 0x2c    /* through 0x2f DMA SCRIPTS pointer rw */
 745 #define DSPS_REG                0x30    /* through 0x33 DMA SCRIPTS pointer 
 746                                            save rw */
 747 #define DMODE_REG_00            0x34    /* DMA mode rw */
 748 #define DMODE_00_BL1    0x80    /* Burst length bits */
 749 #define DMODE_00_BL0    0x40
 750 #define DMODE_BL_MASK   0xc0
 751 /* Burst lengths (800) */
 752 #define DMODE_BL_2      0x00    /* 2 transfer */
 753 #define DMODE_BL_4      0x40    /* 4 transfers */
 754 #define DMODE_BL_8      0x80    /* 8 transfers */
 755 #define DMODE_BL_16     0xc0    /* 16 transfers */
 756 
 757 #define DMODE_700_BW16  0x20    /* Host buswidth = 16 */
 758 #define DMODE_700_286   0x10    /* 286 mode */
 759 #define DMODE_700_IOM   0x08    /* Transfer to IO port */
 760 #define DMODE_700_FAM   0x04    /* Fixed address mode */
 761 #define DMODE_700_PIPE  0x02    /* Pipeline mode disables 
 762                                          * automatic fetch / exec 
 763                                          */
 764 #define DMODE_MAN       0x01            /* Manual start mode, 
 765                                          * requires a 1 to be written
 766                                          * to the start DMA bit in the DCNTL
 767                                          * register to run scripts 
 768                                          */
 769 
 770 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
 771 
 772 /* NCR53c800 series only */
 773 #define SCRATCHA_REG_800        0x34    /* through 0x37 Scratch A rw */
 774 /* NCR53c710 only */
 775 #define SCRATCB_REG_10          0x34    /* through 0x37 scratch B rw */
 776 
 777 #define DMODE_REG_10            0x38    /* DMA mode rw, NCR53c710 and newer */
 778 #define DMODE_800_SIOM          0x20    /* Source IO = 1 */
 779 #define DMODE_800_DIOM          0x10    /* Destination IO = 1 */
 780 #define DMODE_800_ERL           0x08    /* Enable Read Line */
 781 
 782 /* 35-38 are reserved on 700 and 700-66 series chips */
 783 #define DIEN_REG                0x39    /* DMA interrupt enable rw */
 784 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
 785 #define DIEN_800_MDPE           0x40    /* Master data parity error */
 786 #define DIEN_800_BF             0x20    /* BUS fault */
 787 #define DIEN_ABRT               0x10    /* Enable aborted interrupt */
 788 #define DIEN_SSI                0x08    /* Enable single step interrupt */
 789 #define DIEN_SIR                0x04    /* Enable SCRIPTS INT command 
 790                                          * interrupt
 791                                          */
 792 /* 0x02 is reserved on 800 series chips */
 793 #define DIEN_700_WTD            0x02    /* Enable watchdog timeout interrupt */
 794 #define DIEN_700_OPC            0x01    /* Enable illegal instruction 
 795                                          * interrupt 
 796                                          */
 797 #define DIEN_800_IID            0x01    /*  Same meaning, different name */ 
 798 
 799 /*
 800  * DMA watchdog timer rw
 801  * set in 16 CLK input periods.
 802  */
 803 #define DWT_REG                 0x3a
 804 
 805 /* DMA control rw */
 806 #define DCNTL_REG               0x3b
 807 #define DCNTL_700_CF1           0x80    /* Clock divisor bits */
 808 #define DCNTL_700_CF0           0x40
 809 #define DCNTL_700_CF_MASK       0xc0
 810 /* Clock divisors                          Divisor SCLK range (MHZ) */
 811 #define DCNTL_700_CF_2          0x00    /* 2.0     37.51-50.00 */
 812 #define DCNTL_700_CF_1_5        0x40    /* 1.5     25.01-37.50 */
 813 #define DCNTL_700_CF_1          0x80    /* 1.0     16.67-25.00 */
 814 #define DCNTL_700_CF_3          0xc0    /* 3.0     50.01-66.67 (53c700-66) */
 815 
 816 #define DCNTL_700_S16           0x20    /* Load scripts 16 bits at a time */
 817 #define DCNTL_SSM               0x10    /* Single step mode */
 818 #define DCNTL_700_LLM           0x08    /* Low level mode, can only be set 
 819                                          * after selection */
 820 #define DCNTL_800_IRQM          0x08    /* Totem pole IRQ pin */
 821 #define DCNTL_STD               0x04    /* Start DMA / SCRIPTS */
 822 /* 0x02 is reserved */
 823 #define DCNTL_00_RST            0x01    /* Software reset, resets everything
 824                                          * but 286 mode bit  in DMODE. On the
 825                                          * NCR53c710, this bit moved to CTEST8
 826                                          */
 827 #define DCNTL_10_COM            0x01    /* 700 software compatibility mode */
 828 
 829 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
 830 
 831 
 832 /* NCR53c700-66 only */
 833 #define SCRATCHB_REG_00         0x3c    /* through 0x3f scratch b rw */
 834 #define SCRATCHB_REG_800        0x5c    /* through 0x5f scratch b rw */
 835 /* NCR53c710 only */
 836 #define ADDER_REG_10            0x3c    /* Adder, NCR53c710 only */
 837 
 838 #define SIEN1_REG_800           0x41
 839 #define SIEN1_800_STO           0x04    /* selection/reselection timeout */
 840 #define SIEN1_800_GEN           0x02    /* general purpose timer */
 841 #define SIEN1_800_HTH           0x01    /* handshake to handshake */
 842 
 843 #define SIST1_REG_800           0x43
 844 #define SIST1_800_STO           0x04    /* selection/reselection timeout */
 845 #define SIST1_800_GEN           0x02    /* general purpose timer */
 846 #define SIST1_800_HTH           0x01    /* handshake to handshake */
 847 
 848 #define SLPAR_REG_800           0x44    /* Parity */
 849 
 850 #define MACNTL_REG_800          0x46    /* Memory access control */
 851 #define MACNTL_800_TYP3         0x80
 852 #define MACNTL_800_TYP2         0x40
 853 #define MACNTL_800_TYP1         0x20
 854 #define MACNTL_800_TYP0         0x10
 855 #define MACNTL_800_DWR          0x08
 856 #define MACNTL_800_DRD          0x04
 857 #define MACNTL_800_PSCPT        0x02
 858 #define MACNTL_800_SCPTS        0x01
 859 
 860 #define GPCNTL_REG_800          0x47    /* General Purpose Pin Control */
 861 
 862 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
 863 #define STIME0_REG_800          0x48    /* SCSI Timer Register 0 */
 864 #define STIME0_800_HTH_MASK     0xf0    /* Handshake to Handshake timeout */
 865 #define STIME0_800_HTH_SHIFT    4
 866 #define STIME0_800_SEL_MASK     0x0f    /* Selection timeout */
 867 #define STIME0_800_SEL_SHIFT    0
 868 
 869 #define STIME1_REG_800          0x49
 870 #define STIME1_800_GEN_MASK     0x0f    /* General purpose timer */
 871 
 872 #define RESPID_REG_800          0x4a    /* Response ID, bit fielded */
 873 
 874 #define STEST0_REG_800          0x4c    
 875 #define STEST0_800_SLT          0x08    /* Selection response logic test */
 876 #define STEST0_800_ART          0x04    /* Arbitration priority encoder test */
 877 #define STEST0_800_SOZ          0x02    /* Synchronous offset zero */
 878 #define STEST0_800_SOM          0x01    /* Synchronous offset maximum */
 879 
 880 #define STEST1_REG_800          0x4d
 881 #define STEST1_800_SCLK         0x80    /* Disable SCSI clock */
 882 
 883 #define STEST2_REG_800          0x4e    
 884 #define STEST2_800_SCE          0x80    /* Enable SOCL/SODL */
 885 #define STEST2_800_ROF          0x40    /* Reset SCSI sync offset */
 886 #define STEST2_800_SLB          0x10    /* Enable SCSI loopback mode */
 887 #define STEST2_800_SZM          0x08    /* SCSI high impedance mode */
 888 #define STEST2_800_EXT          0x02    /* Extend REQ/ACK filter 30 to 60ns */
 889 #define STEST2_800_LOW          0x01    /* SCSI low level mode */
 890 
 891 #define STEST3_REG_800          0x4f     
 892 #define STEST3_800_TE           0x80    /* Enable active negation */
 893 #define STEST3_800_STR          0x40    /* SCSI FIFO test read */
 894 #define STEST3_800_HSC          0x20    /* Halt SCSI clock */
 895 #define STEST3_800_DSI          0x10    /* Disable single initiator response */
 896 #define STEST3_800_TTM          0x04    /* Time test mode */
 897 #define STEST3_800_CSF          0x02    /* Clear SCSI FIFO */
 898 #define STEST3_800_STW          0x01    /* SCSI FIFO test write */
 899 
 900 
 901 
 902 
 903 
 904 #define OPTION_PARITY           0x1     /* Enable parity checking */
 905 #define OPTION_TAGGED_QUEUE     0x2     /* Enable SCSI-II tagged queuing */
 906 #define OPTION_700              0x8     /* Always run NCR53c700 scripts */
 907 #define OPTION_INTFLY           0x10    /* Use INTFLY interrupts */
 908 #define OPTION_DEBUG_INTR       0x20    /* Debug interrupts */
 909 #define OPTION_DEBUG_INIT_ONLY  0x40    /* Run initialization code and 
 910                                            simple test code, return
 911                                            DID_NO_CONNECT if any SCSI
 912                                            commands are attempted. */
 913 #define OPTION_DEBUG_READ_ONLY  0x80    /* Return DID_ERROR if any 
 914                                            SCSI write is attempted */
 915 #define OPTION_DEBUG_TRACE      0x100   /* Animated trace mode, print 
 916                                            each address and instruction 
 917                                            executed to debug buffer. */
 918 #define OPTION_DEBUG_SINGLE     0x200   /* stop after executing one 
 919                                            instruction */
 920 #define OPTION_SYNCHRONOUS      0x400   /* Enable sync SCSI.  */
 921 #define OPTION_MEMORY_MAPPED    0x800   /* NCR registers have valid 
 922                                            memory mapping */
 923 #define OPTION_IO_MAPPED        0x1000  /* NCR registers have valid
 924                                            I/O mapping */
 925 #define OPTION_DEBUG_PROBE_ONLY 0x2000  /* Probe only, don't even init */
 926 #define OPTION_DEBUG_TESTS_ONLY 0x4000  /* Probe, init, run selected tests */
 927 
 928 #define OPTION_DEBUG_TEST0      0x08000 /* Run test 0 */
 929 #define OPTION_DEBUG_TEST1      0x10000 /* Run test 1 */
 930 #define OPTION_DEBUG_TEST2      0x20000 /* Run test 2 */
 931 
 932 #define OPTION_DEBUG_DUMP       0x40000 /* Dump commands */
 933 #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
 934 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
 935 #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
 936 #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
 937 #define OPTION_DEBUG_DSA 0x800000
 938 #define OPTION_DEBUG_CORRUPTION 0x1000000       /* Detect script corruption */
 939 
 940 #if !defined(PERM_OPTIONS)
 941 #define PERM_OPTIONS 0
 942 #endif
 943                                 
 944 struct NCR53c7x0_synchronous {
 945     u32 select_indirect;                /* Value used for indirect selection */
 946     u32 script[6];                      /* Size ?? Script used when target is 
 947                                                 reselected */
 948     unsigned renegotiate:1;             /* Force renegotiation on next   
 949                                            select */
 950 };
 951 
 952 #define CMD_FLAG_SDTR           1       /* Initiating synchronous 
 953                                            transfer negotiation */
 954 #define CMD_FLAG_WDTR           2       /* Initiating wide transfer
 955                                            negotiation */
 956 #define CMD_FLAG_DID_SDTR       4       /* did SDTR */
 957 
 958 struct NCR53c7x0_table_indirect {
 959     u32 count;
 960     void *address;
 961 };
 962 
 963 struct NCR53c7x0_cmd {
 964     void *real;                         /* Real, unaligned address */
 965     void (* free)(void *);              /* Command to deallocate; NULL
 966                                            for structures allocated with
 967                                            scsi_register, etc. */
 968     Scsi_Cmnd *cmd;                     /* Associated Scsi_Cmnd 
 969                                            structure, Scsi_Cmnd points
 970                                            at NCR53c7x0_cmd using 
 971                                            host_scribble structure */
 972 
 973     int size;                           /* scsi_malloc'd size of this 
 974                                            structure */
 975 
 976     int flags;
 977 
 978     unsigned char select[11];           /* Select message, includes
 979                                            IDENTIFY
 980                                            (optional) QUEUE TAG
 981                                            (optional) SDTR or WDTR
 982                                          */
 983 
 984 
 985     volatile struct NCR53c7x0_cmd *next, *prev; 
 986                                         /* Linux maintained lists.  Note that
 987                                            hostdata->free is a singly linked
 988                                            list; the rest are doubly linked */
 989                                          
 990 
 991     long dsa_size; /* Size of DSA structure */
 992 
 993     u32 *data_transfer_start;           /* Start of data transfer routines */
 994     u32 *data_transfer_end;             /* Address after end of data transfer o
 995                                            routines */
 996 
 997     u32 residual[8];                    /* Residual data transfer
 998                                            shadow of data_transfer code.
 999 
1000                                            Has instruction with modified
1001                                            DBC field followed by jump to 
1002                                            CALL routine following command.
1003                                          */
1004              
1005     u32 dsa[0];                         /* Variable length (depending
1006                                            on host type, number of scatter /
1007                                            gather buffers, etc).  */
1008 };
1009 
1010 struct NCR53c7x0_break {
1011     u32 *address, old_instruction[2];
1012     struct NCR53c7x0_break *next;
1013     unsigned char old_size;             /* Size of old instruction */
1014 };
1015 
1016 /* Indicates that the NCR is not executing code */
1017 #define STATE_HALTED    0               
1018 /* 
1019  * Indicates that the NCR is executing the wait for select / reselect 
1020  * script.  Only used when running NCR53c700 compatible scripts, only 
1021  * state during which an ABORT is _not_ considered an error condition.
1022  */
1023 #define STATE_WAITING   1               
1024 /* Indicates that the NCR is executing other code. */
1025 #define STATE_RUNNING   2               
1026 /* 
1027  * Indicates that the NCR was being aborted.
1028  */
1029 #define STATE_ABORTING  3
1030 /* 
1031  * Indicates that the NCR was successfully aborted. */
1032 #define STATE_ABORTED 4
1033     
1034 
1035 /* 
1036  * Where knowledge of SCSI SCRIPT(tm) specified values are needed 
1037  * in an interrupt handler, an interrupt handler exists for each 
1038  * different SCSI script so we don't have name space problems.
1039  * 
1040  * Return values of these handlers are as follows : 
1041  */
1042 #define SPECIFIC_INT_NOTHING    0       /* don't even restart */
1043 #define SPECIFIC_INT_RESTART    1       /* restart at the next instruction */
1044 #define SPECIFIC_INT_ABORT      2       /* recoverable error, abort cmd */
1045 #define SPECIFIC_INT_PANIC      3       /* unrecoverable error, panic */
1046 #define SPECIFIC_INT_DONE       4       /* normal command completion */
1047 #define SPECIFIC_INT_BREAK      5       /* break point encountered */
1048 
1049 struct NCR53c7x0_hostdata {
1050     int size;                           /* Size of entire Scsi_Host
1051                                            structure */
1052     struct Scsi_Host *next;             /* next of this type */
1053     int board;                          /* set to board type, useful if 
1054                                            we have host specific things,
1055                                            ie, a general purpose I/O 
1056                                            bit is being used to enable
1057                                            termination, etc. */
1058 
1059     int chip;                           /* set to chip type */
1060         /*
1061          * NCR53c700 = 700
1062          * NCR53c700-66 = 70066
1063          * NCR53c710 = 710
1064          * NCR53c720 = 720 
1065          * NCR53c810 = 810
1066          */
1067 
1068     /*
1069      * PCI bus, device, function, only for NCR53c8x0 chips.
1070      * pci_valid indicates that the PCI configuration information
1071      * is valid, and we can twiddle MAX_LAT, etc. as recommended
1072      * for maximum performance in the NCR documentation.
1073      */
1074     unsigned char pci_bus, pci_device_fn;
1075     unsigned pci_valid:1;
1076 
1077     u32 *dsp;                           /* dsp to restart with after
1078                                            all stacked interrupts are
1079                                            handled. */
1080 
1081     unsigned dsp_changed:1;             /* Has dsp changed within this
1082                                            set of stacked interrupts ? */
1083 
1084     unsigned char dstat;                /* Most recent value of dstat */
1085     unsigned dstat_valid:1;
1086 
1087     unsigned expecting_iid:1;           /* Expect IID interrupt */
1088     unsigned expecting_sto:1;           /* Expect STO interrupt */
1089     
1090     /* 
1091      * The code stays cleaner if we use variables with function
1092      * pointers and offsets that are unique for the different
1093      * scripts rather than having a slew of switch(hostdata->chip) 
1094      * statements.
1095      * 
1096      * It also means that the #defines from the SCSI SCRIPTS(tm)
1097      * don't have to be visible outside of the script-specific
1098      * instructions, preventing name space pollution.
1099      */
1100 
1101     void (* init_fixup)(struct Scsi_Host *host);
1102     void (* init_save_regs)(struct Scsi_Host *host);
1103     void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1104     void (* soft_reset)(struct Scsi_Host *host);
1105     int (* run_tests)(struct Scsi_Host *host);
1106 
1107     /*
1108      * Called when DSTAT_SIR is set, indicating an interrupt generated
1109      * by the INT instruction, where values are unique for each SCSI
1110      * script.  Should return one of the SPEC_* values.
1111      */
1112 
1113     int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1114 
1115     long dsa_size; /* Size of DSA structure */
1116 
1117     /*
1118      * Location of DSA fields for the SCSI SCRIPT corresponding to this 
1119      * chip.  
1120      */
1121 
1122     s32 dsa_start;                      
1123     s32 dsa_end;                        
1124     s32 dsa_next;
1125     s32 dsa_prev;
1126     s32 dsa_cmnd;
1127     s32 dsa_select;
1128     s32 dsa_msgout;
1129     s32 dsa_cmdout;
1130     s32 dsa_dataout;
1131     s32 dsa_datain;
1132     s32 dsa_msgin;
1133     s32 dsa_msgout_other;
1134     s32 dsa_write_sync;
1135     s32 dsa_write_resume;
1136     s32 dsa_jump_resume;
1137     s32 dsa_check_reselect;
1138     s32 dsa_status;
1139 
1140     /* 
1141      * Important entry points that generic fixup code needs
1142      * to know about, fixed up.
1143      */
1144 
1145     s32 E_accept_message;
1146     s32 E_dsa_code_template;
1147     s32 E_dsa_code_template_end;
1148     s32 E_command_complete;             
1149     s32 E_msg_in;
1150     s32 E_initiator_abort;
1151     s32 E_other_transfer;
1152     s32 E_target_abort;
1153     s32 E_schedule;                     
1154     s32 E_debug_break;  
1155     s32 E_reject_message;
1156     s32 E_respond_message;
1157     s32 E_select;
1158     s32 E_select_msgout;
1159     s32 E_test_0;
1160     s32 E_test_1;
1161     s32 E_test_2;
1162     s32 E_test_3;
1163     s32 E_dsa_zero;
1164     s32 E_dsa_jump_resume;
1165 
1166     int options;                        /* Bitfielded set of options enabled */
1167     volatile u32 test_completed;        /* Test completed */
1168     int test_running;                   /* Test currently running */
1169     int test_source;
1170     volatile int test_dest;
1171 
1172     volatile int state;                 /* state of driver, only used for 
1173                                            OPTION_700 */
1174 
1175     unsigned char  dmode;               /* 
1176                                          * set to the address of the DMODE 
1177                                          * register for this chip.
1178                                          */
1179     unsigned char istat;                /* 
1180                                          * set to the address of the ISTAT 
1181                                          * register for this chip.
1182                                          */
1183   
1184     int scsi_clock;                     /* 
1185                                          * SCSI clock in HZ. 0 may be used 
1186                                          * for unknown, although this will
1187                                          * disable synchronous negotiation.
1188                                          */
1189 
1190     volatile int intrs;                 /* Number of interrupts */
1191     unsigned char saved_dmode;  
1192     unsigned char saved_ctest4;
1193     unsigned char saved_ctest7;
1194     unsigned char saved_dcntl;
1195     unsigned char saved_scntl3;
1196 
1197     unsigned char this_id_mask;
1198 
1199     /* Debugger information */
1200     struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1201         *breakpoint_current;            /* Current breakpoint being stepped 
1202                                            through, NULL if we are running 
1203                                            normally. */
1204 #ifdef NCR_DEBUG
1205     int debug_size;                     /* Size of debug buffer */
1206     volatile int debug_count;           /* Current data count */
1207     volatile char *debug_buf;           /* Output ring buffer */
1208     volatile char *debug_write;         /* Current write pointer */
1209     volatile char *debug_read;          /* Current read pointer */
1210 #endif /* def NCR_DEBUG */
1211 
1212     /* XXX - primitive debugging junk, remove when working ? */
1213     int debug_print_limit;              /* Number of commands to print
1214                                            out exhaustive debugging
1215                                            information for if 
1216                                            OPTION_DEBUG_DUMP is set */ 
1217 
1218     unsigned char debug_lun_limit[8];   /* If OPTION_DEBUG_TARGET_LIMIT
1219                                            set, puke if commands are sent
1220                                            to other target/lun combinations */
1221 
1222     int debug_count_limit;              /* Number of commands to execute
1223                                            before puking to limit debugging 
1224                                            output */
1225                                     
1226 
1227     volatile unsigned idle:1;                   /* set to 1 if idle */
1228 
1229     /* 
1230      * Table of synchronous transfer parameters set on a per-target
1231      * basis.
1232      * 
1233      * XXX - do we need to increase this to 16 for the WIDE-SCSI
1234      * flavors of the board?
1235      */
1236     
1237     volatile struct NCR53c7x0_synchronous sync[8];
1238 
1239     volatile struct NCR53c7x0_cmd *issue_queue;
1240                                                 /* waiting to be issued by
1241                                                    Linux driver */
1242     volatile struct NCR53c7x0_cmd *running_list;        
1243                                                 /* commands running, maintained
1244                                                    by Linux driver */
1245     volatile struct NCR53c7x0_cmd *current;     /* currently connected 
1246                                                    nexus, ONLY valid for
1247                                                    NCR53c700/NCR53c700-66
1248                                                  */
1249 
1250     volatile struct NCR53c7x0_cmd *spare;       /* pointer to spare,
1251                                                    allocated at probe time,
1252                                                    which we can use for 
1253                                                    initialization */
1254     volatile struct NCR53c7x0_cmd *free;
1255     int max_cmd_size;                           /* Maximum size of NCR53c7x0_cmd
1256                                                    based on number of 
1257                                                    scatter/gather segments, etc.
1258                                                    */
1259     volatile int num_cmds;                      /* Number of commands 
1260                                                    allocated */
1261     volatile unsigned char cmd_allocated[8];    /* Have we allocated commands
1262                                                    for this target yet?  If not,
1263                                                    do so ASAP */
1264     volatile unsigned char busy[8][8];          /* number of commands 
1265                                                    executing on each target
1266                                                  */
1267     /* 
1268      * Eventually, I'll switch to a coroutine for calling 
1269      * cmd->done(cmd), etc. so that we can overlap interrupt
1270      * processing with this code for maximum performance.
1271      */
1272     
1273     volatile struct NCR53c7x0_cmd *finished_queue;      
1274                                                 
1275 
1276     /* Shared variables between SCRIPT and host driver */
1277     volatile u32 issue_dsa_head;
1278                                                 /* commands waiting to be 
1279                                                    issued, insertions are 
1280                                                    done by Linux driver,
1281                                                    deletions are done by
1282                                                    NCR */
1283     u32 *issue_dsa_tail;                        /* issue queue tail pointer;
1284                                                    used by Linux driver only */
1285     volatile unsigned char msg_buf[16];         /* buffer for messages
1286                                                    other than the command
1287                                                    complete message */
1288     volatile u32 reconnect_dsa_head;
1289                                                 /* disconnected commands,
1290                                                    maintained by NCR */
1291     /* Data identifying nexus we are trying to match during reselection */
1292     volatile unsigned char reselected_identify; /* IDENTIFY message */
1293     volatile unsigned char reselected_tag;      /* second byte of queue tag 
1294                                                    message or 0 */
1295     /* These were static variables before we moved them */
1296 
1297     s32 NCR53c7xx_zero;
1298     s32 NCR53c7xx_sink;
1299     char NCR53c7xx_msg_reject;
1300     char NCR53c7xx_msg_abort;
1301     char NCR53c7xx_msg_nop;
1302 
1303     int script_count;                           /* Size of script in words */
1304     u32 script[0];                              /* Relocated SCSI script */
1305 
1306 };
1307 
1308 #define IRQ_NONE        255
1309 #define DMA_NONE        255
1310 #define IRQ_AUTO        254
1311 #define DMA_AUTO        254
1312 
1313 #define BOARD_GENERIC   0
1314 
1315 #define NCR53c7x0_insn_size(insn)                                       \
1316     (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1317     
1318 
1319 #define NCR53c7x0_local_declare()                                       \
1320     volatile unsigned char *NCR53c7x0_address_memory;                   \
1321     unsigned int NCR53c7x0_address_io;                                  \
1322     int NCR53c7x0_memory_mapped
1323 
1324 #define NCR53c7x0_local_setup(host)                                     \
1325     NCR53c7x0_address_memory = (void *) (host)->base;                   \
1326     NCR53c7x0_address_io = (unsigned int) (host)->io_port;              \
1327     NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *)            \
1328         host->hostdata)-> options & OPTION_MEMORY_MAPPED 
1329 
1330 #define NCR53c7x0_read8(address)                                        \
1331     (NCR53c7x0_memory_mapped ?                                          \
1332         ncr_readb(NCR53c7x0_address_memory + (address))  :              \
1333         inb(NCR53c7x0_address_io + (address)))
1334 
1335 #define NCR53c7x0_read16(address)                                       \
1336     (NCR53c7x0_memory_mapped ?                                          \
1337         ncr_readw(NCR53c7x0_address_memory + (address))  :              \
1338         inw(NCR53c7x0_address_io + (address)))
1339 
1340 #define NCR53c7x0_read32(address)                                       \
1341     (NCR53c7x0_memory_mapped ?                                          \
1342         ncr_readl(NCR53c7x0_address_memory + (address))  :              \
1343         inl(NCR53c7x0_address_io + (address)))
1344 
1345 #define NCR53c7x0_write8(address,value)                                 \
1346     (NCR53c7x0_memory_mapped ?                                          \
1347         ncr_writeb((value), NCR53c7x0_address_memory + (address)) :     \
1348         outb((value), NCR53c7x0_address_io + (address)))
1349 
1350 #define NCR53c7x0_write16(address,value)                                \
1351     (NCR53c7x0_memory_mapped ?                                          \
1352         ncr_writew((value), NCR53c7x0_address_memory + (address)) :     \
1353         outw((value), NCR53c7x0_address_io + (address)))
1354 
1355 #define NCR53c7x0_write32(address,value)                                \
1356     (NCR53c7x0_memory_mapped ?                                          \
1357         ncr_writel((value), NCR53c7x0_address_memory + (address)) :     \
1358         outl((value), NCR53c7x0_address_io + (address)))
1359 
1360 #define patch_abs_32(script, offset, symbol, value)                     \
1361         for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof            \
1362             (u32)); ++i) {                                              \
1363             (script)[A_##symbol##_used[i] - (offset)] += (value);       \
1364             if (hostdata->options & OPTION_DEBUG_FIXUP)                 \
1365               printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1366                 host->host_no, #symbol, i, A_##symbol##_used[i] -       \
1367                 (int)(offset), #script, (script)[A_##symbol##_used[i] - \
1368                 (offset)]);                                             \
1369         }
1370 
1371 #define patch_abs_rwri_data(script, offset, symbol, value)              \
1372         for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof            \
1373             (u32)); ++i)                                                \
1374             (script)[A_##symbol##_used[i] - (offset)] =                 \
1375                 ((script)[A_##symbol##_used[i] - (offset)] &            \
1376                 ~DBC_RWRI_IMMEDIATE_MASK) |                             \
1377                 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) &                \
1378                  DBC_RWRI_IMMEDIATE_MASK)
1379 
1380 #define patch_dsa_32(dsa, symbol, word, value)                          \
1381         {                                                               \
1382         (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(u32)  \
1383                 + (word)] = (value);                                    \
1384         if (hostdata->options & OPTION_DEBUG_DSA)                       \
1385             printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n",    \
1386                 #dsa, #symbol, hostdata->##symbol,                      \
1387                 (word), (u32)(value));                          \
1388         }
1389     
1390 
1391 
1392 #endif /* NCR53c7x0_C */
1393 #endif /* NCR53c7x0_H */

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