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38
39 #ifndef NCR53c7x0_H
40 #define NCR53c7x0_H
41
42 #ifdef __alpha__
43
44 # define ncr_readb(a) ((unsigned int)readb((unsigned long)(a)))
45 # define ncr_readw(a) ((unsigned int)readw((unsigned long)(a)))
46 # define ncr_readl(a) ((unsigned int)readl((unsigned long)(a)))
47 # define ncr_writeb(v,a) (writeb((v), (unsigned long)(a)))
48 # define ncr_writew(v,a) (writew((v), (unsigned long)(a)))
49 # define ncr_writel(v,a) (writel((v), (unsigned long)(a)))
50
51 #else
52
53 # define ncr_readb(a) (*(unsigned char*)(a))
54 # define ncr_readw(a) (*(unsigned short*)(a))
55 # define ncr_readl(a) (*(unsigned int*)(a))
56 # define ncr_writeb(v,a) (*(unsigned char*)(a) = (v))
57 # define ncr_writew(v,a) (*(unsigned short*)(a) = (v))
58 # define ncr_writel(v,a) (*(unsigned int*)(a) = (v))
59
60 #endif
61
62
63
64
65
66
67
68
69 #if defined(HOSTS_C) || defined(MODULE)
70 #include <linux/scsicam.h>
71 extern int NCR53c7xx_abort(Scsi_Cmnd *);
72 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
73 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
74 extern int NCR53c7xx_reset(Scsi_Cmnd *);
75 #ifdef MODULE
76 extern int NCR53c7xx_release(struct Scsi_Host *);
77 #else
78 #define NCR53c7xx_release NULL
79 #endif
80
81 extern int generic_proc_info(char *, char **, off_t, int, int, int);
82
83 #define NCR53c7xx {NULL, NULL, generic_proc_info, "NCR53c7xx", \
84 PROC_SCSI_NCR53C7xx, "NCR53c{7,8}xx (rel 4)", NCR53c7xx_detect, \
85 NULL, NULL, NULL, \
86 NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset, \
87 NULL , scsicam_bios_param, 1, \
88 7, 127 , 1 , \
89 0, 0, DISABLE_CLUSTERING}
90 #endif
91
92 #ifndef HOSTS_C
93
94
95
96
97 #define SCNTL0_REG 0x00
98 #define SCNTL0_ARB1 0x80
99 #define SCNTL0_ARB2 0x40
100 #define SCNTL0_STRT 0x20
101 #define SCNTL0_WATN 0x10
102 #define SCNTL0_EPC 0x08
103
104 #define SCNTL0_EPG_700 0x04
105 #define SCNTL0_AAP 0x02
106 #define SCNTL0_TRG 0x01
107
108
109
110 #define SCNTL1_REG 0x01
111 #define SCNTL1_EXC 0x80
112 #define SCNTL1_ADB 0x40
113 #define SCNTL1_ESR_700 0x20
114
115 #define SCNTL1_DHP_800 0x20
116
117 #define SCNTL1_CON 0x10
118 #define SCNTL1_RST 0x08
119 #define SCNTL1_AESP 0x04
120 #define SCNTL1_SND_700 0x02
121 #define SCNTL1_IARB_800 0x02
122
123
124 #define SCNTL1_RCV_700 0x01
125 #define SCNTL1_SST_800 0x01
126
127
128
129 #define SCNTL2_REG_800 0x02
130 #define SCNTL2_800_SDU 0x80
131
132
133
134 #define SCNTL3_REG_800 0x03
135 #define SCNTL3_800_SCF_SHIFT 4
136 #define SCNTL3_800_SCF_MASK 0x70
137 #define SCNTL3_800_SCF2 0x40
138 #define SCNTL3_800_SCF1 0x20
139 #define SCNTL3_800_SCF0 0x10
140
141
142
143
144 #define SCNTL3_800_CCF_SHIFT 0
145 #define SCNTL3_800_CCF_MASK 0x07
146 #define SCNTL3_800_CCF2 0x04
147 #define SCNTL3_800_CCF1 0x02
148 #define SCNTL3_800_CCF0 0x01
149
150
151
152
153
154
155
156
157 #define SDID_REG_700 0x02
158 #define SDID_REG_800 0x06
159
160 #define GP_REG_800 0x07
161 #define GP_800_IO1 0x02
162 #define GP_800_IO2 0x01
163
164
165
166 #define SIEN_REG_700 0x03
167 #define SIEN0_REG_800 0x40
168 #define SIEN_MA 0x80
169 #define SIEN_FC 0x40
170 #define SIEN_700_STO 0x20
171 #define SIEN_800_SEL 0x20
172 #define SIEN_700_SEL 0x10
173 #define SIEN_800_RESEL 0x10
174 #define SIEN_SGE 0x08
175 #define SIEN_UDC 0x04
176 #define SIEN_RST 0x02
177 #define SIEN_PAR 0x01
178
179
180
181
182
183
184
185
186
187
188 #define SCID_REG 0x04
189
190 #define SCID_800_RRE 0x40
191 #define SCID_800_SRE 0x20
192
193 #define SCID_800_ENC_MASK 0x07
194
195
196 #define SXFER_REG 0x05
197 #define SXFER_DHP 0x80
198
199 #define SXFER_TP2 0x40
200 #define SXFER_TP1 0x20
201 #define SXFER_TP0 0x10
202 #define SXFER_TP_MASK 0x70
203 #define SXFER_TP_SHIFT 4
204 #define SXFER_TP_4 0x00
205 #define SXFER_TP_5 0x10
206 #define SXFER_TP_6 0x20
207 #define SXFER_TP_7 0x30
208 #define SXFER_TP_8 0x40
209 #define SXFER_TP_9 0x50
210 #define SXFER_TP_10 0x60
211 #define SXFER_TP_11 0x70
212
213 #define SXFER_MO3 0x08
214 #define SXFER_MO2 0x04
215 #define SXFER_MO1 0x02
216 #define SXFER_MO0 0x01
217 #define SXFER_MO_MASK 0x0f
218 #define SXFER_MO_SHIFT 0
219
220
221
222
223
224
225
226 #define SODL_REG_700 0x06
227 #define SODL_REG_800 0x54
228
229
230
231
232
233
234
235
236
237
238 #define SBCL_REG 0x0b
239 #define SBCL_REQ 0x80
240 #define SBCL_ACK 0x40
241 #define SBCL_BSY 0x20
242 #define SBCL_SEL 0x10
243 #define SBCL_ATN 0x08
244 #define SBCL_MSG 0x04
245 #define SBCL_CD 0x02
246 #define SBCL_IO 0x01
247 #define SBCL_PHASE_CMDOUT SBCL_CD
248 #define SBCL_PHASE_DATAIN SBCL_IO
249 #define SBCL_PHASE_DATAOUT 0
250 #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
251 #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
252 #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
253 #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271 #define SFBR_REG 0x08
272
273
274
275
276
277
278
279 #define SIDL_REG_700 0x09
280 #define SIDL_REG_800 0x50
281
282
283
284
285
286
287
288 #define SBDL_REG_700 0x0a
289 #define SBDL_REG_800 0x58
290
291 #define SSID_REG_800 0x0a
292 #define SSID_800_VAL 0x80
293 #define SSID_800_ENCID_MASK 0x07
294
295
296
297
298
299
300 #define SOCL_REG 0x0b
301 #define SOCL_REQ 0x80
302 #define SOCL_ACK 0x40
303 #define SOCL_BSY 0x20
304 #define SOCL_SEL 0x10
305 #define SOCL_ATN 0x08
306 #define SOCL_MSG 0x04
307 #define SOCL_CD 0x02
308 #define SOCL_IO 0x01
309
310
311
312
313
314
315
316 #define SBCL_SSCF1 0x02
317 #define SBCL_SSCF0 0x01
318 #define SBCL_SSCF_MASK 0x03
319
320
321
322
323
324
325 #define DSTAT_REG 0x0c
326 #define DSTAT_DFE 0x80
327 #define DSTAT_800_MDPE 0x40
328 #define DSTAT_800_BF 0x20
329 #define DSTAT_ABRT 0x10
330 #define DSTAT_SSI 0x08
331 #define DSTAT_SIR 0x04
332
333
334 #define DSTAT_WTD 0x02
335 #define DSTAT_OPC 0x01
336 #define DSTAT_800_IID 0x01
337
338
339 #define SSTAT0_REG 0x0d
340 #define SIST0_REG_800 0x42
341 #define SSTAT0_MA 0x80
342
343
344 #define SSTAT0_CMP 0x40
345 #define SSTAT0_700_STO 0x20
346 #define SIST0_800_SEL 0x20
347 #define SSTAT0_700_SEL 0x10
348 #define SIST0_800_RSL 0x10
349 #define SSTAT0_SGE 0x08
350 #define SSTAT0_UDC 0x04
351 #define SSTAT0_RST 0x02
352 #define SSTAT0_PAR 0x01
353
354 #define SSTAT1_REG 0x0e
355 #define SSTAT1_ILF 0x80
356 #define SSTAT1_ORF 0x40
357 #define SSTAT1_OLF 0x20
358 #define SSTAT1_AIP 0x10
359 #define SSTAT1_LOA 0x08
360 #define SSTAT1_WOA 0x04
361 #define SSTAT1_RST 0x02
362 #define SSTAT1_SDP 0x01
363
364 #define SSTAT2_REG 0x0f
365 #define SSTAT2_FF3 0x80
366 #define SSTAT2_FF2 0x40
367 #define SSTAT2_FF1 0x20
368 #define SSTAT2_FF0 0x10
369 #define SSTAT2_FF_MASK 0xf0
370
371
372
373
374
375 #define SSTAT2_SDP 0x08
376 #define SSTAT2_MSG 0x04
377 #define SSTAT2_CD 0x02
378 #define SSTAT2_IO 0x01
379
380
381
382 #define SCRATCHA_REG_00 0x10
383
384 #define DSA_REG 0x10
385
386 #define CTEST0_REG_700 0x14
387 #define CTEST0_REG_800 0x18
388
389 #define CTEST0_700_RTRG 0x02
390 #define CTEST0_700_DDIR 0x01
391
392
393
394
395 #define CTEST1_REG_700 0x15
396 #define CTEST1_REG_800 0x19
397 #define CTEST1_FMT3 0x80
398 #define CTEST1_FMT2 0x40
399 #define CTEST1_FMT1 0x20
400 #define CTEST1_FMT0 0x10
401
402 #define CTEST1_FFL3 0x08
403 #define CTEST1_FFL2 0x04
404 #define CTEST1_FFL1 0x02
405 #define CTEST1_FFL0 0x01
406
407 #define CTEST2_REG_700 0x16
408 #define CTEST2_REG_800 0x1a
409
410 #define CTEST2_800_DDIR 0x80
411 #define CTEST2_800_SIGP 0x40
412
413 #define CTEST2_800_CIO 0x20 .
414 #define CTEST2_800_CM 0x10
415
416
417 #define CTEST2_700_SOFF 0x20
418
419
420
421
422
423
424
425 #define CTEST2_700_SFP 0x10
426
427
428
429 #define CTEST2_700_DFP 0x08
430
431
432
433 #define CTEST2_TEOP 0x04
434
435
436
437 #define CTEST2_DREQ 0x02
438
439 #define CTEST2_800_DACK 0x01
440
441
442
443
444
445
446
447
448 #define CTEST3_REG_700 0x17
449
450 #define CTEST3_REG_800 0x1b
451 #define CTEST3_800_V3 0x80
452 #define CTEST3_800_V2 0x40
453 #define CTEST3_800_V1 0x20
454 #define CTEST3_800_V0 0x10
455 #define CTEST3_800_FLF 0x08
456 #define CTEST3_800_CLF 0x04
457 #define CTEST3_800_FM 0x02
458
459
460 #define CTEST4_REG_700 0x18
461 #define CTEST4_REG_800 0x21
462
463 #define CTEST4_800_BDIS 0x80
464 #define CTEST4_ZMOD 0x40
465 #define CTEST4_SZM 0x20
466 #define CTEST4_700_SLBE 0x10
467 #define CTEST4_800_SRTM 0x10
468 #define CTEST4_700_SFWR 0x08
469
470
471
472 #define CTEST4_800_MPEE 0x08
473
474
475
476
477
478
479
480
481 #define CTEST4_FBL2 0x04
482 #define CTEST4_FBL1 0x02
483 #define CTEST4_FBL0 0x01
484 #define CTEST4_FBL_MASK 0x07
485 #define CTEST4_FBL_0 0x04
486 #define CTEST4_FBL_1 0x05
487 #define CTEST4_FBL_2 0x06
488 #define CTEST4_FBL_3 0x07
489 #define CTEST4_800_SAVE (CTEST4_800_BDIS)
490
491
492 #define CTEST5_REG_700 0x19
493 #define CTEST5_REG_800 0x22
494
495
496
497
498
499 #define CTEST5_ADCK 0x80
500
501
502
503
504 #define CTEST5_BBCK 0x40
505
506
507
508
509
510
511
512
513
514 #define CTEST5_700_ROFF 0x20
515
516
517
518
519
520 #define CTEST5_MASR 0x10
521 #define CTEST5_DDIR 0x08
522
523
524
525 #define CTEST5_700_EOP 0x04
526 #define CTEST5_700_DREQ 0x02
527 #define CTEST5_700_DACK 0x01
528
529
530
531
532
533
534 #define CTEST6_REG_700 0x1a
535 #define CTEST6_REG_800 0x23
536
537 #define CTEST7_REG 0x1b
538
539 #define CTEST7_10_CDIS 0x80
540 #define CTEST7_10_SC1 0x40
541 #define CTEST7_10_SC0 0x20
542 #define CTEST7_10_SC_MASK 0x60
543
544 #define CTEST7_0060_FM 0x20
545 #define CTEST7_STD 0x10
546 #define CTEST7_DFP 0x08
547 #define CTEST7_EVP 0x04
548 #define CTEST7_10_TT1 0x02
549 #define CTEST7_00_DC 0x02
550
551 #define CTEST7_DIFF 0x01
552
553 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
554
555
556 #define TEMP_REG 0x1c
557
558 #define DFIFO_REG 0x20
559
560
561
562
563 #define DFIFO_00_FLF 0x80
564 #define DFIFO_00_CLF 0x40
565 #define DFIFO_BO6 0x40
566 #define DFIFO_BO5 0x20
567 #define DFIFO_BO4 0x10
568 #define DFIFO_BO3 0x08
569 #define DFIFO_BO2 0x04
570 #define DFIFO_BO1 0x02
571 #define DFIFO_BO0 0x01
572 #define DFIFO_10_BO_MASK 0x7f
573 #define DFIFO_00_BO_MASK 0x3f
574
575
576
577
578
579
580 #define ISTAT_REG_700 0x21
581 #define ISTAT_REG_800 0x14
582 #define ISTAT_ABRT 0x80
583
584
585 #define ISTAT_10_SRST 0x40
586 #define ISTAT_10_SIGP 0x20
587
588 #define ISTAT_800_SEM 0x10
589 #define ISTAT_CON 0x08
590 #define ISTAT_800_INTF 0x04
591 #define ISTAT_700_PRE 0x04
592
593
594
595
596 #define ISTAT_SIP 0x02
597
598
599
600 #define ISTAT_DIP 0x01
601
602
603
604
605 #define CTEST8_REG 0x22
606 #define CTEST8_0066_EAS 0x80
607
608
609 #define CTEST8_0066_EFM 0x40
610 #define CTEST8_0066_GRP 0x20
611
612
613
614
615 #define CTEST8_0066_TE 0x10
616
617
618
619
620 #define CTEST8_0066_HSC 0x08
621 #define CTEST8_0066_SRA 0x04
622
623
624
625 #define CTEST8_0066_DAS 0x02
626
627
628 #define CTEST8_0066_LDE 0x01
629
630
631
632
633
634
635
636
637
638 #define CTEST8_10_V3 0x80
639 #define CTEST8_10_V2 0x40
640 #define CTEST8_10_V1 0x20
641 #define CTEST8_10_V0 0x10
642 #define CTEST8_10_V_MASK 0xf0
643 #define CTEST8_10_FLF 0x08
644 #define CTEST8_10_CLF 0x04
645 #define CTEST8_10_FM 0x02
646 #define CTEST8_10_SM 0x01
647
648
649
650
651
652
653
654
655
656
657
658
659 #define CTEST9_REG_00 0x23
660 #define LCRC_REG_10 0x23
661
662
663
664
665
666
667
668
669
670
671 #define DBC_REG 0x24
672
673
674
675
676
677
678 #define DBC_TCI_TRUE (1 << 19)
679 #define DBC_TCI_COMPARE_DATA (1 << 18)
680 #define DBC_TCI_COMPARE_PHASE (1 << 17)
681 #define DBC_TCI_WAIT_FOR_VALID (1 << 16)
682
683 #define DBC_TCI_MASK_MASK 0xff00
684 #define DBC_TCI_MASK_SHIFT 8
685 #define DBC_TCI_DATA_MASK 0xff
686 #define DBC_TCI_DATA_SHIFT 0
687
688 #define DBC_RWRI_IMMEDIATE_MASK 0xff00
689 #define DBC_RWRI_IMMEDIATE_SHIFT 8
690 #define DBC_RWRI_ADDRESS_MASK 0x3f0000
691 #define DBC_RWRI_ADDRESS_SHIFT 16
692
693
694
695
696
697 #define DCMD_REG 0x27
698 #define DCMD_TYPE_MASK 0xc0
699 #define DCMD_TYPE_BMI 0x00
700 #define DCMD_BMI_IO 0x01
701 #define DCMD_BMI_CD 0x02
702 #define DCMD_BMI_MSG 0x04
703
704 #define DCMD_BMI_OP_MASK 0x18
705 #define DCMD_BMI_OP_MOVE_T 0x00
706 #define DCMD_BMI_OP_MOVE_I 0x08
707
708 #define DCMD_BMI_INDIRECT 0x20
709
710 #define DCMD_TYPE_TCI 0x80
711
712 #define DCMD_TCI_IO 0x01
713 #define DCMD_TCI_CD 0x02
714 #define DCMD_TCI_MSG 0x04
715 #define DCMD_TCI_OP_MASK 0x38
716 #define DCMD_TCI_OP_JUMP 0x00
717 #define DCMD_TCI_OP_CALL 0x08
718 #define DCMD_TCI_OP_RETURN 0x10
719 #define DCMD_TCI_OP_INT 0x18
720
721 #define DCMD_TYPE_RWRI 0x40
722
723 #define DCMD_RWRI_OPC_MASK 0x38
724 #define DCMD_RWRI_OPC_WRITE 0x28
725 #define DCMD_RWRI_OPC_READ 0x30
726 #define DCMD_RWRI_OPC_MODIFY 0x38
727
728 #define DCMD_RWRI_OP_MASK 0x07
729 #define DCMD_RWRI_OP_MOVE 0x00
730 #define DCMD_RWRI_OP_SHL 0x01
731 #define DCMD_RWRI_OP_OR 0x02
732 #define DCMD_RWRI_OP_XOR 0x03
733 #define DCMD_RWRI_OP_AND 0x04
734 #define DCMD_RWRI_OP_SHR 0x05
735 #define DCMD_RWRI_OP_ADD 0x06
736 #define DCMD_RWRI_OP_ADDC 0x07
737
738 #define DCMD_TYPE_MMI 0xc0
739
740
741
742 #define DNAD_REG 0x28
743
744 #define DSP_REG 0x2c
745 #define DSPS_REG 0x30
746
747 #define DMODE_REG_00 0x34
748 #define DMODE_00_BL1 0x80
749 #define DMODE_00_BL0 0x40
750 #define DMODE_BL_MASK 0xc0
751
752 #define DMODE_BL_2 0x00
753 #define DMODE_BL_4 0x40
754 #define DMODE_BL_8 0x80
755 #define DMODE_BL_16 0xc0
756
757 #define DMODE_700_BW16 0x20
758 #define DMODE_700_286 0x10
759 #define DMODE_700_IOM 0x08
760 #define DMODE_700_FAM 0x04
761 #define DMODE_700_PIPE 0x02
762
763
764 #define DMODE_MAN 0x01
765
766
767
768
769
770 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
771
772
773 #define SCRATCHA_REG_800 0x34
774
775 #define SCRATCB_REG_10 0x34
776
777 #define DMODE_REG_10 0x38
778 #define DMODE_800_SIOM 0x20
779 #define DMODE_800_DIOM 0x10
780 #define DMODE_800_ERL 0x08
781
782
783 #define DIEN_REG 0x39
784
785 #define DIEN_800_MDPE 0x40
786 #define DIEN_800_BF 0x20
787 #define DIEN_ABRT 0x10
788 #define DIEN_SSI 0x08
789 #define DIEN_SIR 0x04
790
791
792
793 #define DIEN_700_WTD 0x02
794 #define DIEN_700_OPC 0x01
795
796
797 #define DIEN_800_IID 0x01
798
799
800
801
802
803 #define DWT_REG 0x3a
804
805
806 #define DCNTL_REG 0x3b
807 #define DCNTL_700_CF1 0x80
808 #define DCNTL_700_CF0 0x40
809 #define DCNTL_700_CF_MASK 0xc0
810
811 #define DCNTL_700_CF_2 0x00
812 #define DCNTL_700_CF_1_5 0x40
813 #define DCNTL_700_CF_1 0x80
814 #define DCNTL_700_CF_3 0xc0
815
816 #define DCNTL_700_S16 0x20
817 #define DCNTL_SSM 0x10
818 #define DCNTL_700_LLM 0x08
819
820 #define DCNTL_800_IRQM 0x08
821 #define DCNTL_STD 0x04
822
823 #define DCNTL_00_RST 0x01
824
825
826
827 #define DCNTL_10_COM 0x01
828
829 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
830
831
832
833 #define SCRATCHB_REG_00 0x3c
834 #define SCRATCHB_REG_800 0x5c
835
836 #define ADDER_REG_10 0x3c
837
838 #define SIEN1_REG_800 0x41
839 #define SIEN1_800_STO 0x04
840 #define SIEN1_800_GEN 0x02
841 #define SIEN1_800_HTH 0x01
842
843 #define SIST1_REG_800 0x43
844 #define SIST1_800_STO 0x04
845 #define SIST1_800_GEN 0x02
846 #define SIST1_800_HTH 0x01
847
848 #define SLPAR_REG_800 0x44
849
850 #define MACNTL_REG_800 0x46
851 #define MACNTL_800_TYP3 0x80
852 #define MACNTL_800_TYP2 0x40
853 #define MACNTL_800_TYP1 0x20
854 #define MACNTL_800_TYP0 0x10
855 #define MACNTL_800_DWR 0x08
856 #define MACNTL_800_DRD 0x04
857 #define MACNTL_800_PSCPT 0x02
858 #define MACNTL_800_SCPTS 0x01
859
860 #define GPCNTL_REG_800 0x47
861
862
863 #define STIME0_REG_800 0x48
864 #define STIME0_800_HTH_MASK 0xf0
865 #define STIME0_800_HTH_SHIFT 4
866 #define STIME0_800_SEL_MASK 0x0f
867 #define STIME0_800_SEL_SHIFT 0
868
869 #define STIME1_REG_800 0x49
870 #define STIME1_800_GEN_MASK 0x0f
871
872 #define RESPID_REG_800 0x4a
873
874 #define STEST0_REG_800 0x4c
875 #define STEST0_800_SLT 0x08
876 #define STEST0_800_ART 0x04
877 #define STEST0_800_SOZ 0x02
878 #define STEST0_800_SOM 0x01
879
880 #define STEST1_REG_800 0x4d
881 #define STEST1_800_SCLK 0x80
882
883 #define STEST2_REG_800 0x4e
884 #define STEST2_800_SCE 0x80
885 #define STEST2_800_ROF 0x40
886 #define STEST2_800_SLB 0x10
887 #define STEST2_800_SZM 0x08
888 #define STEST2_800_EXT 0x02
889 #define STEST2_800_LOW 0x01
890
891 #define STEST3_REG_800 0x4f
892 #define STEST3_800_TE 0x80
893 #define STEST3_800_STR 0x40
894 #define STEST3_800_HSC 0x20
895 #define STEST3_800_DSI 0x10
896 #define STEST3_800_TTM 0x04
897 #define STEST3_800_CSF 0x02
898 #define STEST3_800_STW 0x01
899
900
901
902
903
904 #define OPTION_PARITY 0x1
905 #define OPTION_TAGGED_QUEUE 0x2
906 #define OPTION_700 0x8
907 #define OPTION_INTFLY 0x10
908 #define OPTION_DEBUG_INTR 0x20
909 #define OPTION_DEBUG_INIT_ONLY 0x40
910
911
912
913 #define OPTION_DEBUG_READ_ONLY 0x80
914
915 #define OPTION_DEBUG_TRACE 0x100
916
917
918 #define OPTION_DEBUG_SINGLE 0x200
919
920 #define OPTION_SYNCHRONOUS 0x400
921 #define OPTION_MEMORY_MAPPED 0x800
922
923 #define OPTION_IO_MAPPED 0x1000
924
925 #define OPTION_DEBUG_PROBE_ONLY 0x2000
926 #define OPTION_DEBUG_TESTS_ONLY 0x4000
927
928 #define OPTION_DEBUG_TEST0 0x08000
929 #define OPTION_DEBUG_TEST1 0x10000
930 #define OPTION_DEBUG_TEST2 0x20000
931
932 #define OPTION_DEBUG_DUMP 0x40000
933 #define OPTION_DEBUG_TARGET_LIMIT 0x80000
934 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000
935 #define OPTION_DEBUG_SCRIPT 0x200000
936 #define OPTION_DEBUG_FIXUP 0x400000
937 #define OPTION_DEBUG_DSA 0x800000
938 #define OPTION_DEBUG_CORRUPTION 0x1000000
939
940 #if !defined(PERM_OPTIONS)
941 #define PERM_OPTIONS 0
942 #endif
943
944 struct NCR53c7x0_synchronous {
945 u32 select_indirect;
946 u32 script[6];
947
948 unsigned renegotiate:1;
949
950 };
951
952 #define CMD_FLAG_SDTR 1
953
954 #define CMD_FLAG_WDTR 2
955
956 #define CMD_FLAG_DID_SDTR 4
957
958 struct NCR53c7x0_table_indirect {
959 u32 count;
960 void *address;
961 };
962
963 struct NCR53c7x0_cmd {
964 void *real;
965 void (* free)(void *);
966
967
968 Scsi_Cmnd *cmd;
969
970
971
972
973 int size;
974
975
976 int flags;
977
978 unsigned char select[11];
979
980
981
982
983
984
985 volatile struct NCR53c7x0_cmd *next, *prev;
986
987
988
989
990
991 long dsa_size;
992
993 u32 *data_transfer_start;
994 u32 *data_transfer_end;
995
996
997 u32 residual[8];
998
999
1000
1001
1002
1003
1004
1005 u32 dsa[0];
1006
1007
1008 };
1009
1010 struct NCR53c7x0_break {
1011 u32 *address, old_instruction[2];
1012 struct NCR53c7x0_break *next;
1013 unsigned char old_size;
1014 };
1015
1016
1017 #define STATE_HALTED 0
1018
1019
1020
1021
1022
1023 #define STATE_WAITING 1
1024
1025 #define STATE_RUNNING 2
1026
1027
1028
1029 #define STATE_ABORTING 3
1030
1031
1032 #define STATE_ABORTED 4
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042 #define SPECIFIC_INT_NOTHING 0
1043 #define SPECIFIC_INT_RESTART 1
1044 #define SPECIFIC_INT_ABORT 2
1045 #define SPECIFIC_INT_PANIC 3
1046 #define SPECIFIC_INT_DONE 4
1047 #define SPECIFIC_INT_BREAK 5
1048
1049 struct NCR53c7x0_hostdata {
1050 int size;
1051
1052 struct Scsi_Host *next;
1053 int board;
1054
1055
1056
1057
1058
1059 int chip;
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074 unsigned char pci_bus, pci_device_fn;
1075 unsigned pci_valid:1;
1076
1077 u32 *dsp;
1078
1079
1080
1081 unsigned dsp_changed:1;
1082
1083
1084 unsigned char dstat;
1085 unsigned dstat_valid:1;
1086
1087 unsigned expecting_iid:1;
1088 unsigned expecting_sto:1;
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101 void (* init_fixup)(struct Scsi_Host *host);
1102 void (* init_save_regs)(struct Scsi_Host *host);
1103 void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1104 void (* soft_reset)(struct Scsi_Host *host);
1105 int (* run_tests)(struct Scsi_Host *host);
1106
1107
1108
1109
1110
1111
1112
1113 int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1114
1115 long dsa_size;
1116
1117
1118
1119
1120
1121
1122 s32 dsa_start;
1123 s32 dsa_end;
1124 s32 dsa_next;
1125 s32 dsa_prev;
1126 s32 dsa_cmnd;
1127 s32 dsa_select;
1128 s32 dsa_msgout;
1129 s32 dsa_cmdout;
1130 s32 dsa_dataout;
1131 s32 dsa_datain;
1132 s32 dsa_msgin;
1133 s32 dsa_msgout_other;
1134 s32 dsa_write_sync;
1135 s32 dsa_write_resume;
1136 s32 dsa_jump_resume;
1137 s32 dsa_check_reselect;
1138 s32 dsa_status;
1139
1140
1141
1142
1143
1144
1145 s32 E_accept_message;
1146 s32 E_dsa_code_template;
1147 s32 E_dsa_code_template_end;
1148 s32 E_command_complete;
1149 s32 E_msg_in;
1150 s32 E_initiator_abort;
1151 s32 E_other_transfer;
1152 s32 E_target_abort;
1153 s32 E_schedule;
1154 s32 E_debug_break;
1155 s32 E_reject_message;
1156 s32 E_respond_message;
1157 s32 E_select;
1158 s32 E_select_msgout;
1159 s32 E_test_0;
1160 s32 E_test_1;
1161 s32 E_test_2;
1162 s32 E_test_3;
1163 s32 E_dsa_zero;
1164 s32 E_dsa_jump_resume;
1165
1166 int options;
1167 volatile u32 test_completed;
1168 int test_running;
1169 int test_source;
1170 volatile int test_dest;
1171
1172 volatile int state;
1173
1174
1175 unsigned char dmode;
1176
1177
1178
1179 unsigned char istat;
1180
1181
1182
1183
1184 int scsi_clock;
1185
1186
1187
1188
1189
1190 volatile int intrs;
1191 unsigned char saved_dmode;
1192 unsigned char saved_ctest4;
1193 unsigned char saved_ctest7;
1194 unsigned char saved_dcntl;
1195 unsigned char saved_scntl3;
1196
1197 unsigned char this_id_mask;
1198
1199
1200 struct NCR53c7x0_break *breakpoints,
1201 *breakpoint_current;
1202
1203
1204 #ifdef NCR_DEBUG
1205 int debug_size;
1206 volatile int debug_count;
1207 volatile char *debug_buf;
1208 volatile char *debug_write;
1209 volatile char *debug_read;
1210 #endif
1211
1212
1213 int debug_print_limit;
1214
1215
1216
1217
1218 unsigned char debug_lun_limit[8];
1219
1220
1221
1222 int debug_count_limit;
1223
1224
1225
1226
1227 volatile unsigned idle:1;
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237 volatile struct NCR53c7x0_synchronous sync[8];
1238
1239 volatile struct NCR53c7x0_cmd *issue_queue;
1240
1241
1242 volatile struct NCR53c7x0_cmd *running_list;
1243
1244
1245 volatile struct NCR53c7x0_cmd *current;
1246
1247
1248
1249
1250 volatile struct NCR53c7x0_cmd *spare;
1251
1252
1253
1254 volatile struct NCR53c7x0_cmd *free;
1255 int max_cmd_size;
1256
1257
1258
1259 volatile int num_cmds;
1260
1261 volatile unsigned char cmd_allocated[8];
1262
1263
1264 volatile unsigned char busy[8][8];
1265
1266
1267
1268
1269
1270
1271
1272
1273 volatile struct NCR53c7x0_cmd *finished_queue;
1274
1275
1276
1277 volatile u32 issue_dsa_head;
1278
1279
1280
1281
1282
1283 u32 *issue_dsa_tail;
1284
1285 volatile unsigned char msg_buf[16];
1286
1287
1288 volatile u32 reconnect_dsa_head;
1289
1290
1291
1292 volatile unsigned char reselected_identify;
1293 volatile unsigned char reselected_tag;
1294
1295
1296
1297 s32 NCR53c7xx_zero;
1298 s32 NCR53c7xx_sink;
1299 char NCR53c7xx_msg_reject;
1300 char NCR53c7xx_msg_abort;
1301 char NCR53c7xx_msg_nop;
1302
1303 int script_count;
1304 u32 script[0];
1305
1306 };
1307
1308 #define IRQ_NONE 255
1309 #define DMA_NONE 255
1310 #define IRQ_AUTO 254
1311 #define DMA_AUTO 254
1312
1313 #define BOARD_GENERIC 0
1314
1315 #define NCR53c7x0_insn_size(insn) \
1316 (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1317
1318
1319 #define NCR53c7x0_local_declare() \
1320 volatile unsigned char *NCR53c7x0_address_memory; \
1321 unsigned int NCR53c7x0_address_io; \
1322 int NCR53c7x0_memory_mapped
1323
1324 #define NCR53c7x0_local_setup(host) \
1325 NCR53c7x0_address_memory = (void *) (host)->base; \
1326 NCR53c7x0_address_io = (unsigned int) (host)->io_port; \
1327 NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
1328 host->hostdata)-> options & OPTION_MEMORY_MAPPED
1329
1330 #define NCR53c7x0_read8(address) \
1331 (NCR53c7x0_memory_mapped ? \
1332 ncr_readb(NCR53c7x0_address_memory + (address)) : \
1333 inb(NCR53c7x0_address_io + (address)))
1334
1335 #define NCR53c7x0_read16(address) \
1336 (NCR53c7x0_memory_mapped ? \
1337 ncr_readw(NCR53c7x0_address_memory + (address)) : \
1338 inw(NCR53c7x0_address_io + (address)))
1339
1340 #define NCR53c7x0_read32(address) \
1341 (NCR53c7x0_memory_mapped ? \
1342 ncr_readl(NCR53c7x0_address_memory + (address)) : \
1343 inl(NCR53c7x0_address_io + (address)))
1344
1345 #define NCR53c7x0_write8(address,value) \
1346 (NCR53c7x0_memory_mapped ? \
1347 ncr_writeb((value), NCR53c7x0_address_memory + (address)) : \
1348 outb((value), NCR53c7x0_address_io + (address)))
1349
1350 #define NCR53c7x0_write16(address,value) \
1351 (NCR53c7x0_memory_mapped ? \
1352 ncr_writew((value), NCR53c7x0_address_memory + (address)) : \
1353 outw((value), NCR53c7x0_address_io + (address)))
1354
1355 #define NCR53c7x0_write32(address,value) \
1356 (NCR53c7x0_memory_mapped ? \
1357 ncr_writel((value), NCR53c7x0_address_memory + (address)) : \
1358 outl((value), NCR53c7x0_address_io + (address)))
1359
1360 #define patch_abs_32(script, offset, symbol, value) \
1361 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1362 (u32)); ++i) { \
1363 (script)[A_##symbol##_used[i] - (offset)] += (value); \
1364 if (hostdata->options & OPTION_DEBUG_FIXUP) \
1365 printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1366 host->host_no, #symbol, i, A_##symbol##_used[i] - \
1367 (int)(offset), #script, (script)[A_##symbol##_used[i] - \
1368 (offset)]); \
1369 }
1370
1371 #define patch_abs_rwri_data(script, offset, symbol, value) \
1372 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1373 (u32)); ++i) \
1374 (script)[A_##symbol##_used[i] - (offset)] = \
1375 ((script)[A_##symbol##_used[i] - (offset)] & \
1376 ~DBC_RWRI_IMMEDIATE_MASK) | \
1377 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
1378 DBC_RWRI_IMMEDIATE_MASK)
1379
1380 #define patch_dsa_32(dsa, symbol, word, value) \
1381 { \
1382 (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(u32) \
1383 + (word)] = (value); \
1384 if (hostdata->options & OPTION_DEBUG_DSA) \
1385 printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n", \
1386 #dsa, #symbol, hostdata->##symbol, \
1387 (word), (u32)(value)); \
1388 }
1389
1390
1391
1392 #endif
1393 #endif