This source file includes following definitions.
- pci_lookup_dev
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/ptrace.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/bios32.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16
17 #include <asm/page.h>
18
19 struct pci_bus pci_root;
20 struct pci_dev *pci_devices = 0;
21
22
23
24
25
26
27
28
29
30
31
32 #define DEVICE(vid,did,name) \
33 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
34
35 #define BRIDGE(vid,did,name,bridge) \
36 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
37
38
39
40
41
42
43 struct pci_dev_info dev_info[] = {
44 DEVICE( COMPAQ, COMPAQ_1280, "QVision 1280/p"),
45 DEVICE( NCR, NCR_53C810, "53c810"),
46 DEVICE( NCR, NCR_53C820, "53c820"),
47 DEVICE( NCR, NCR_53C825, "53c825"),
48 DEVICE( NCR, NCR_53C815, "53c815"),
49 DEVICE( ATI, ATI_68800, "68800AX"),
50 DEVICE( ATI, ATI_215CT222, "215CT222"),
51 DEVICE( ATI, ATI_210888CX, "210888CX"),
52 DEVICE( ATI, ATI_210888GX, "210888GX"),
53 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
54 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
55 DEVICE( ADL, ADL_2301, "2301"),
56 DEVICE( NS, NS_87410, "87410"),
57 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
58 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
59 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
60 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
61 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
62 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
63 BRIDGE( DEC, DEC_BRD, "DC21050", 0x00),
64 DEVICE( DEC, DEC_TULIP, "DC21040"),
65 DEVICE( DEC, DEC_TGA, "DC21030"),
66 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
67 DEVICE( DEC, DEC_FDDI, "DEFPA"),
68 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
69 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
70 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
71 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
72 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
73 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
74 DEVICE( CIRRUS, CIRRUS_7543, "CL 7543"),
75 DEVICE( AMD, AMD_LANCE, "79C970"),
76 DEVICE( AMD, AMD_SCSI, "53C974"),
77 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
78 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
79 DEVICE( TRIDENT, TRIDENT_9660, "TG 9660"),
80 DEVICE( AI, AI_M1435, "M1435"),
81 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
82 DEVICE( MATROX, MATROX_MIL ,"Millenium"),
83 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
84 DEVICE( CT, CT_65545, "65545"),
85 DEVICE( FD, FD_36C70, "TMC-18C30"),
86 DEVICE( SI, SI_503, "85C503"),
87 DEVICE( SI, SI_501, "85C501"),
88 DEVICE( SI, SI_496, "85C496"),
89 DEVICE( SI, SI_601, "85C601"),
90 DEVICE( SI, SI_5511, "85C5511"),
91 DEVICE( SI, SI_5513, "85C5513"),
92 DEVICE( HP, HP_J2585A, "J2585A"),
93 DEVICE( PCTECH, PCTECH_RZ1000, "RZ1000 (buggy)"),
94 DEVICE( DPT, DPT, "SmartCache/Raid"),
95 DEVICE( OPTI, OPTI_82C557, "82C557"),
96 DEVICE( OPTI, OPTI_82C558, "82C558"),
97 DEVICE( OPTI, OPTI_82C621, "82C621"),
98 DEVICE( OPTI, OPTI_82C822, "82C822"),
99 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"BT-946C"),
100 DEVICE( BUSLOGIC, BUSLOGIC_946C, "BT-946C"),
101 DEVICE( BUSLOGIC, BUSLOGIC_930, "BT-930"),
102 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
103 DEVICE( N9, N9_I128, "Imagine 128"),
104 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
105 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
106 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
107 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
108 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
109 DEVICE( UMC, UMC_UM9017F, "UM9017F"),
110 DEVICE( X, X_AGX016, "ITT AGX016"),
111 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
112 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
113 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
114 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
115 DEVICE( CMD, CMD_640, "640 (buggy)"),
116 DEVICE( CMD, CMD_646, "646"),
117 DEVICE( VISION, VISION_QD8500, "QD-8500"),
118 DEVICE( VISION, VISION_QD8580, "QD-8580"),
119 DEVICE( SIERRA, SIERRA_STB, "STB Horizon 64"),
120 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
121 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
122 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
123 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
124 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
125 DEVICE( AL, AL_M1445, "M1445"),
126 DEVICE( AL, AL_M1449, "M1449"),
127 DEVICE( AL, AL_M1451, "M1451"),
128 DEVICE( AL, AL_M1461, "M1461"),
129 DEVICE( AL, AL_M4803, "M4803"),
130 DEVICE( ASP, ASP_ABP940, "ABP940"),
131 DEVICE( IMS, IMS_8849, "8849"),
132 DEVICE( TEKRAM2, TEKRAM2_690c, "DC690c"),
133 DEVICE( REALTEK, REALTEK_8029, "8029"),
134 DEVICE( VIA, VIA_82C505, "VT 82C505"),
135 DEVICE( VIA, VIA_82C561, "VT 82C561"),
136 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
137 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
138 DEVICE( EF, EF_ATM_FPGA, "155P-MF1 (FPGA)"),
139 DEVICE( EF, EF_ATM_ASIC, "155P-MF1 (ASIC)"),
140 DEVICE( IMAGINGTECH, IMAGINGTECH_ICPCI, "MVC IC-PCI"),
141 DEVICE( PLX, PLX_9060, "PCI9060 i960 bridge"),
142 DEVICE( ALLIANCE, ALLIANCE_PROVIDEO, "Provideo"),
143 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
144 DEVICE( ZEITNET, ZEITNET_1221, "1221"),
145 DEVICE( SPECIALIX, SPECIALIX_XIO, "XIO/SIO host"),
146 DEVICE( SPECIALIX, SPECIALIX_RIO, "RIO host"),
147 DEVICE( CYCLADES, CYCLADES_Y, "Cyclome-Y"),
148 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
149 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290"),
150 DEVICE( AVANCE, AVANCE_2302, "ALG-2302"),
151 DEVICE( S3, S3_811, "Trio32/Trio64"),
152 DEVICE( S3, S3_868, "Vision 868"),
153 DEVICE( S3, S3_928, "Vision 928-P"),
154 DEVICE( S3, S3_864_1, "Vision 864-P"),
155 DEVICE( S3, S3_864_2, "Vision 864-P"),
156 DEVICE( S3, S3_964_1, "Vision 964-P"),
157 DEVICE( S3, S3_964_2, "Vision 964-P"),
158 DEVICE( S3, S3_968, "Vision 968"),
159 DEVICE( INTEL, INTEL_82375, "82375EB"),
160 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
161 DEVICE( INTEL, INTEL_82378, "82378IB"),
162 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
163 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
164 DEVICE( INTEL, INTEL_7116, "SAA7116"),
165 DEVICE( INTEL, INTEL_82596, "82596"),
166 DEVICE( INTEL, INTEL_82865, "82865"),
167 DEVICE( INTEL, INTEL_82557, "82557"),
168 DEVICE( INTEL, INTEL_82437, "82437"),
169 DEVICE( INTEL, INTEL_82371_0, "82371 Triton PIIX"),
170 DEVICE( INTEL, INTEL_82371_1, "82371 Triton PIIX"),
171 DEVICE( INTEL, INTEL_P6, "Orion P6"),
172 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
173 DEVICE( ADAPTEC, ADAPTEC_7870, "AIC-7870"),
174 DEVICE( ADAPTEC, ADAPTEC_7871, "AIC-7871"),
175 DEVICE( ADAPTEC, ADAPTEC_7872, "AIC-7872"),
176 DEVICE( ADAPTEC, ADAPTEC_7873, "AIC-7873"),
177 DEVICE( ADAPTEC, ADAPTEC_7874, "AIC-7874"),
178 DEVICE( ADAPTEC, ADAPTEC_7880, "AIC-7880U"),
179 DEVICE( ADAPTEC, ADAPTEC_7881, "AIC-7881U"),
180 DEVICE( ADAPTEC, ADAPTEC_7882, "AIC-7882U"),
181 DEVICE( ADAPTEC, ADAPTEC_7883, "AIC-7883U"),
182 DEVICE( ADAPTEC, ADAPTEC_7884, "AIC-7884U"),
183 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
184 DEVICE( HER, HER_STING, "Stingray"),
185 DEVICE( HER, HER_STINGARK, "Stingray ARK 2000PV")
186 };
187
188
189 #ifdef CONFIG_PCI_OPTIMIZE
190
191
192
193
194
195
196
197
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200
201
202
203
204
205
206 struct optimization_type {
207 const char *type;
208 const char *off;
209 const char *on;
210 } bridge_optimization[] = {
211 {"Cache L2", "write trough", "write back"},
212 {"CPU-PCI posted write", "off", "on"},
213 {"CPU-Memory posted write", "off", "on"},
214 {"PCI-Memory posted write", "off", "on"},
215 {"PCI burst", "off", "on"}
216 };
217
218 #define NUM_OPTIMIZATIONS \
219 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
220
221 struct bridge_mapping_type {
222 unsigned char addr;
223 unsigned char mask;
224 unsigned char value;
225 } bridge_mapping[] = {
226
227
228
229
230
231
232
233 {0x0 ,0x02 ,0x02 },
234 {0x53 ,0x02 ,0x02 },
235 {0x53 ,0x01 ,0x01 },
236 {0x54 ,0x01 ,0x01 },
237 {0x54 ,0x02 ,0x02 },
238
239
240
241
242
243 {0x50 ,0x10 ,0x00 },
244 {0x51 ,0x40 ,0x40 },
245 {0x0 ,0x0 ,0x0 },
246 {0x0 ,0x0 ,0x0 },
247 {0x0 ,0x0 ,0x0 },
248
249
250
251
252
253
254 {0x0 ,0x1 ,0x1 },
255 {0x0 ,0x2 ,0x0 },
256 {0x0 ,0x0 ,0x0 },
257 {0x0 ,0x0 ,0x0 },
258 {0x0 ,0x0 ,0x0 }
259 };
260
261 #endif
262
263
264
265
266
267 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
268 {
269 int min = 0,
270 max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
271
272 for ( ; ; )
273 {
274 int i = (min + max) >> 1;
275 long order;
276
277 order = dev_info[i].vendor - (long) vendor;
278 if (!order)
279 order = dev_info[i].device - (long) dev;
280
281 if (order < 0)
282 {
283 min = i + 1;
284 if ( min > max )
285 return 0;
286 continue;
287 }
288
289 if (order > 0)
290 {
291 max = i - 1;
292 if ( min > max )
293 return 0;
294 continue;
295 }
296
297 return & dev_info[ i ];
298 }
299 }
300
301 const char *pci_strclass (unsigned int class)
302 {
303 switch (class >> 8) {
304 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
305 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
306
307 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
308 case PCI_CLASS_STORAGE_IDE: return "IDE interface";
309 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
310 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
311 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
312 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
313
314 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
315 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
316 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
317 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
318 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
319
320 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
321 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
322 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
323
324 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
325 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
326 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
327
328 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
329 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
330 case PCI_CLASS_MEMORY_OTHER: return "Memory";
331
332 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
333 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
334 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
335 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
336 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
337 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
338 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
339 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
340 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
341
342 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
343 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
344 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
345
346 case PCI_CLASS_SYSTEM_PIC: return "PIC";
347 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
348 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
349 case PCI_CLASS_SYSTEM_RTC: return "RTC";
350 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
351
352 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
353 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
354 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
355 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
356
357 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
358 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
359
360 case PCI_CLASS_PROCESSOR_386: return "386";
361 case PCI_CLASS_PROCESSOR_486: return "486";
362 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
363 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
364 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
365 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
366
367 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
368 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
369 case PCI_CLASS_SERIAL_SSA: return "SSA";
370 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
371
372 default: return "Unknown class";
373 }
374 }
375
376
377 const char *pci_strvendor(unsigned int vendor)
378 {
379 switch (vendor) {
380 case PCI_VENDOR_ID_COMPAQ: return "Compaq";
381 case PCI_VENDOR_ID_NCR: return "NCR";
382 case PCI_VENDOR_ID_ATI: return "ATI";
383 case PCI_VENDOR_ID_VLSI: return "VLSI";
384 case PCI_VENDOR_ID_ADL: return "Advance Logic";
385 case PCI_VENDOR_ID_NS: return "NS";
386 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
387 case PCI_VENDOR_ID_WEITEK: return "Weitek";
388 case PCI_VENDOR_ID_DEC: return "DEC";
389 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
390 case PCI_VENDOR_ID_IBM: return "IBM";
391 case PCI_VENDOR_ID_AMD: return "AMD";
392 case PCI_VENDOR_ID_TRIDENT: return "Trident";
393 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
394 case PCI_VENDOR_ID_MATROX: return "Matrox";
395 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
396 case PCI_VENDOR_ID_FD: return "Future Domain";
397 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
398 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
399 case PCI_VENDOR_ID_PCTECH: return "PCTECH";
400 case PCI_VENDOR_ID_DPT: return "DPT";
401 case PCI_VENDOR_ID_OPTI: return "OPTI";
402 case PCI_VENDOR_ID_BUSLOGIC: return "BusLogic";
403 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
404 case PCI_VENDOR_ID_N9: return "Number Nine";
405 case PCI_VENDOR_ID_UMC: return "UMC";
406 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
407 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
408 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
409 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
410 case PCI_VENDOR_ID_OLICOM: return "Olicom";
411 case PCI_VENDOR_ID_CMD: return "CMD";
412 case PCI_VENDOR_ID_VISION: return "Vision";
413 case PCI_VENDOR_ID_SIERRA: return "Sierra";
414 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
415 case PCI_VENDOR_ID_WINBOND: return "Winbond";
416 case PCI_VENDOR_ID_3COM: return "3Com";
417 case PCI_VENDOR_ID_AL: return "Acer Labs";
418 case PCI_VENDOR_ID_ASP: return "Advanced System Products";
419 case PCI_VENDOR_ID_IMS: return "IMS";
420 case PCI_VENDOR_ID_TEKRAM2: return "Tekram";
421 case PCI_VENDOR_ID_REALTEK: return "Realtek";
422 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
423 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
424 case PCI_VENDOR_ID_EF: return "Efficient Networks";
425 case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology";
426 case PCI_VENDOR_ID_PLX: return "PLX";
427 case PCI_VENDOR_ID_ALLIANCE: return "Alliance";
428 case PCI_VENDOR_ID_MUTECH: return "Mutech";
429 case PCI_VENDOR_ID_ZEITNET: return "ZeitNet";
430 case PCI_VENDOR_ID_SPECIALIX: return "Specialix";
431 case PCI_VENDOR_ID_CYCLADES: return "Cyclades";
432 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
433 case PCI_VENDOR_ID_TEKRAM: return "Tekram";
434 case PCI_VENDOR_ID_AVANCE: return "Avance";
435 case PCI_VENDOR_ID_S3: return "S3 Inc.";
436 case PCI_VENDOR_ID_INTEL: return "Intel";
437 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
438 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
439 case PCI_VENDOR_ID_HER: return "Hercules";
440 default: return "Unknown vendor";
441 }
442 }
443
444
445 const char *pci_strdev(unsigned int vendor, unsigned int device)
446 {
447 struct pci_dev_info *info;
448
449 info = pci_lookup_dev(vendor, device);
450 return info ? info->name : "Unknown device";
451 }
452
453
454
455
456
457
458 static void burst_bridge(unsigned char bus, unsigned char devfn,
459 unsigned char pos, int turn_on)
460 {
461 #ifdef CONFIG_PCI_OPTIMIZE
462 struct bridge_mapping_type *bmap;
463 unsigned char val;
464 int i;
465
466 pos *= NUM_OPTIMIZATIONS;
467 printk("PCI bridge optimization.\n");
468 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
469 printk(" %s: ", bridge_optimization[i].type);
470 bmap = &bridge_mapping[pos + i];
471 if (!bmap->addr) {
472 printk("Not supported.");
473 } else {
474 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
475 if ((val & bmap->mask) == bmap->value) {
476 printk("%s.", bridge_optimization[i].on);
477 if (!turn_on) {
478 pcibios_write_config_byte(bus, devfn,
479 bmap->addr,
480 (val | bmap->mask)
481 - bmap->value);
482 printk("Changed! Now %s.", bridge_optimization[i].off);
483 }
484 } else {
485 printk("%s.", bridge_optimization[i].off);
486 if (turn_on) {
487 pcibios_write_config_byte(bus, devfn,
488 bmap->addr,
489 (val & (0xff - bmap->mask))
490 + bmap->value);
491 printk("Changed! Now %s.", bridge_optimization[i].on);
492 }
493 }
494 }
495 printk("\n");
496 }
497 #endif
498 }
499
500
501
502
503
504
505
506
507 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
508 {
509 unsigned long base;
510 unsigned int l, class_rev, bus, devfn;
511 unsigned short vendor, device, status;
512 unsigned char bist, latency, min_gnt, max_lat;
513 int reg, len = 0;
514 const char *str;
515
516 bus = dev->bus->number;
517 devfn = dev->devfn;
518
519 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
520 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
521 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
522 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
523 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
524 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
525 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
526 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
527 if (len + 80 > size) {
528 return -1;
529 }
530 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
531 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
532
533 if (len + 80 > size) {
534 return -1;
535 }
536 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
537 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
538 pci_strdev(vendor, device), class_rev & 0xff);
539
540 if (!pci_lookup_dev(vendor, device)) {
541 len += sprintf(buf + len,
542 "Vendor id=%x. Device id=%x.\n ",
543 vendor, device);
544 }
545
546 str = 0;
547 switch (status & PCI_STATUS_DEVSEL_MASK) {
548 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
549 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
550 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
551 }
552 if (len + strlen(str) > size) {
553 return -1;
554 }
555 len += sprintf(buf + len, str);
556
557 if (status & PCI_STATUS_FAST_BACK) {
558 # define fast_b2b_capable "Fast back-to-back capable. "
559 if (len + strlen(fast_b2b_capable) > size) {
560 return -1;
561 }
562 len += sprintf(buf + len, fast_b2b_capable);
563 # undef fast_b2b_capable
564 }
565
566 if (bist & PCI_BIST_CAPABLE) {
567 # define BIST_capable "BIST capable. "
568 if (len + strlen(BIST_capable) > size) {
569 return -1;
570 }
571 len += sprintf(buf + len, BIST_capable);
572 # undef BIST_capable
573 }
574
575 if (dev->irq) {
576 if (len + 40 > size) {
577 return -1;
578 }
579 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
580 }
581
582 if (dev->master) {
583 if (len + 80 > size) {
584 return -1;
585 }
586 len += sprintf(buf + len, "Master Capable. ");
587 if (latency)
588 len += sprintf(buf + len, "Latency=%d. ", latency);
589 else
590 len += sprintf(buf + len, "No bursts. ");
591 if (min_gnt)
592 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
593 if (max_lat)
594 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
595 }
596
597 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
598 if (len + 40 > size) {
599 return -1;
600 }
601 pcibios_read_config_dword(bus, devfn, reg, &l);
602 base = l;
603 if (!base) {
604 continue;
605 }
606
607 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
608 len += sprintf(buf + len,
609 "\n I/O at 0x%lx.",
610 base & PCI_BASE_ADDRESS_IO_MASK);
611 } else {
612 const char *pref, *type = "unknown";
613
614 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
615 pref = "P";
616 } else {
617 pref = "Non-p";
618 }
619 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
620 case PCI_BASE_ADDRESS_MEM_TYPE_32:
621 type = "32 bit"; break;
622 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
623 type = "20 bit"; break;
624 case PCI_BASE_ADDRESS_MEM_TYPE_64:
625 type = "64 bit";
626
627 reg += 4;
628 pcibios_read_config_dword(bus, devfn, reg, &l);
629 base |= ((u64) l) << 32;
630 break;
631 }
632 len += sprintf(buf + len,
633 "\n %srefetchable %s memory at "
634 "0x%lx.", pref, type,
635 base & PCI_BASE_ADDRESS_MEM_MASK);
636 }
637 }
638
639 len += sprintf(buf + len, "\n");
640 return len;
641 }
642
643
644
645
646
647
648 int get_pci_list(char *buf)
649 {
650 int nprinted, len, size;
651 struct pci_dev *dev;
652 # define MSG "\nwarning: page-size limit reached!\n"
653
654
655 size = PAGE_SIZE - (strlen(MSG) + 1);
656 len = sprintf(buf, "PCI devices found:\n");
657
658 for (dev = pci_devices; dev; dev = dev->next) {
659 nprinted = sprint_dev_config(dev, buf + len, size - len);
660 if (nprinted < 0) {
661 return len + sprintf(buf + len, MSG);
662 }
663 len += nprinted;
664 }
665 return len;
666 }
667
668
669
670
671
672
673 static void *pci_malloc(long size, unsigned long *mem_startp)
674 {
675 void *mem;
676
677 #ifdef DEBUG
678 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
679 #endif
680 mem = (void*) *mem_startp;
681 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
682 memset(mem, 0, size);
683 return mem;
684 }
685
686
687 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
688 {
689 unsigned int devfn, l, max;
690 unsigned char cmd, tmp, hdr_type = 0;
691 struct pci_dev_info *info;
692 struct pci_dev *dev;
693 struct pci_bus *child;
694
695 #ifdef DEBUG
696 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
697 #endif
698
699 max = bus->secondary;
700 for (devfn = 0; devfn < 0xff; ++devfn) {
701 if (PCI_FUNC(devfn) == 0) {
702 pcibios_read_config_byte(bus->number, devfn,
703 PCI_HEADER_TYPE, &hdr_type);
704 } else if (!(hdr_type & 0x80)) {
705
706 continue;
707 }
708
709 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
710 &l);
711
712 if (l == 0xffffffff || l == 0x00000000) {
713 hdr_type = 0;
714 continue;
715 }
716
717 dev = pci_malloc(sizeof(*dev), mem_startp);
718 dev->bus = bus;
719
720
721
722
723
724 dev->next = pci_devices;
725 pci_devices = dev;
726
727 dev->devfn = devfn;
728 dev->vendor = l & 0xffff;
729 dev->device = (l >> 16) & 0xffff;
730
731
732
733
734
735
736 info = pci_lookup_dev(dev->vendor, dev->device);
737 if (!info) {
738 printk("Warning : Unknown PCI device (%x:%x). Please read include/linux/pci.h \n",
739 dev->vendor, dev->device);
740 } else {
741
742 if (info->bridge_type != 0xff) {
743 burst_bridge(bus->number, devfn,
744 info->bridge_type, 1);
745 }
746 }
747
748
749 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
750 &cmd);
751 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
752 cmd | PCI_COMMAND_MASTER);
753 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
754 &tmp);
755 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
756 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
757 cmd);
758
759
760 pcibios_read_config_byte(bus->number, devfn,
761 PCI_INTERRUPT_LINE, &dev->irq);
762
763
764 pcibios_read_config_dword(bus->number, devfn,
765 PCI_CLASS_REVISION, &l);
766 l = l >> 8;
767 dev->class = l;
768
769
770
771
772 dev->sibling = bus->devices;
773 bus->devices = dev;
774
775 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
776 unsigned int buses;
777 unsigned short cr;
778
779
780
781
782 child = pci_malloc(sizeof(*child), mem_startp);
783 child->next = bus->children;
784 bus->children = child;
785 child->self = dev;
786 child->parent = bus;
787
788
789
790
791
792 child->number = child->secondary = ++max;
793 child->primary = bus->secondary;
794 child->subordinate = 0xff;
795
796
797
798
799 pcibios_read_config_word(bus->number, devfn,
800 PCI_COMMAND, &cr);
801 pcibios_write_config_word(bus->number, devfn,
802 PCI_COMMAND, 0x0000);
803 pcibios_write_config_word(bus->number, devfn,
804 PCI_STATUS, 0xffff);
805
806
807
808 pcibios_read_config_dword(bus->number, devfn, 0x18,
809 &buses);
810 buses &= 0xff000000;
811 buses |= (((unsigned int)(child->primary) << 0) |
812 ((unsigned int)(child->secondary) << 8) |
813 ((unsigned int)(child->subordinate) << 16));
814 pcibios_write_config_dword(bus->number, devfn, 0x18,
815 buses);
816
817
818
819 max = scan_bus(child, mem_startp);
820
821
822
823
824 child->subordinate = max;
825 buses = (buses & 0xff00ffff)
826 | ((unsigned int)(child->subordinate) << 16);
827 pcibios_write_config_dword(bus->number, devfn, 0x18,
828 buses);
829 pcibios_write_config_word(bus->number, devfn,
830 PCI_COMMAND, cr);
831 }
832 }
833
834
835
836
837
838
839
840 return max;
841 }
842
843
844 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
845 {
846 mem_start = pcibios_init(mem_start, mem_end);
847
848 if (!pcibios_present()) {
849 printk("pci_init: no BIOS32 detected\n");
850 return mem_start;
851 }
852
853 printk("Probing PCI hardware.\n");
854
855 memset(&pci_root, 0, sizeof(pci_root));
856 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
857
858
859 mem_start = pcibios_fixup(mem_start, mem_end);
860
861 #ifdef DEBUG
862 {
863 int len = get_pci_list((char*)mem_start);
864 if (len) {
865 ((char *) mem_start)[len] = '\0';
866 printk("%s\n", (char *) mem_start);
867 }
868 }
869 #endif
870 return mem_start;
871 }