This source file includes following definitions.
- pci_lookup_dev
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/ptrace.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/bios32.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16
17 #include <asm/page.h>
18
19 struct pci_bus pci_root;
20 struct pci_dev *pci_devices = 0;
21
22
23
24
25
26
27
28
29
30
31
32 #define DEVICE(vid,did,name) \
33 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
34
35 #define BRIDGE(vid,did,name,bridge) \
36 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
37
38
39
40
41
42
43 struct pci_dev_info dev_info[] = {
44 DEVICE( COMPAQ, COMPAQ_1280, "QVision 1280/p"),
45 DEVICE( NCR, NCR_53C810, "53c810"),
46 DEVICE( NCR, NCR_53C820, "53c820"),
47 DEVICE( NCR, NCR_53C825, "53c825"),
48 DEVICE( NCR, NCR_53C815, "53c815"),
49 DEVICE( ATI, ATI_68800, "68800AX"),
50 DEVICE( ATI, ATI_215CT222, "215CT222"),
51 DEVICE( ATI, ATI_210888CX, "210888CX"),
52 DEVICE( ATI, ATI_210888GX, "210888GX"),
53 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
54 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
55 DEVICE( ADL, ADL_2301, "2301"),
56 DEVICE( NS, NS_87410, "87410"),
57 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
58 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
59 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
60 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
61 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
62 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
63 BRIDGE( DEC, DEC_BRD, "DC21050", 0x00),
64 DEVICE( DEC, DEC_TULIP, "DC21040"),
65 DEVICE( DEC, DEC_TGA, "DC21030"),
66 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
67 DEVICE( DEC, DEC_FDDI, "DEFPA"),
68 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
69 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
70 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
71 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
72 DEVICE( CIRRUS, CIRRUS_5436, "GD 5436"),
73 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
74 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
75 DEVICE( CIRRUS, CIRRUS_7543, "CL 7543"),
76 DEVICE( WD, WD_7197, "WD 7197"),
77 DEVICE( AMD, AMD_LANCE, "79C970"),
78 DEVICE( AMD, AMD_SCSI, "53C974"),
79 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
80 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
81 DEVICE( TRIDENT, TRIDENT_9660, "TG 9660"),
82 DEVICE( AI, AI_M1435, "M1435"),
83 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
84 DEVICE( MATROX, MATROX_MIL ,"Millenium"),
85 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
86 DEVICE( CT, CT_65545, "65545"),
87 DEVICE( FD, FD_36C70, "TMC-18C30"),
88 DEVICE( SI, SI_6202, "6202"),
89 DEVICE( SI, SI_503, "85C503"),
90 DEVICE( SI, SI_501, "85C501"),
91 DEVICE( SI, SI_496, "85C496"),
92 DEVICE( SI, SI_601, "85C601"),
93 DEVICE( SI, SI_5511, "85C5511"),
94 DEVICE( SI, SI_5513, "85C5513"),
95 DEVICE( HP, HP_J2585A, "J2585A"),
96 DEVICE( PCTECH, PCTECH_RZ1000, "RZ1000 (buggy)"),
97 DEVICE( DPT, DPT, "SmartCache/Raid"),
98 DEVICE( OPTI, OPTI_82C557, "82C557"),
99 DEVICE( OPTI, OPTI_82C558, "82C558"),
100 DEVICE( OPTI, OPTI_82C621, "82C621"),
101 DEVICE( OPTI, OPTI_82C822, "82C822"),
102 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"BT-946C"),
103 DEVICE( BUSLOGIC, BUSLOGIC_946C, "BT-946C"),
104 DEVICE( BUSLOGIC, BUSLOGIC_930, "BT-930"),
105 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
106 DEVICE( N9, N9_I128, "Imagine 128"),
107 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
108 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
109 DEVICE( UMC, UMC_UM8886BF, "UM8886BF"),
110 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
111 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
112 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
113 DEVICE( UMC, UMC_UM9017F, "UM9017F"),
114 DEVICE( UMC, UMC_UM8886N, "UM8886N"),
115 DEVICE( UMC, UMC_UM8891N, "UM8891N"),
116 DEVICE( X, X_AGX016, "ITT AGX016"),
117 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
118 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
119 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
120 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
121 DEVICE( CMD, CMD_640, "640 (buggy)"),
122 DEVICE( CMD, CMD_646, "646"),
123 DEVICE( VISION, VISION_QD8500, "QD-8500"),
124 DEVICE( VISION, VISION_QD8580, "QD-8580"),
125 DEVICE( SIERRA, SIERRA_STB, "STB Horizon 64"),
126 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
127 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
128 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
129 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
130 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
131 DEVICE( AL, AL_M1445, "M1445"),
132 DEVICE( AL, AL_M1449, "M1449"),
133 DEVICE( AL, AL_M1451, "M1451"),
134 DEVICE( AL, AL_M1461, "M1461"),
135 DEVICE( AL, AL_M1489, "M1489"),
136 DEVICE( AL, AL_M4803, "M4803"),
137 DEVICE( ASP, ASP_ABP940, "ABP940"),
138 DEVICE( IMS, IMS_8849, "8849"),
139 DEVICE( TEKRAM2, TEKRAM2_690c, "DC690c"),
140 DEVICE( REALTEK, REALTEK_8029, "8029"),
141 DEVICE( VIA, VIA_82C505, "VT 82C505"),
142 DEVICE( VIA, VIA_82C561, "VT 82C561"),
143 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
144 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
145 DEVICE( EF, EF_ATM_FPGA, "155P-MF1 (FPGA)"),
146 DEVICE( EF, EF_ATM_ASIC, "155P-MF1 (ASIC)"),
147 DEVICE( IMAGINGTECH, IMAGINGTECH_ICPCI, "MVC IC-PCI"),
148 DEVICE( PLX, PLX_9060, "PCI9060 i960 bridge"),
149 DEVICE( ALLIANCE, ALLIANCE_PROMOTIO, "Promotion-6410"),
150 DEVICE( ALLIANCE, ALLIANCE_PROVIDEO, "Provideo"),
151 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
152 DEVICE( ZEITNET, ZEITNET_1221, "1221"),
153 DEVICE( SPECIALIX, SPECIALIX_XIO, "XIO/SIO host"),
154 DEVICE( SPECIALIX, SPECIALIX_RIO, "RIO host"),
155 DEVICE( CYCLADES, CYCLADES_Y, "Cyclome-Y"),
156 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
157 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290"),
158 DEVICE( AVANCE, AVANCE_2302, "ALG-2302"),
159 DEVICE( S3, S3_811, "Trio32/Trio64"),
160 DEVICE( S3, S3_868, "Vision 868"),
161 DEVICE( S3, S3_928, "Vision 928-P"),
162 DEVICE( S3, S3_864_1, "Vision 864-P"),
163 DEVICE( S3, S3_864_2, "Vision 864-P"),
164 DEVICE( S3, S3_964_1, "Vision 964-P"),
165 DEVICE( S3, S3_964_2, "Vision 964-P"),
166 DEVICE( S3, S3_968, "Vision 968"),
167 DEVICE( INTEL, INTEL_82375, "82375EB"),
168 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
169 DEVICE( INTEL, INTEL_82378, "82378IB"),
170 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
171 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
172 DEVICE( INTEL, INTEL_7116, "SAA7116"),
173 DEVICE( INTEL, INTEL_82596, "82596"),
174 DEVICE( INTEL, INTEL_82865, "82865"),
175 DEVICE( INTEL, INTEL_82557, "82557"),
176 DEVICE( INTEL, INTEL_82437, "82437"),
177 DEVICE( INTEL, INTEL_82371_0, "82371 Triton PIIX"),
178 DEVICE( INTEL, INTEL_82371_1, "82371 Triton PIIX"),
179 DEVICE( INTEL, INTEL_P6, "Orion P6"),
180 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
181 DEVICE( ADAPTEC, ADAPTEC_7870, "AIC-7870"),
182 DEVICE( ADAPTEC, ADAPTEC_7871, "AIC-7871"),
183 DEVICE( ADAPTEC, ADAPTEC_7872, "AIC-7872"),
184 DEVICE( ADAPTEC, ADAPTEC_7873, "AIC-7873"),
185 DEVICE( ADAPTEC, ADAPTEC_7874, "AIC-7874"),
186 DEVICE( ADAPTEC, ADAPTEC_7880, "AIC-7880U"),
187 DEVICE( ADAPTEC, ADAPTEC_7881, "AIC-7881U"),
188 DEVICE( ADAPTEC, ADAPTEC_7882, "AIC-7882U"),
189 DEVICE( ADAPTEC, ADAPTEC_7883, "AIC-7883U"),
190 DEVICE( ADAPTEC, ADAPTEC_7884, "AIC-7884U"),
191 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
192 DEVICE( HER, HER_STING, "Stingray"),
193 DEVICE( HER, HER_STINGARK, "Stingray ARK 2000PV")
194 };
195
196
197 #ifdef CONFIG_PCI_OPTIMIZE
198
199
200
201
202
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209
210
211
212
213
214 struct optimization_type {
215 const char *type;
216 const char *off;
217 const char *on;
218 } bridge_optimization[] = {
219 {"Cache L2", "write trough", "write back"},
220 {"CPU-PCI posted write", "off", "on"},
221 {"CPU-Memory posted write", "off", "on"},
222 {"PCI-Memory posted write", "off", "on"},
223 {"PCI burst", "off", "on"}
224 };
225
226 #define NUM_OPTIMIZATIONS \
227 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
228
229 struct bridge_mapping_type {
230 unsigned char addr;
231 unsigned char mask;
232 unsigned char value;
233 } bridge_mapping[] = {
234
235
236
237
238
239
240
241 {0x0 ,0x02 ,0x02 },
242 {0x53 ,0x02 ,0x02 },
243 {0x53 ,0x01 ,0x01 },
244 {0x54 ,0x01 ,0x01 },
245 {0x54 ,0x02 ,0x02 },
246
247
248
249
250
251 {0x50 ,0x10 ,0x00 },
252 {0x51 ,0x40 ,0x40 },
253 {0x0 ,0x0 ,0x0 },
254 {0x0 ,0x0 ,0x0 },
255 {0x0 ,0x0 ,0x0 },
256
257
258
259
260
261
262 {0x0 ,0x1 ,0x1 },
263 {0x0 ,0x2 ,0x0 },
264 {0x0 ,0x0 ,0x0 },
265 {0x0 ,0x0 ,0x0 },
266 {0x0 ,0x0 ,0x0 }
267 };
268
269 #endif
270
271
272
273
274
275 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
276 {
277 int min = 0,
278 max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
279
280 for ( ; ; )
281 {
282 int i = (min + max) >> 1;
283 long order;
284
285 order = dev_info[i].vendor - (long) vendor;
286 if (!order)
287 order = dev_info[i].device - (long) dev;
288
289 if (order < 0)
290 {
291 min = i + 1;
292 if ( min > max )
293 return 0;
294 continue;
295 }
296
297 if (order > 0)
298 {
299 max = i - 1;
300 if ( min > max )
301 return 0;
302 continue;
303 }
304
305 return & dev_info[ i ];
306 }
307 }
308
309 const char *pci_strclass (unsigned int class)
310 {
311 switch (class >> 8) {
312 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
313 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
314
315 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
316 case PCI_CLASS_STORAGE_IDE: return "IDE interface";
317 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
318 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
319 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
320 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
321
322 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
323 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
324 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
325 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
326 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
327
328 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
329 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
330 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
331
332 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
333 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
334 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
335
336 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
337 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
338 case PCI_CLASS_MEMORY_OTHER: return "Memory";
339
340 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
341 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
342 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
343 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
344 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
345 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
346 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
347 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
348 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
349
350 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
351 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
352 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
353
354 case PCI_CLASS_SYSTEM_PIC: return "PIC";
355 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
356 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
357 case PCI_CLASS_SYSTEM_RTC: return "RTC";
358 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
359
360 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
361 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
362 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
363 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
364
365 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
366 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
367
368 case PCI_CLASS_PROCESSOR_386: return "386";
369 case PCI_CLASS_PROCESSOR_486: return "486";
370 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
371 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
372 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
373 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
374
375 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
376 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
377 case PCI_CLASS_SERIAL_SSA: return "SSA";
378 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
379
380 default: return "Unknown class";
381 }
382 }
383
384
385 const char *pci_strvendor(unsigned int vendor)
386 {
387 switch (vendor) {
388 case PCI_VENDOR_ID_COMPAQ: return "Compaq";
389 case PCI_VENDOR_ID_NCR: return "NCR";
390 case PCI_VENDOR_ID_ATI: return "ATI";
391 case PCI_VENDOR_ID_VLSI: return "VLSI";
392 case PCI_VENDOR_ID_ADL: return "Advance Logic";
393 case PCI_VENDOR_ID_NS: return "NS";
394 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
395 case PCI_VENDOR_ID_WEITEK: return "Weitek";
396 case PCI_VENDOR_ID_DEC: return "DEC";
397 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
398 case PCI_VENDOR_ID_IBM: return "IBM";
399 case PCI_VENDOR_ID_WD: return "Western Digital";
400 case PCI_VENDOR_ID_AMD: return "AMD";
401 case PCI_VENDOR_ID_TRIDENT: return "Trident";
402 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
403 case PCI_VENDOR_ID_MATROX: return "Matrox";
404 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
405 case PCI_VENDOR_ID_FD: return "Future Domain";
406 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
407 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
408 case PCI_VENDOR_ID_PCTECH: return "PCTECH";
409 case PCI_VENDOR_ID_DPT: return "DPT";
410 case PCI_VENDOR_ID_OPTI: return "OPTI";
411 case PCI_VENDOR_ID_BUSLOGIC: return "BusLogic";
412 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
413 case PCI_VENDOR_ID_N9: return "Number Nine";
414 case PCI_VENDOR_ID_UMC: return "UMC";
415 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
416 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
417 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
418 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
419 case PCI_VENDOR_ID_FOREX: return "Forex";
420 case PCI_VENDOR_ID_OLICOM: return "Olicom";
421 case PCI_VENDOR_ID_CMD: return "CMD";
422 case PCI_VENDOR_ID_VISION: return "Vision";
423 case PCI_VENDOR_ID_SIERRA: return "Sierra";
424 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
425 case PCI_VENDOR_ID_WINBOND: return "Winbond";
426 case PCI_VENDOR_ID_3COM: return "3Com";
427 case PCI_VENDOR_ID_AL: return "Acer Labs";
428 case PCI_VENDOR_ID_ASP: return "Advanced System Products";
429 case PCI_VENDOR_ID_IMS: return "IMS";
430 case PCI_VENDOR_ID_TEKRAM2: return "Tekram";
431 case PCI_VENDOR_ID_AMCC: return "AMCC";
432 case PCI_VENDOR_ID_REALTEK: return "Realtek";
433 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
434 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
435 case PCI_VENDOR_ID_EF: return "Efficient Networks";
436 case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology";
437 case PCI_VENDOR_ID_PLX: return "PLX";
438 case PCI_VENDOR_ID_ALLIANCE: return "Alliance";
439 case PCI_VENDOR_ID_MUTECH: return "Mutech";
440 case PCI_VENDOR_ID_ZEITNET: return "ZeitNet";
441 case PCI_VENDOR_ID_SPECIALIX: return "Specialix";
442 case PCI_VENDOR_ID_CYCLADES: return "Cyclades";
443 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
444 case PCI_VENDOR_ID_TEKRAM: return "Tekram";
445 case PCI_VENDOR_ID_AVANCE: return "Avance";
446 case PCI_VENDOR_ID_S3: return "S3 Inc.";
447 case PCI_VENDOR_ID_INTEL: return "Intel";
448 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
449 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
450 case PCI_VENDOR_ID_HER: return "Hercules";
451 default: return "Unknown vendor";
452 }
453 }
454
455
456 const char *pci_strdev(unsigned int vendor, unsigned int device)
457 {
458 struct pci_dev_info *info;
459
460 info = pci_lookup_dev(vendor, device);
461 return info ? info->name : "Unknown device";
462 }
463
464
465
466
467
468
469 static void burst_bridge(unsigned char bus, unsigned char devfn,
470 unsigned char pos, int turn_on)
471 {
472 #ifdef CONFIG_PCI_OPTIMIZE
473 struct bridge_mapping_type *bmap;
474 unsigned char val;
475 int i;
476
477 pos *= NUM_OPTIMIZATIONS;
478 printk("PCI bridge optimization.\n");
479 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
480 printk(" %s: ", bridge_optimization[i].type);
481 bmap = &bridge_mapping[pos + i];
482 if (!bmap->addr) {
483 printk("Not supported.");
484 } else {
485 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
486 if ((val & bmap->mask) == bmap->value) {
487 printk("%s.", bridge_optimization[i].on);
488 if (!turn_on) {
489 pcibios_write_config_byte(bus, devfn,
490 bmap->addr,
491 (val | bmap->mask)
492 - bmap->value);
493 printk("Changed! Now %s.", bridge_optimization[i].off);
494 }
495 } else {
496 printk("%s.", bridge_optimization[i].off);
497 if (turn_on) {
498 pcibios_write_config_byte(bus, devfn,
499 bmap->addr,
500 (val & (0xff - bmap->mask))
501 + bmap->value);
502 printk("Changed! Now %s.", bridge_optimization[i].on);
503 }
504 }
505 }
506 printk("\n");
507 }
508 #endif
509 }
510
511
512
513
514
515
516
517
518 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
519 {
520 unsigned long base;
521 unsigned int l, class_rev, bus, devfn;
522 unsigned short vendor, device, status;
523 unsigned char bist, latency, min_gnt, max_lat;
524 int reg, len = 0;
525 const char *str;
526
527 bus = dev->bus->number;
528 devfn = dev->devfn;
529
530 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
531 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
532 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
533 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
534 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
535 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
536 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
537 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
538 if (len + 80 > size) {
539 return -1;
540 }
541 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
542 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
543
544 if (len + 80 > size) {
545 return -1;
546 }
547 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
548 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
549 pci_strdev(vendor, device), class_rev & 0xff);
550
551 if (!pci_lookup_dev(vendor, device)) {
552 len += sprintf(buf + len,
553 "Vendor id=%x. Device id=%x.\n ",
554 vendor, device);
555 }
556
557 str = 0;
558 switch (status & PCI_STATUS_DEVSEL_MASK) {
559 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
560 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
561 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
562 }
563 if (len + strlen(str) > size) {
564 return -1;
565 }
566 len += sprintf(buf + len, str);
567
568 if (status & PCI_STATUS_FAST_BACK) {
569 # define fast_b2b_capable "Fast back-to-back capable. "
570 if (len + strlen(fast_b2b_capable) > size) {
571 return -1;
572 }
573 len += sprintf(buf + len, fast_b2b_capable);
574 # undef fast_b2b_capable
575 }
576
577 if (bist & PCI_BIST_CAPABLE) {
578 # define BIST_capable "BIST capable. "
579 if (len + strlen(BIST_capable) > size) {
580 return -1;
581 }
582 len += sprintf(buf + len, BIST_capable);
583 # undef BIST_capable
584 }
585
586 if (dev->irq) {
587 if (len + 40 > size) {
588 return -1;
589 }
590 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
591 }
592
593 if (dev->master) {
594 if (len + 80 > size) {
595 return -1;
596 }
597 len += sprintf(buf + len, "Master Capable. ");
598 if (latency)
599 len += sprintf(buf + len, "Latency=%d. ", latency);
600 else
601 len += sprintf(buf + len, "No bursts. ");
602 if (min_gnt)
603 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
604 if (max_lat)
605 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
606 }
607
608 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
609 if (len + 40 > size) {
610 return -1;
611 }
612 pcibios_read_config_dword(bus, devfn, reg, &l);
613 base = l;
614 if (!base) {
615 continue;
616 }
617
618 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
619 len += sprintf(buf + len,
620 "\n I/O at 0x%lx.",
621 base & PCI_BASE_ADDRESS_IO_MASK);
622 } else {
623 const char *pref, *type = "unknown";
624
625 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
626 pref = "P";
627 } else {
628 pref = "Non-p";
629 }
630 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
631 case PCI_BASE_ADDRESS_MEM_TYPE_32:
632 type = "32 bit"; break;
633 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
634 type = "20 bit"; break;
635 case PCI_BASE_ADDRESS_MEM_TYPE_64:
636 type = "64 bit";
637
638 reg += 4;
639 pcibios_read_config_dword(bus, devfn, reg, &l);
640 base |= ((u64) l) << 32;
641 break;
642 }
643 len += sprintf(buf + len,
644 "\n %srefetchable %s memory at "
645 "0x%lx.", pref, type,
646 base & PCI_BASE_ADDRESS_MEM_MASK);
647 }
648 }
649
650 len += sprintf(buf + len, "\n");
651 return len;
652 }
653
654
655
656
657
658
659 int get_pci_list(char *buf)
660 {
661 int nprinted, len, size;
662 struct pci_dev *dev;
663 # define MSG "\nwarning: page-size limit reached!\n"
664
665
666 size = PAGE_SIZE - (strlen(MSG) + 1);
667 len = sprintf(buf, "PCI devices found:\n");
668
669 for (dev = pci_devices; dev; dev = dev->next) {
670 nprinted = sprint_dev_config(dev, buf + len, size - len);
671 if (nprinted < 0) {
672 return len + sprintf(buf + len, MSG);
673 }
674 len += nprinted;
675 }
676 return len;
677 }
678
679
680
681
682
683
684 static void *pci_malloc(long size, unsigned long *mem_startp)
685 {
686 void *mem;
687
688 #ifdef DEBUG
689 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
690 #endif
691 mem = (void*) *mem_startp;
692 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
693 memset(mem, 0, size);
694 return mem;
695 }
696
697
698 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
699 {
700 unsigned int devfn, l, max;
701 unsigned char cmd, tmp, hdr_type = 0;
702 struct pci_dev_info *info;
703 struct pci_dev *dev;
704 struct pci_bus *child;
705
706 #ifdef DEBUG
707 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
708 #endif
709
710 max = bus->secondary;
711 for (devfn = 0; devfn < 0xff; ++devfn) {
712 if (PCI_FUNC(devfn) == 0) {
713 pcibios_read_config_byte(bus->number, devfn,
714 PCI_HEADER_TYPE, &hdr_type);
715 } else if (!(hdr_type & 0x80)) {
716
717 continue;
718 }
719
720 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
721 &l);
722
723 if (l == 0xffffffff || l == 0x00000000) {
724 hdr_type = 0;
725 continue;
726 }
727
728 dev = pci_malloc(sizeof(*dev), mem_startp);
729 dev->bus = bus;
730
731
732
733
734
735 dev->next = pci_devices;
736 pci_devices = dev;
737
738 dev->devfn = devfn;
739 dev->vendor = l & 0xffff;
740 dev->device = (l >> 16) & 0xffff;
741
742
743
744
745
746
747 info = pci_lookup_dev(dev->vendor, dev->device);
748 if (!info) {
749 printk("Warning : Unknown PCI device (%x:%x). Please read include/linux/pci.h \n",
750 dev->vendor, dev->device);
751 } else {
752
753 if (info->bridge_type != 0xff) {
754 burst_bridge(bus->number, devfn,
755 info->bridge_type, 1);
756 }
757 }
758
759
760 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
761 &cmd);
762 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
763 cmd | PCI_COMMAND_MASTER);
764 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
765 &tmp);
766 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
767 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
768 cmd);
769
770
771 pcibios_read_config_byte(bus->number, devfn,
772 PCI_INTERRUPT_LINE, &dev->irq);
773
774
775 pcibios_read_config_dword(bus->number, devfn,
776 PCI_CLASS_REVISION, &l);
777 l = l >> 8;
778 dev->class = l;
779
780
781
782
783 dev->sibling = bus->devices;
784 bus->devices = dev;
785
786 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
787 unsigned int buses;
788 unsigned short cr;
789
790
791
792
793 child = pci_malloc(sizeof(*child), mem_startp);
794 child->next = bus->children;
795 bus->children = child;
796 child->self = dev;
797 child->parent = bus;
798
799
800
801
802
803 child->number = child->secondary = ++max;
804 child->primary = bus->secondary;
805 child->subordinate = 0xff;
806
807
808
809
810 pcibios_read_config_word(bus->number, devfn,
811 PCI_COMMAND, &cr);
812 pcibios_write_config_word(bus->number, devfn,
813 PCI_COMMAND, 0x0000);
814 pcibios_write_config_word(bus->number, devfn,
815 PCI_STATUS, 0xffff);
816
817
818
819 pcibios_read_config_dword(bus->number, devfn, 0x18,
820 &buses);
821 buses &= 0xff000000;
822 buses |= (((unsigned int)(child->primary) << 0) |
823 ((unsigned int)(child->secondary) << 8) |
824 ((unsigned int)(child->subordinate) << 16));
825 pcibios_write_config_dword(bus->number, devfn, 0x18,
826 buses);
827
828
829
830 max = scan_bus(child, mem_startp);
831
832
833
834
835 child->subordinate = max;
836 buses = (buses & 0xff00ffff)
837 | ((unsigned int)(child->subordinate) << 16);
838 pcibios_write_config_dword(bus->number, devfn, 0x18,
839 buses);
840 pcibios_write_config_word(bus->number, devfn,
841 PCI_COMMAND, cr);
842 }
843 }
844
845
846
847
848
849
850
851 return max;
852 }
853
854
855 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
856 {
857 mem_start = pcibios_init(mem_start, mem_end);
858
859 if (!pcibios_present()) {
860 printk("pci_init: no BIOS32 detected\n");
861 return mem_start;
862 }
863
864 printk("Probing PCI hardware.\n");
865
866 memset(&pci_root, 0, sizeof(pci_root));
867 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
868
869
870 mem_start = pcibios_fixup(mem_start, mem_end);
871
872 #ifdef DEBUG
873 {
874 int len = get_pci_list((char*)mem_start);
875 if (len) {
876 ((char *) mem_start)[len] = '\0';
877 printk("%s\n", (char *) mem_start);
878 }
879 }
880 #endif
881 return mem_start;
882 }
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