root/include/asm-sparc/timer.h

/* */

INCLUDED FROM

   1 /* $Id: timer.h,v 1.10 1995/11/25 02:33:03 davem Exp $
   2  * timer.h:  Definitions for the timer chips on the Sparc.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 #ifndef _SPARC_TIMER_H
   7 #define _SPARC_TIMER_H
   8 
   9 #include <asm/system.h>  /* For NCPUS */
  10 
  11 /* Timer structures. The interrupt timer has two properties which
  12  * are the counter (which is handled in do_timer in sched.c) and the limit.
  13  * This limit is where the timer's counter 'wraps' around. Oddly enough,
  14  * the sun4c timer when it hits the limit wraps back to 1 and not zero
  15  * thus when calculating the value at which it will fire a microsecond you
  16  * must adjust by one.  Thanks SUN for designing such great hardware ;(
  17  */
  18 
  19 /* Note that I am only going to use the timer that interrupts at
  20  * Sparc IRQ 10.  There is another one available that can fire at
  21  * IRQ 14. Currently it is left untouched, we keep the PROM's limit
  22  * register value and let the prom take these interrupts.  This allows
  23  * L1-A to work.
  24  */
  25 
  26 struct sun4c_timer_info {
  27   volatile unsigned int cur_count10;
  28   volatile unsigned int timer_limit10;
  29   volatile unsigned int cur_count14;
  30   volatile unsigned int timer_limit14;
  31 };
  32 
  33 #define SUN4C_TIMER_PHYSADDR   0xf3000000
  34 
  35 /* All accesses to the sun4c timer registers should use this macro. */
  36 #define  SUN4C_TIMER_STRUCT  ((volatile struct sun4c_timer_info *) TIMER_VADDR)
  37 
  38 /* A sun4m has two blocks of registers which are probably of the same
  39  * structure. LSI Logic's L64851 is told to _decrement_ from the limit
  40  * value. Aurora behaves similarly but its limit value is compacted in
  41  * other fashion (it's wider). Documented fields are defined here.
  42  */
  43 
  44 /* As with the interrupt register, we have two classes of timer registers
  45  * which are per-cpu and master.  Per-cpu timers only hit that cpu and are
  46  * only level 14 ticks, master timer hits all cpus and is level 10.
  47  */
  48 
  49 #define SUN4M_PRM_CNT_L       0x80000000
  50 #define SUN4M_PRM_CNT_LVALUE  0x7FFFFC00
  51 
  52 struct sun4m_timer_percpu_info {
  53   volatile unsigned int l14_timer_limit;    /* Initial value is 0x009c4000 */
  54   volatile unsigned int l14_cur_count;
  55 
  56   /* This register appears to be write only and/or inaccessible
  57    * on Uni-Processor sun4m machines.
  58    */
  59   volatile unsigned int l14_limit_noclear;  /* Data access error is here */
  60 
  61   volatile unsigned int cntrl;            /* =1 after POST on Aurora */
  62   volatile unsigned char space[PAGE_SIZE - 16];
  63 };
  64 
  65 struct sun4m_timer_regs {
  66         struct sun4m_timer_percpu_info cpu_timers[NCPUS];
  67         volatile unsigned int l10_timer_limit;
  68         volatile unsigned int l10_cur_count;
  69 
  70         /* Again, this appears to be write only and/or inaccessible
  71          * on uni-processor sun4m machines.
  72          */
  73         volatile unsigned int l10_limit_noclear;
  74 
  75         /* This register too, it must be magic. */
  76         volatile unsigned int foobar;
  77 
  78         volatile unsigned int cfg;     /* equals zero at boot time... */
  79 };
  80 
  81 extern struct sun4m_timer_regs *sun4m_timers;
  82 extern volatile unsigned int *master_l10_counter;
  83 extern volatile unsigned int *master_l10_limit;
  84 
  85 #endif /* !(_SPARC_TIMER_H) */

/* */