root/arch/alpha/kernel/bios32.c

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DEFINITIONS

This source file includes following definitions.
  1. pcibios_present
  2. layout_dev
  3. layout_bus
  4. pcibios_find_device
  5. pcibios_find_class
  6. pcibios_present
  7. pcibios_init
  8. enable_ide
  9. common_fixup
  10. eb66p_fixup
  11. cabriolet_fixup
  12. eb66_and_eb64p_fixup
  13. avanti_and_noname_fixup
  14. pcibios_fixup
  15. pcibios_strerror

   1 /*
   2  * bios32.c - PCI BIOS functions for Alpha systems not using BIOS
   3  *            emulation code.
   4  *
   5  * Written by Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *
   7  * Adapted to 64-bit kernel and then rewritten by David Mosberger
   8  * (davidm@cs.arizona.edu)
   9  *
  10  * For more information, please consult
  11  *
  12  * PCI BIOS Specification Revision
  13  * PCI Local Bus Specification
  14  * PCI System Design Guide
  15  *
  16  * PCI Special Interest Group
  17  * M/S HF3-15A
  18  * 5200 N.E. Elam Young Parkway
  19  * Hillsboro, Oregon 97124-6497
  20  * +1 (503) 696-2000
  21  * +1 (800) 433-5177
  22  *
  23  * Manuals are $25 each or $50 for all three, plus $7 shipping
  24  * within the United States, $35 abroad.
  25  */
  26 #include <linux/config.h>
  27 
  28 #ifndef CONFIG_PCI
  29 
  30 int pcibios_present(void)
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  31 {
  32         return 0;
  33 }
  34 
  35 #else /* CONFIG_PCI */
  36 
  37 #include <linux/kernel.h>
  38 #include <linux/bios32.h>
  39 #include <linux/pci.h>
  40 #include <linux/malloc.h>
  41 #include <linux/mm.h>
  42 
  43 #include <asm/hwrpb.h>
  44 #include <asm/io.h>
  45 
  46 
  47 #define KB              1024
  48 #define MB              (1024*KB)
  49 #define GB              (1024*MB)
  50 
  51 #define MAJOR_REV       0
  52 #define MINOR_REV       3
  53 
  54 /*
  55  * Align VAL to ALIGN, which must be a power of two.
  56  */
  57 #define ALIGN(val,align)        (((val) + ((align) - 1)) & ~((align) - 1))
  58 
  59 
  60 /*
  61  * Temporary internal macro.  If this 0, then do not write to any of
  62  * the PCI registers, merely read them (i.e., use configuration as
  63  * determined by SRM).  The SRM seem do be doing a less than perfect
  64  * job in configuring PCI devices, so for now we do it ourselves.
  65  * Reconfiguring PCI devices breaks console (RPB) callbacks, but
  66  * those don't work properly with 64 bit addresses anyways.
  67  *
  68  * The accepted convention seems to be that the console (POST
  69  * software) should fully configure boot devices and configure the
  70  * interrupt routing of *all* devices.  In particular, the base
  71  * addresses of non-boot devices need not be initialized.  For
  72  * example, on the AXPpci33 board, the base address a #9 GXE PCI
  73  * graphics card reads as zero (this may, however, be due to a bug in
  74  * the graphics card---there have been some rumor that the #9 BIOS
  75  * incorrectly resets that address to 0...).
  76  */
  77 #define PCI_MODIFY              1
  78 
  79 
  80 extern struct hwrpb_struct *hwrpb;
  81 
  82 
  83 #if PCI_MODIFY
  84 
  85 static unsigned int     io_base  = 64*KB;       /* <64KB are (E)ISA ports */
  86 static unsigned int     mem_base = 16*MB;       /* <16MB is ISA memory */
  87 
  88 
  89 /*
  90  * Layout memory and I/O for a device:
  91  */
  92 static void layout_dev(struct pci_dev *dev)
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  93 {
  94         struct pci_bus *bus;
  95         unsigned short cmd;
  96         unsigned int base, mask, size, reg;
  97 
  98         bus = dev->bus;
  99         pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
 100 
 101         for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
 102                 /*
 103                  * Figure out how much space and of what type this
 104                  * device wants.
 105                  */
 106                 pcibios_write_config_dword(bus->number, dev->devfn, reg,
 107                                            0xffffffff);
 108                 pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
 109                 if (!base) {
 110                         /* this base-address register is unused */
 111                         continue;
 112                 }
 113                 /*
 114                  * We've read the base address register back after
 115                  * writing all ones and so now we must decode it.
 116                  */
 117                 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
 118                         /*
 119                          * I/O space base address register.
 120                          */
 121                         cmd |= PCI_COMMAND_IO;
 122 
 123                         base &= PCI_BASE_ADDRESS_IO_MASK;
 124                         mask = (~base << 1) | 0x1;
 125                         size = (mask & base) & 0xffffffff;
 126                         base = ALIGN(io_base, size);
 127                         io_base = base + size;
 128                         pcibios_write_config_dword(bus->number, dev->devfn, 
 129                                                    reg, base | 0x1);
 130                 } else {
 131                         unsigned int type;
 132                         /*
 133                          * Memory space base address register.
 134                          */
 135                         cmd |= PCI_COMMAND_MEMORY;
 136 
 137                         type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 138                         base &= PCI_BASE_ADDRESS_MEM_MASK;
 139                         mask = (~base << 1) | 0x1;
 140                         size = (mask & base) & 0xffffffff;
 141                         switch (type) {
 142                               case PCI_BASE_ADDRESS_MEM_TYPE_32:
 143                                 break;
 144 
 145                               case PCI_BASE_ADDRESS_MEM_TYPE_64:
 146                                 printk("bios32 WARNING: "
 147                                        "ignoring 64-bit device in "
 148                                        "slot %d, function %d: \n",
 149                                        PCI_SLOT(dev->devfn),
 150                                        PCI_FUNC(dev->devfn));
 151                                 reg += 4;       /* skip extra 4 bytes */
 152                                 continue;
 153 
 154                               case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 155                                 /*
 156                                  * Allocating memory below 1MB is *very*
 157                                  * tricky, as there may be all kinds of
 158                                  * ISA devices lurking that we don't know
 159                                  * about.  For now, we just cross fingers
 160                                  * and hope nobody tries to do this on an
 161                                  * Alpha (or that the console has set it
 162                                  * up properly).
 163                                  */
 164                                 printk("bios32 WARNING: slot %d, function %d "
 165                                        "requests memory below 1MB---don't "
 166                                        "know how to do that.\n",
 167                                        PCI_SLOT(dev->devfn),
 168                                        PCI_FUNC(dev->devfn));
 169                                 continue;
 170                         }
 171                         /*
 172                          * The following holds at least for the Low Cost
 173                          * Alpha implementation of the PCI interface:
 174                          *
 175                          * In sparse memory address space, the first
 176                          * octant (16MB) of every 128MB segment is
 177                          * aliased to the the very first 16MB of the
 178                          * address space (i.e., it aliases the ISA
 179                          * memory address space).  Thus, we try to
 180                          * avoid allocating PCI devices in that range.
 181                          * Can be allocated in 2nd-7th octant only.
 182                          * Devices that need more than 112MB of
 183                          * address space must be accessed through
 184                          * dense memory space only!
 185                          */
 186                         base = ALIGN(mem_base, size);
 187                         if (size > 7 * 16*MB) {
 188                                 printk("bios32 WARNING: slot %d, function %d "
 189                                        "requests  %dB of contiguous address "
 190                                        " space---don't use sparse memory "
 191                                        " accesses on this device!!\n",
 192                                        PCI_SLOT(dev->devfn),
 193                                        PCI_FUNC(dev->devfn), size);
 194                         } else {
 195                                 if (((base / 16*MB) & 0x7) == 0) {
 196                                         base &= ~(128*MB - 1);
 197                                         base += 16*MB;
 198                                         base  = ALIGN(base, size);
 199                                 }
 200                                 if (base / 128*MB != (base + size) / 128*MB) {
 201                                         base &= ~(128*MB - 1);
 202                                         base += (128 + 16)*MB;
 203                                         base  = ALIGN(base, size);
 204                                 }
 205                         }
 206                         mem_base = base + size;
 207                         pcibios_write_config_dword(bus->number, dev->devfn,
 208                                                    reg, base);
 209                 }
 210         }
 211         /* enable device: */
 212         if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
 213             dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
 214             dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
 215             dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
 216         {
 217                 /*
 218                  * All of these (may) have I/O scattered all around
 219                  * and may not use i/o-base address registers at all.
 220                  * So we just have to always enable I/O to these
 221                  * devices.
 222                  */
 223                 cmd |= PCI_COMMAND_IO;
 224         }
 225         pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
 226                                   cmd | PCI_COMMAND_MASTER);
 227 }
 228 
 229 
 230 static void layout_bus(struct pci_bus *bus)
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 231 {
 232         unsigned int l, tio, bio, tmem, bmem;
 233         struct pci_bus *child;
 234         struct pci_dev *dev;
 235 
 236         if (!bus->devices && !bus->children)
 237           return;
 238 
 239         /*
 240          * Align the current bases on appropriate boundaries (4K for
 241          * IO and 1MB for memory).
 242          */
 243         bio = io_base = ALIGN(io_base, 4*KB);
 244         bmem = mem_base = ALIGN(mem_base, 1*MB);
 245 
 246         /*
 247          * Allocate space to each device:
 248          */
 249         for (dev = bus->devices; dev; dev = dev->sibling) {
 250                 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
 251                         layout_dev(dev);
 252                 }
 253         }
 254         /*
 255          * Recursively allocate space for all of the sub-buses:
 256          */
 257         for (child = bus->children; child; child = child->next) {
 258                 layout_bus(child);
 259         }
 260         /*
 261          * Align the current bases on 4K and 1MB boundaries:
 262          */
 263         tio = io_base = ALIGN(io_base, 4*KB);
 264         tmem = mem_base = ALIGN(mem_base, 1*MB);
 265 
 266         if (bus->self) {
 267                 struct pci_dev *bridge = bus->self;
 268                 /*
 269                  * Set up the top and bottom of the I/O memory segment
 270                  * for this bus.
 271                  */
 272                 pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
 273                                           0x1c, &l);
 274                 l = l | (bio >> 8) | ((tio - 1) & 0xf000);
 275                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 276                                            0x1c, l);
 277 
 278                 l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
 279                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 280                                            0x20, l);
 281                 /*
 282                  * Turn off downstream PF memory address range:
 283                  */
 284                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 285                                            0x24, 0x0000ffff);
 286                 /*
 287                  * Tell bridge that there is an ISA bus in the system:
 288                  */
 289                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 290                                            0x3c, 0x00040000);
 291                 /*
 292                  * Clear status bits, enable I/O (for downstream I/O),
 293                  * turn on master enable (for upstream I/O), turn on
 294                  * memory enable (for downstream memory), turn on
 295                  * master enable (for upstream memory and I/O).
 296                  */
 297                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 298                                            0x4, 0xffff0007);
 299         }
 300 }
 301 
 302 #endif /* !PCI_MODIFY */
 303 
 304 
 305 /*
 306  * Given the vendor and device ids, find the n'th instance of that device
 307  * in the system.  
 308  */
 309 int pcibios_find_device (unsigned short vendor, unsigned short device_id,
     /* [previous][next][first][last][top][bottom][index][help] */
 310                          unsigned short index, unsigned char *bus,
 311                          unsigned char *devfn)
 312 {
 313         unsigned int curr = 0;
 314         struct pci_dev *dev;
 315 
 316         for (dev = pci_devices; dev; dev = dev->next) {
 317                 if (dev->vendor == vendor && dev->device == device_id) {
 318                         if (curr == index) {
 319                                 *devfn = dev->devfn;
 320                                 *bus = dev->bus->number;
 321                                 return PCIBIOS_SUCCESSFUL;
 322                         }
 323                         ++curr;
 324                 }
 325         }
 326         return PCIBIOS_DEVICE_NOT_FOUND;
 327 }
 328 
 329 
 330 /*
 331  * Given the class, find the n'th instance of that device
 332  * in the system.
 333  */
 334 int pcibios_find_class (unsigned int class_code, unsigned short index,
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 335                         unsigned char *bus, unsigned char *devfn)
 336 {
 337         unsigned int curr = 0;
 338         struct pci_dev *dev;
 339 
 340         for (dev = pci_devices; dev; dev = dev->next) {
 341                 if (dev->class == class_code) {
 342                         if (curr == index) {
 343                                 *devfn = dev->devfn;
 344                                 *bus = dev->bus->number;
 345                                 return PCIBIOS_SUCCESSFUL;
 346                         }
 347                         ++curr;
 348                 }
 349         }
 350         return PCIBIOS_DEVICE_NOT_FOUND;
 351 }
 352 
 353 
 354 int pcibios_present(void)
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 355 {
 356         return 1;
 357 }
 358 
 359 
 360 unsigned long pcibios_init(unsigned long mem_start,
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 361                            unsigned long mem_end)
 362 {
 363         printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
 364 
 365 #if !PCI_MODIFY
 366         printk("...NOT modifying existing (SRM) PCI configuration\n");
 367 #endif
 368         return mem_start;
 369 }
 370 
 371 /*
 372  * The SRM console *disables* the IDE interface, this code ensures its
 373  * enabled.
 374  *
 375  * This code bangs on a control register of the 87312 Super I/O chip
 376  * that implements parallel port/serial ports/IDE/FDI.  Depending on
 377  * the motherboard, the Super I/O chip can be configured through a
 378  * pair of registers that are located either at I/O ports 0x26e/0x26f
 379  * or 0x398/0x399.  Unfortunately, autodetecting which base address is
 380  * in use works only once (right after a reset).  The Super I/O chip
 381  * has the additional quirk that configuration register data must be
 382  * written twice (I believe this is a saftey feature to prevent
 383  * accidental modification---fun, isn't it?).
 384  */
 385 static inline void enable_ide(long ide_base)
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 386 {
 387         int data;
 388 
 389         outb(0, ide_base);              /* set the index register for reg #0 */
 390         data = inb(ide_base+1);         /* read the current contents */
 391         outb(0, ide_base);              /* set the index register for reg #0 */
 392         outb(data | 0x40, ide_base+1);  /* turn on IDE */
 393         outb(data | 0x40, ide_base+1);  /* turn on IDE, really! */
 394 }
 395 
 396 /*
 397  * Most evaluation boards share most of the fixup code, which is isolated here.
 398  * This function is declared "inline" as only one platform will ever be selected
 399  * in any given kernel.  If that platform doesn't need this code, we don't want
 400  * it around as dead code.
 401  */
 402 static inline void common_fixup(long min_idsel, long max_idsel, long irqs_per_slot,
     /* [previous][next][first][last][top][bottom][index][help] */
 403                                 char irq_tab[max_idsel - min_idsel + 1][irqs_per_slot],
 404                                 long ide_base)
 405 {
 406         struct pci_dev *dev;
 407         unsigned char pin;
 408         /*
 409          * Go through all devices, fixing up irqs as we see fit:
 410          */
 411         for (dev = pci_devices; dev; dev = dev->next) {
 412                 dev->irq = 0;
 413                 /*
 414                  * Ignore things not on the primary bus - I'll figure
 415                  * this out one day - Dave Rusling
 416                  */
 417                 if (dev->bus->number != 0)
 418                         continue;
 419 
 420                 /* read the pin */
 421                 pcibios_read_config_byte(dev->bus->number, dev->devfn,
 422                                          PCI_INTERRUPT_PIN, &pin);
 423                 if (irq_tab[PCI_SLOT(dev->devfn) - min_idsel][pin] != -1)
 424                         dev->irq = irq_tab[PCI_SLOT(dev->devfn) - min_idsel][pin];
 425 #if PCI_MODIFY
 426                 /* tell the device: */
 427                 pcibios_write_config_byte(dev->bus->number, dev->devfn,
 428                                           PCI_INTERRUPT_LINE, dev->irq);
 429 #endif
 430                 /*
 431                  * if its a VGA, enable its BIOS ROM at C0000
 432                  */
 433                 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
 434                         pcibios_write_config_dword(dev->bus->number, dev->devfn,
 435                                                    PCI_ROM_ADDRESS,
 436                                                    0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
 437                 }
 438         }
 439         if (ide_base) {
 440                 enable_ide(ide_base);
 441         }
 442 }
 443 
 444 /*
 445  * The EB66+ is very similar to the EB66 except that it does not have
 446  * the on-board NCR and Tulip chips.  In the code below, I have used
 447  * slot number to refer to the id select line and *not* the slot
 448  * number used in the EB66+ documentation.  However, in the table,
 449  * I've given the slot number, the id select line and the Jxx number
 450  * that's printed on the board.  The interrupt pins from the PCI slots
 451  * are wired into 3 interrupt summary registers at 0x804, 0x805 and
 452  * 0x806 ISA.
 453  *
 454  * In the table, -1 means don't assign an IRQ number.  This is usually
 455  * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 456  */
 457 static inline void eb66p_fixup(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 458 {
 459         char irq_tab[5][5] = {
 460                 {16+0, 16+0, 16+5,  16+9, 16+13},       /* IdSel 6,  slot 0, J25 */
 461                 {16+1, 16+1, 16+6, 16+10, 16+14},       /* IdSel 7,  slot 1, J26 */
 462                 {  -1,   -1,   -1,    -1,    -1},       /* IdSel 8,  SIO         */
 463                 {16+2, 16+2, 16+7, 16+11, 16+15},       /* IdSel 9,  slot 2, J27 */
 464                 {16+3, 16+3, 16+8, 16+12,  16+6}        /* IdSel 10, slot 3, J28 */
 465         };
 466         common_fixup(6, 10, 5, irq_tab, 0x398);
 467 }
 468 
 469 
 470 /*
 471  * The AlphaPC64 is very similar to the EB66+ except that its slots
 472  * are numbered differently.  In the code below, I have used slot
 473  * number to refer to the id select line and *not* the slot number
 474  * used in the AlphaPC64 documentation.  However, in the table, I've
 475  * given the slot number, the id select line and the Jxx number that's
 476  * printed on the board.  The interrupt pins from the PCI slots are
 477  * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
 478  * ISA.
 479  *
 480  * In the table, -1 means don't assign an IRQ number.  This is usually
 481  * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 482  */
 483 static inline void cabriolet_fixup(void)
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 484 {
 485         char irq_tab[5][5] = {
 486                 { 16+2, 16+2, 16+7, 16+11, 16+15},      /* IdSel 5,  slot 2, J21 */
 487                 { 16+0, 16+0, 16+5,  16+9, 16+13},      /* IdSel 6,  slot 0, J19 */
 488                 { 16+1, 16+1, 16+6, 16+10, 16+14},      /* IdSel 7,  slot 1, J20 */
 489                 {   -1,   -1,   -1,    -1,    -1},      /* IdSel 8,  SIO         */
 490                 { 16+3, 16+3, 16+8, 16+12, 16+16}       /* IdSel 9,  slot 3, J22 */
 491         };
 492         common_fixup(5, 9, 5, irq_tab, 0x398);
 493 }
 494 
 495 
 496 /*
 497  * Fixup configuration for EB66/EB64+ boards.
 498  *
 499  * Both these boards use the same interrupt summary scheme.  There are
 500  * two 8 bit external summary registers as follows:
 501  *
 502  * Summary @ 0x26:
 503  * Bit      Meaning
 504  * 0        Interrupt Line A from slot 0
 505  * 1        Interrupt Line A from slot 1
 506  * 2        Interrupt Line B from slot 0
 507  * 3        Interrupt Line B from slot 1
 508  * 4        Interrupt Line C from slot 0
 509  * 5        Interrupt line from the two ISA PICs
 510  * 6        Tulip (slot 
 511  * 7        NCR SCSI
 512  *
 513  * Summary @ 0x27
 514  * Bit      Meaning
 515  * 0        Interrupt Line C from slot 1
 516  * 1        Interrupt Line D from slot 0
 517  * 2        Interrupt Line D from slot 1
 518  * 3        RAZ
 519  * 4        RAZ
 520  * 5        RAZ
 521  * 6        RAZ
 522  * 7        RAZ
 523  *
 524  * The device to slot mapping looks like:
 525  *
 526  * Slot     Device
 527  *  5       NCR SCSI controller
 528  *  6       PCI on board slot 0
 529  *  7       PCI on board slot 1
 530  *  8       Intel SIO PCI-ISA bridge chip
 531  *  9       Tulip - DECchip 21040 ethernet controller
 532  *   
 533  *
 534  * This two layered interrupt approach means that we allocate IRQ 16 and 
 535  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 536  * comes in on.  This makes interrupt processing much easier.
 537  */
 538 static inline void eb66_and_eb64p_fixup(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 539 {
 540         char irq_tab[5][5] = {
 541                 {16+7, 16+7, 16+7, 16+7,  16+7},        /* IdSel 5,  slot ?, ?? */
 542                 {16+0, 16+0, 16+2, 16+4,  16+9},        /* IdSel 6,  slot ?, ?? */
 543                 {16+1, 16+1, 16+3, 16+8, 16+10},        /* IdSel 7,  slot ?, ?? */
 544                 {  -1,   -1,   -1,   -1,    -1},        /* IdSel 8,  SIO */
 545                 {16+6, 16+6, 16+6, 16+6,  16+6},        /* IdSel 9,  TULIP */
 546         };
 547         common_fixup(5, 9, 5, irq_tab, 0);
 548 }
 549 
 550 
 551 /*
 552  * Fixup configuration for Noname (AXPpci33) and Avanti (AlphaStation 240).
 553  */
 554 static inline void avanti_and_noname_fixup(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 555 {
 556         struct pci_dev *dev;
 557         /*
 558          * The Noname board has 5 PCI slots with each of the 4
 559          * interrupt pins routed to different pins on the PCI/ISA
 560          * bridge (PIRQ0-PIRQ3).  The table below is based on
 561          * information available at:
 562          *
 563          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 564          *
 565          * I have no information on the Avanti interrupt routing, but
 566          * the routing seems to be identical to the Noname except
 567          * that the Avanti has an additional slot whose routing I'm
 568          * unsure of.
 569          *
 570          * pirq_tab[0] is a fake entry to deal with old PCI boards
 571          * that have the interrupt pin number hardwired to 0 (meaning
 572          * that they use the default INTA line, if they are interrupt
 573          * driven at all).
 574          */
 575         static const char pirq_tab[][5] = {
 576                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */ 
 577                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 578                 { 2,  2, -1, -1, -1}, /* idsel  8 (slot closest to ISA) */
 579                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 580                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 581                 { 0,  0,  2,  1,  0}, /* idsel 11 (slot furthest from ISA) KN25_PCI_SLOT0 */
 582                 { 1,  1,  0,  2,  1}, /* idsel 12 (middle slot) KN25_PCI_SLOT1 */
 583 #ifdef CONFIG_ALPHA_AVANTI
 584                 { 1,  1, -1, -1, -1}, /* idsel 13 KN25_PCI_SLOT2 */
 585 #endif /* CONFIG_ALPHA_AVANTI */
 586         };
 587         /*
 588          * route_tab selects irq routing in PCI/ISA bridge so that:
 589          *              PIRQ0 -> irq 15
 590          *              PIRQ1 -> irq  9
 591          *              PIRQ2 -> irq 10
 592          *              PIRQ3 -> irq 11
 593          *
 594          * This probably ought to be configurable via MILO.  For
 595          * example, sound boards seem to like using IRQ 9.
 596          */
 597         const unsigned int route_tab = 0x0b0a090f;
 598         unsigned int level_bits;
 599         unsigned char pin;
 600         int pirq;
 601 
 602         pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
 603 
 604         /*
 605          * Go through all devices, fixing up irqs as we see fit:
 606          */
 607         level_bits = 0;
 608         for (dev = pci_devices; dev; dev = dev->next) {
 609                 dev->irq = 0;
 610                 if (dev->bus->number != 0 ||
 611                     PCI_SLOT(dev->devfn) < 6 ||
 612                     PCI_SLOT(dev->devfn) >= 6 + sizeof(pirq_tab)/sizeof(pirq_tab[0]))
 613                 {
 614                         printk("bios32.avanti_and_noname_fixup: no dev on bus %d, slot %d!!\n",
 615                                dev->bus->number, PCI_SLOT(dev->devfn));
 616                         continue;
 617                 }
 618                 pcibios_read_config_byte(dev->bus->number, dev->devfn,
 619                                          PCI_INTERRUPT_PIN, &pin);
 620                 pirq = pirq_tab[PCI_SLOT(dev->devfn) - 6][pin];
 621                 if (pirq < 0) {
 622                         continue;
 623                 }
 624                 /*
 625                  * if its a VGA, enable its BIOS ROM at C0000
 626                  */
 627                 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
 628                         pcibios_write_config_dword(dev->bus->number, dev->devfn,
 629                                                    PCI_ROM_ADDRESS,
 630                                                    0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
 631                 }
 632                 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
 633                         continue; /* for now, displays get no IRQ */
 634                 }
 635                 dev->irq = (route_tab >> (8 * pirq)) & 0xff;
 636 
 637                 /* must set the PCI IRQs to level triggered */
 638                 level_bits |= (1 << dev->irq);
 639 
 640 #if PCI_MODIFY
 641                 /* tell the device: */
 642                 pcibios_write_config_byte(dev->bus->number, dev->devfn,
 643                                           PCI_INTERRUPT_LINE, dev->irq);
 644 #endif
 645         }
 646         /* now, set any level-triggered IRQs */
 647         if (level_bits)
 648                 outw(level_bits, 0x4d0);
 649 
 650 
 651 #if PCI_MODIFY
 652         {
 653                 unsigned char hostid;
 654                 /*
 655                  * SRM console version X3.9 seems to reset the SCSI
 656                  * host-id to 0 no matter what console environment
 657                  * variable pka0_host_id is set to.  Thus, if the
 658                  * host-id reads out as a zero, we set it to 7.  The
 659                  * SCSI controller is on the motherboard on bus 0,
 660                  * slot 6
 661                  */
 662                 if (pcibios_read_config_byte(0, PCI_DEVFN(6, 0), 0x84, &hostid)
 663                     == PCIBIOS_SUCCESSFUL && (hostid == 0))
 664                 {
 665                         pcibios_write_config_byte(0, PCI_DEVFN(6, 0),
 666                                                   0x84, 7);
 667                 }
 668         }
 669 #endif /* !PCI_MODIFY */
 670 
 671         enable_ide(0x26e);
 672 }
 673 
 674 
 675 #ifdef CONFIG_TGA_CONSOLE
 676 extern void tga_console_init(void);
 677 #endif /* CONFIG_TGA_CONSOLE */
 678 
 679 unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
     /* [previous][next][first][last][top][bottom][index][help] */
 680 {
 681 #if PCI_MODIFY
 682         /*
 683          * Scan the tree, allocating PCI memory and I/O space.
 684          */
 685         layout_bus(&pci_root);
 686 #endif
 687         
 688         /*
 689          * Now is the time to do all those dirty little deeds...
 690          */
 691 #if defined(CONFIG_ALPHA_NONAME) || defined(CONFIG_ALPHA_AVANTI)
 692         avanti_and_noname_fixup();
 693 #elif defined(CONFIG_ALPHA_CABRIOLET)
 694         cabriolet_fixup();
 695 #elif defined(CONFIG_ALPHA_EB66P)
 696         eb66p_fixup();
 697 #elif defined(CONFIG_ALPHA_EB66)
 698         eb66_and_eb64p_fixup();
 699 #elif defined(CONFIG_ALPHA_EB64P)
 700         eb66_and_eb64p_fixup();
 701 #else
 702 #       error You must tell me what kind of platform you want.
 703 #endif
 704 
 705 #ifdef CONFIG_TGA_CONSOLE
 706         tga_console_init();
 707 #endif /* CONFIG_TGA_CONSOLE */
 708 
 709         return mem_start;
 710 }
 711 
 712 
 713 const char *pcibios_strerror (int error)
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 714 {
 715         static char buf[80];
 716 
 717         switch (error) {
 718                 case PCIBIOS_SUCCESSFUL:
 719                         return "SUCCESSFUL";
 720 
 721                 case PCIBIOS_FUNC_NOT_SUPPORTED:
 722                         return "FUNC_NOT_SUPPORTED";
 723 
 724                 case PCIBIOS_BAD_VENDOR_ID:
 725                         return "SUCCESSFUL";
 726 
 727                 case PCIBIOS_DEVICE_NOT_FOUND:
 728                         return "DEVICE_NOT_FOUND";
 729 
 730                 case PCIBIOS_BAD_REGISTER_NUMBER:
 731                         return "BAD_REGISTER_NUMBER";
 732 
 733                 default:
 734                         sprintf (buf, "UNKNOWN RETURN 0x%x", error);
 735                         return buf;
 736         }
 737 }
 738 
 739 #endif /* CONFIG_PCI */

/* [previous][next][first][last][top][bottom][index][help] */