root/arch/i386/kernel/smp.c

/* [previous][next][first][last][top][bottom][index][help] */

DEFINITIONS

This source file includes following definitions.
  1. mpf_checksum
  2. mpc_family
  3. smp_read_mpc
  4. smp_scan_config
  5. install_trampoline
  6. smp_alloc_memory
  7. get_kernel_stack
  8. smp_store_cpu_info
  9. smp_commence
  10. smp_callin
  11. smp_boot_cpus
  12. smp_message_pass
  13. smp_invalidate
  14. smp_reschedule_irq
  15. smp_message_irq

   1 /*
   2  *      Intel MP v1.1 specification support routines for multi-pentium 
   3  *      hosts.
   4  *
   5  *      (c) 1995 Alan Cox, CymruNET Ltd  <alan@cymru.net>
   6  *      Supported by Caldera http://www.caldera.com.
   7  *      Much of the core SMP work is based on previous work by Thomas Radke, to
   8  *      whom a great many thanks are extended.
   9  *
  10  *      This code is released under the GNU public license version 2 or
  11  *      later.
  12  *
  13  *      Fixes
  14  *              Felix Koop      :       NR_CPUS used properly
  15  *              Jose Renau      :       Handle single CPU case.
  16  *              Alan Cox        :       By repeated request 8) - Total BogoMIP report.
  17  *              Greg Wright     :       Fix for kernel stacks panic.
  18  *
  19  */
  20 
  21 #include <linux/kernel.h>
  22 #include <linux/string.h>
  23 #include <linux/config.h>
  24 #include <linux/timer.h>
  25 #include <linux/sched.h>
  26 #include <linux/mm.h>
  27 #include <linux/kernel_stat.h>
  28 #include <linux/delay.h>
  29 #include <asm/i82489.h>
  30 #include <linux/smp.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/bitops.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/smp.h>
  35 
  36 extern void *vremap(unsigned long offset, unsigned long size);  /* Linus hasnt put this in the headers yet */
  37 
  38 static int smp_found_config=0;                          /* Have we found an SMP box                             */
  39 
  40 unsigned long cpu_present_map = 0;                      /* Bitmask of existing CPU's                            */
  41 int smp_num_cpus;                                       /* Total count of live CPU's                            */
  42 int smp_threads_ready=0;                                /* Set when the idlers are all forked                   */
  43 volatile unsigned long cpu_callin_map[NR_CPUS] = {0,};  /* We always use 0 the rest is ready for parallel delivery */
  44 volatile unsigned long smp_invalidate_needed;           /* Used for the invalidate map thats also checked in the spinlock */
  45 struct cpuinfo_x86 cpu_data[NR_CPUS];                   /* Per cpu bogomips and other parameters                */
  46 static unsigned int num_processors = 1;                 /* Internal processor count                             */
  47 static unsigned long io_apic_addr = 0;                  /* Address of the I/O apic (not yet used)               */
  48 unsigned char boot_cpu_id = 0;                          /* Processor that is doing the boot up                  */
  49 static unsigned char *kstack_base,*kstack_end;          /* Kernel stack list pointers                           */
  50 static int smp_activated = 0;                           /* Tripped once we need to start cross invalidating     */
  51 static volatile int smp_commenced=0;                    /* Tripped when we start scheduling                     */
  52 static unsigned char nlong=0;                           /* Apparent value for boot CPU                          */
  53 unsigned char *apic_reg=((unsigned char *)&nlong)-0x20; /* Later set to the vremap() of the APIC                */
  54 unsigned long apic_retval;                              /* Just debugging the assembler..                       */
  55 unsigned char *kernel_stacks[NR_CPUS];                  /* Kernel stack pointers for CPU's (debugging)          */
  56 
  57 static volatile unsigned char smp_cpu_in_msg[NR_CPUS];  /* True if this processor is sending an IPI             */
  58 static volatile unsigned long smp_msg_data;             /* IPI data pointer                                     */
  59 static volatile int smp_src_cpu;                        /* IPI sender processor                                 */
  60 static volatile int smp_msg_id;                         /* Message being sent                                   */
  61 
  62 volatile unsigned long kernel_flag=0;                   /* Kernel spinlock                                      */
  63 volatile unsigned char active_kernel_processor = NO_PROC_ID;    /* Processor holding kernel spinlock            */
  64 volatile unsigned long kernel_counter=0;                /* Number of times the processor holds the lock         */
  65 volatile unsigned long syscall_count=0;                 /* Number of times the processor holds the syscall lock */
  66 volatile unsigned long smp_spins=0;                     /* Count of cycles wasted to spinning                   */
  67 
  68 volatile unsigned long ipi_count;                       /* Number of IPI's delivered                            */
  69 
  70 /* 
  71  *      Checksum an MP configuration block.
  72  */
  73  
  74 static int mpf_checksum(unsigned char *mp, int len)
     /* [previous][next][first][last][top][bottom][index][help] */
  75 {
  76         int sum=0;
  77         while(len--)
  78                 sum+=*mp++;
  79         return sum&0xFF;
  80 }
  81 
  82 /*
  83  *      Processor encoding in an MP configuration block
  84  */
  85  
  86 static char *mpc_family(int family,int model)
     /* [previous][next][first][last][top][bottom][index][help] */
  87 {
  88         static char n[32];
  89         static char *model_defs[]=
  90         {
  91                 "80486DX","80486DX",
  92                 "80486SX","80486DX/2 or 80487",
  93                 "80486SL","Intel5X2(tm)",
  94                 "Unknown","Unknown",
  95                 "80486DX/4"
  96         };
  97         if(family==0x5)
  98                 return("Pentium(tm)");
  99         if(family==0x0F && model==0x0F)
 100                 return("Special controller");
 101         if(family==0x04 && model<9)
 102                 return model_defs[model];
 103         sprintf(n,"Unknown CPU [%d:%d]",family, model);
 104         return n;
 105 }
 106 
 107 /*
 108  *      Read the MPC
 109  */
 110 
 111 static int smp_read_mpc(struct mp_config_table *mpc)
     /* [previous][next][first][last][top][bottom][index][help] */
 112 {
 113         char str[16];
 114         int count=sizeof(*mpc);
 115         int apics=0;
 116         unsigned char *mpt=((unsigned char *)mpc)+count;
 117 
 118         if(memcmp(mpc->mpc_signature,MPC_SIGNATURE,4))
 119         {
 120                 printk("Bad signature [%c%c%c%c].\n",
 121                         mpc->mpc_signature[0],
 122                         mpc->mpc_signature[1],
 123                         mpc->mpc_signature[2],
 124                         mpc->mpc_signature[3]);
 125                 return 1;
 126         }
 127         if(mpf_checksum((unsigned char *)mpc,mpc->mpc_length))
 128         {
 129                 printk("Checksum error.\n");
 130                 return 1;
 131         }
 132         if(mpc->mpc_spec!=0x01)
 133         {
 134                 printk("Unsupported version (%d)\n",mpc->mpc_spec);
 135                 return 1;
 136         }
 137         memcpy(str,mpc->mpc_oem,8);
 138         str[8]=0;
 139         printk("OEM ID: %s ",str);
 140         memcpy(str,mpc->mpc_productid,12);
 141         str[12]=0;
 142         printk("Product ID: %s ",str);
 143         printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
 144         
 145         /*
 146          *      Now process the configuration blocks.
 147          */
 148          
 149         while(count<mpc->mpc_length)
 150         {
 151                 switch(*mpt)
 152                 {
 153                         case MP_PROCESSOR:
 154                         {
 155                                 struct mpc_config_processor *m=
 156                                         (struct mpc_config_processor *)mpt;
 157                                 if(m->mpc_cpuflag&CPU_ENABLED)
 158                                 {
 159                                         printk("Processor #%d %s APIC version %d\n",
 160                                                 m->mpc_apicid, 
 161                                                 mpc_family((m->mpc_cpufeature&
 162                                                         CPU_FAMILY_MASK)>>8,
 163                                                         (m->mpc_cpufeature&
 164                                                                 CPU_MODEL_MASK)>>4),
 165                                                 m->mpc_apicver);
 166                                         if(m->mpc_featureflag&(1<<0))
 167                                                 printk("    Floating point unit present.\n");
 168                                         if(m->mpc_featureflag&(1<<7))
 169                                                 printk("    Machine Exception supported.\n");
 170                                         if(m->mpc_featureflag&(1<<8))
 171                                                 printk("    64 bit compare & exchange supported.\n");
 172                                         if(m->mpc_featureflag&(1<<9))
 173                                                 printk("    Internal APIC present.\n");
 174                                         if(m->mpc_cpuflag&CPU_BOOTPROCESSOR)
 175                                         {
 176                                                 printk("    Bootup CPU\n");
 177                                                 boot_cpu_id=m->mpc_apicid;
 178                                                 nlong = boot_cpu_id<<24;        /* Dummy 'self' for bootup */
 179                                         }
 180                                         else    /* Boot CPU already counted */
 181                                                 num_processors++;
 182                                                 
 183                                         if(m->mpc_apicid>NR_CPUS)
 184                                                 printk("Processor #%d unused. (Max %d processors).\n",m->mpc_apicid, NR_CPUS);
 185                                         else                                            
 186                                                 cpu_present_map|=(1<<m->mpc_apicid);
 187                                 }
 188                                 mpt+=sizeof(*m);
 189                                 count+=sizeof(*m);
 190                                 break;
 191                         }
 192                         case MP_BUS:
 193                         {
 194                                 struct mpc_config_bus *m=
 195                                         (struct mpc_config_bus *)mpt;
 196                                 memcpy(str,m->mpc_bustype,6);
 197                                 str[6]=0;
 198                                 printk("Bus #%d is %s\n",
 199                                         m->mpc_busid,
 200                                         str);
 201                                 mpt+=sizeof(*m);
 202                                 count+=sizeof(*m);
 203                                 break; 
 204                         }
 205                         case MP_IOAPIC:
 206                         {
 207                                 struct mpc_config_ioapic *m=
 208                                         (struct mpc_config_ioapic *)mpt;
 209                                 if(m->mpc_flags&MPC_APIC_USABLE)
 210                                 {
 211                                         apics++;
 212                                         printk("I/O APIC #%d Version %d at 0x%lX.\n",
 213                                                 m->mpc_apicid,m->mpc_apicver,
 214                                                 m->mpc_apicaddr);
 215                                         io_apic_addr = m->mpc_apicaddr;
 216                                 }
 217                                 mpt+=sizeof(*m);
 218                                 count+=sizeof(*m); 
 219                                 break;
 220                         }
 221                         case MP_INTSRC:
 222                         {
 223                                 struct mpc_config_intsrc *m=
 224                                         (struct mpc_config_intsrc *)mpt;
 225                                 
 226                                 mpt+=sizeof(*m);
 227                                 count+=sizeof(*m);
 228                                 break;
 229                         }
 230                         case MP_LINTSRC:
 231                         {
 232                                 struct mpc_config_intlocal *m=
 233                                         (struct mpc_config_intlocal *)mpt;
 234                                 mpt+=sizeof(*m);
 235                                 count+=sizeof(*m);
 236                                 break;
 237                         }
 238                 }
 239         }
 240         if(apics>1)
 241                 printk("Warning: Multiple APIC's not supported.\n");
 242         return num_processors;                          
 243 }
 244 
 245 /*
 246  *      Scan the memory blocks for an SMP configuration block.
 247  */
 248  
 249 void smp_scan_config(unsigned long base, unsigned long length)
     /* [previous][next][first][last][top][bottom][index][help] */
 250 {
 251         unsigned long *bp=(unsigned long *)base;
 252         struct intel_mp_floating *mpf;
 253         
 254 /*      printk("Scan SMP from %p for %ld bytes.\n",
 255                 bp,length);*/
 256         if(sizeof(*mpf)!=16)
 257                 printk("Error: MPF size\n");
 258         
 259         while(length>0)
 260         {
 261                 if(*bp==SMP_MAGIC_IDENT)
 262                 {
 263                         mpf=(struct intel_mp_floating *)bp;
 264                         if(mpf->mpf_length==1 && 
 265                                 !mpf_checksum((unsigned char *)bp,16) &&
 266                                 mpf->mpf_specification==1)
 267                         {
 268                                 printk("Intel multiprocessing (MPv1.1) available.\n");
 269                                 if(mpf->mpf_feature2&(1<<7))
 270                                         printk("    IMCR and PIC mode supported.\n");
 271                                 smp_found_config=1;
 272                                 /*
 273                                  *      Now see if we need to read further.
 274                                  */
 275                                 if(mpf->mpf_feature1!=0)
 276                                 {
 277                                         num_processors=2;
 278                                         printk("I/O APIC at 0xFEC00000.\n");
 279                                         printk("Bus#0 is ");
 280                                 }
 281                                 switch(mpf->mpf_feature1)
 282                                 {
 283                                         case 1:
 284                                                 printk("ISA");
 285                                                 break;
 286                                         case 2:
 287                                                 printk("EISA with no IRQ8 chaining");
 288                                                 break;
 289                                         case 3:
 290                                                 printk("EISA");
 291                                                 break;
 292                                         case 4:
 293                                                 printk("MCA");
 294                                                 break;
 295                                         case 5:
 296                                                 printk("ISA\nBus#1 is PCI");
 297                                                 break;
 298                                         case 6:
 299                                                 printk("EISA\nBus #1 is PCI");
 300                                                 break;
 301                                         case 7:
 302                                                 printk("MCA\nBus #1 is PCI");
 303                                                 break;
 304                                         case 0:
 305                                                 break;
 306                                         default:
 307                                                 printk("???\nUnknown standard configuration %d\n",
 308                                                         mpf->mpf_feature1);
 309                                                 return;
 310                                 }
 311                                 /*
 312                                  *      Read the physical hardware table. If there isn't one
 313                                  *      the processors present are 0 and 1.
 314                                  */
 315                                 if(mpf->mpf_physptr)
 316                                         smp_read_mpc((void *)mpf->mpf_physptr);
 317                                 else
 318                                         cpu_present_map=3;
 319                                 printk("Processors: %d\n", num_processors);
 320                         }
 321                 }
 322                 bp+=4;
 323                 length-=16;
 324         }
 325 }
 326 
 327 /*
 328  *      Trampoline 80x86 program as an array.
 329  */
 330 
 331 static unsigned char trampoline_data[]={ 
 332 #include  "trampoline.hex"
 333 };
 334 
 335 /*
 336  *      Currently trivial. Write the real->protected mode
 337  *      bootstrap into the page concerned. The caller
 338  *      has made sure its suitably aligned.
 339  */
 340  
 341 static void install_trampoline(unsigned char *mp)
     /* [previous][next][first][last][top][bottom][index][help] */
 342 {
 343         memcpy(mp,trampoline_data,sizeof(trampoline_data));
 344 }
 345 
 346 /*
 347  *      We are called very early to get the low memory for the trampoline/kernel stacks
 348  *      This has to be done by mm/init.c to parcel us out nice low memory. We allocate
 349  *      the kernel stacks at 4K, 8K, 12K... currently (0-03FF is preserved for SMM and
 350  *      other things).
 351  */
 352  
 353 unsigned long smp_alloc_memory(unsigned long mem_base)
     /* [previous][next][first][last][top][bottom][index][help] */
 354 {
 355         int size=(num_processors-1)*PAGE_SIZE;          /* Number of stacks needed */
 356         /*
 357          *      Our stacks have to be below the 1Mb line, and mem_base on entry
 358          *      is 4K aligned.
 359          */
 360          
 361         if(mem_base+size>=0x9F000)
 362                 panic("smp_alloc_memory: Insufficient low memory for kernel stacks.\n");
 363         kstack_base=(void *)mem_base;
 364         mem_base+=size;
 365         kstack_end=(void *)mem_base;
 366         return mem_base;
 367 }
 368         
 369 /*
 370  *      Hand out stacks one at a time.
 371  */
 372  
 373 static void *get_kernel_stack(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 374 {
 375         void *stack=kstack_base;
 376         if(kstack_base>=kstack_end)
 377                 return NULL;
 378         kstack_base+=PAGE_SIZE;
 379         return stack;
 380 }
 381 
 382 
 383 /*
 384  *      The bootstrap kernel entry code has set these up. Save them for
 385  *      a given CPU
 386  */
 387  
 388 void smp_store_cpu_info(int id)
     /* [previous][next][first][last][top][bottom][index][help] */
 389 {
 390         struct cpuinfo_x86 *c=&cpu_data[id];
 391         c->hard_math=hard_math;                 /* Always assumed same currently */
 392         c->x86=x86;
 393         c->x86_model=x86_model;
 394         c->x86_mask=x86_mask;
 395         c->x86_capability=x86_capability;
 396         c->fdiv_bug=fdiv_bug;
 397         c->wp_works_ok=wp_works_ok;             /* Always assumed the same currently */
 398         c->hlt_works_ok=hlt_works_ok;
 399         c->udelay_val=loops_per_sec;
 400         strcpy(c->x86_vendor_id, x86_vendor_id);
 401 }
 402 
 403 /*
 404  *      Architecture specific routine called by the kernel just before init is
 405  *      fired off. This allows the BP to have everything in order [we hope].
 406  *      At the end of this all the AP's will hit the system scheduling and off
 407  *      we go. Each AP will load the system gdt's and jump through the kernel
 408  *      init into idle(). At this point the scheduler will one day take over 
 409  *      and give them jobs to do. smp_callin is a standard routine
 410  *      we use to track CPU's as they power up.
 411  */
 412 
 413 void smp_commence(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 414 {
 415         /*
 416          *      Lets the callin's below out of their loop.
 417          */
 418         smp_commenced=1;
 419 }
 420  
 421 void smp_callin(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 422 {
 423         int cpuid=GET_APIC_ID(apic_read(APIC_ID));
 424         unsigned long l;
 425         /*
 426          *      Activate our APIC
 427          */
 428          
 429 /*      printk("CALLIN %d\n",smp_processor_id());*/
 430         l=apic_read(APIC_SPIV);
 431         l|=(1<<8);              /* Enable */
 432         apic_write(APIC_SPIV,l);
 433         sti();
 434         /*
 435          *      Get our bogomips.
 436          */     
 437         calibrate_delay();
 438         /*
 439          *      Save our processor parameters
 440          */
 441         smp_store_cpu_info(cpuid);
 442         /*
 443          *      Allow the master to continue.
 444          */     
 445         set_bit(cpuid, &cpu_callin_map[0]);
 446         /*
 447          *      Until we are ready for SMP scheduling
 448          */
 449         load_ldt(0);
 450 /*      printk("Testing faulting...\n");
 451         *(long *)0=1;            OOPS... */
 452         local_invalidate();
 453         while(!smp_commenced);
 454         local_invalidate();
 455 /*      printk("Commenced..\n");*/
 456         
 457         /* This assumes the processor id's are consecutive 0..n-1 -  FIXME */
 458         load_TR(cpuid);
 459 /*      while(1);*/
 460 }
 461 
 462 /*
 463  *      Cycle through the processors sending pentium IPI's to boot each.
 464  */
 465  
 466 void smp_boot_cpus(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 467 {
 468         int i=0;
 469         int cpucount=0;
 470         void *stack;
 471         extern unsigned long init_user_stack[];
 472         
 473         /*
 474          *      Map the local APIC into kernel space
 475          */
 476         
 477         apic_reg = vremap(0xFEE00000,4096);
 478         
 479         
 480         if(apic_reg == NULL)
 481                 panic("Unable to map local apic.\n");
 482                 
 483         /*
 484          *      Now scan the cpu present map and fire up anything we find.
 485          */
 486          
 487          
 488         kernel_stacks[boot_cpu_id]=(void *)init_user_stack;     /* Set up for boot processor first */
 489 
 490         smp_store_cpu_info(boot_cpu_id);                        /* Final full version of the data */
 491         
 492         active_kernel_processor=boot_cpu_id;
 493                 
 494         for(i=0;i<NR_CPUS;i++)
 495         {
 496                 if((cpu_present_map&(1<<i)) && i!=boot_cpu_id)          /* Rebooting yourself is a bad move */
 497                 {
 498                         unsigned long cfg;
 499                         int timeout;
 500                         
 501                         /*
 502                          *      We need a kernel stack for each processor.
 503                          */
 504                         
 505                         stack=get_kernel_stack();       /* We allocated these earlier */
 506                         if(stack==NULL)
 507                                 panic("No memory for processor stacks.\n");
 508                         kernel_stacks[i]=stack;
 509                         install_trampoline(stack);
 510                         
 511                         printk("Booting processor %d stack %p: ",i,stack);                      /* So we set whats up   */
 512                                 
 513                         /*
 514                          *      Enable the local APIC
 515                          */
 516                          
 517                         cfg=apic_read(APIC_SPIV);
 518                         cfg|=(1<<8);            /* Enable APIC */
 519                         apic_write(APIC_SPIV,cfg);
 520                         
 521                         /*
 522                          *      This gunge sends an IPI (Inter Processor Interrupt) to the
 523                          *      processor we wish to wake. When the startup IPI is received
 524                          *      the target CPU does a real mode jump to the stack base.
 525                          */
 526                         
 527                         cfg=apic_read(APIC_ICR2);
 528                         cfg&=0x00FFFFFF;
 529                         apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(i));                      /* Target chip          */
 530                         cfg=apic_read(APIC_ICR);
 531                         cfg&=~0xFDFFF   ;                                                       /* Clear bits           */
 532                         cfg|=APIC_DEST_FIELD|APIC_DEST_DM_STARTUP|(((unsigned long)stack)>>12); /* Boot on the stack    */              
 533                         apic_write(APIC_ICR, cfg);                                              /* Kick the second      */
 534                         udelay(10);                                                             /* Masses of time       */
 535                         cfg=apic_read(APIC_ESR);
 536                         if(cfg&4)               /* Send accept error */
 537                                 printk("Processor refused startup request.\n");
 538                         else
 539                         {
 540                                 for(timeout=0;timeout<50000;timeout++)
 541                                 {
 542                                         if(cpu_callin_map[0]&(1<<i))
 543                                                 break;                          /* It has booted */
 544                                         udelay(100);                            /* Wait 5s total for a response */
 545                                 }
 546                                 if(cpu_callin_map[0]&(1<<i))
 547                                         cpucount++;
 548                                 else
 549                                 {
 550                                         /*
 551                                          *      At this point we should set up a BIOS warm start and try
 552                                          *      a RESTART IPI. The 486+82489 MP pair don't support STARTUP IPI's
 553                                          */
 554                                         if(*((unsigned char *)8192)==0xA5)
 555                                                 printk("Stuck ??\n");
 556                                         else
 557                                                 printk("Not responding.\n");
 558                                         cpu_present_map&=~(1<<i);
 559                                 }
 560                         }
 561                 }
 562         }
 563         /*
 564          *      Allow the user to impress friends.
 565          */
 566         if(cpucount==0)
 567         {
 568                 printk("Error: only one processor found.\n");
 569                 cpu_present_map=(1<<smp_processor_id());
 570         }
 571         else
 572         {
 573                 unsigned long bogosum=0;
 574                 for(i=0;i<32;i++)
 575                 {
 576                         if(cpu_present_map&(1<<i))
 577                                 bogosum+=cpu_data[i].udelay_val;
 578                 }
 579                 printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 
 580                         cpucount+1, 
 581                         (bogosum+2500)/500000,
 582                         ((bogosum+2500)/5000)%100);
 583                 smp_activated=1;
 584                 smp_num_cpus=cpucount+1;
 585         }
 586 }
 587 
 588 
 589 /*
 590  *      A non wait message cannot pass data or cpu source info. This current setup
 591  *      is only safe because the kernel lock owner is the only person who can send a message.
 592  *
 593  *      Wrapping this whole block in a spinlock is not the safe answer either. A processor may
 594  *      get stuck with irq's off waiting to send a message and thus not replying to the person
 595  *      spinning for a reply....
 596  *
 597  *      In the end invalidate ought to be the NMI and a very very short function (to avoid the old
 598  *      IDE disk problems), and other messages sent with IRQ's enabled in a civilised fashion. That
 599  *      will also boost performance.
 600  */
 601  
 602 void smp_message_pass(int target, int msg, unsigned long data, int wait)
     /* [previous][next][first][last][top][bottom][index][help] */
 603 {
 604         unsigned long cfg;
 605         unsigned long target_map;
 606         int p=smp_processor_id();
 607         int irq=0x2d;                                                           /* IRQ 13 */
 608         int ct=0;
 609         static volatile int message_cpu = NO_PROC_ID;
 610 
 611         /*
 612          *      During boot up send no messages
 613          */
 614          
 615         if(!smp_activated || !smp_commenced)
 616                 return;
 617                 
 618         
 619         /*
 620          *      Skip the reschedule if we are waiting to clear a
 621          *      message at this time. The reschedule cannot wait
 622          *      but is not critical.
 623          */
 624         
 625         if(msg==MSG_RESCHEDULE)                                                 /* Reschedules we do via trap 0x30 */
 626         {
 627                 irq=0x30;
 628                 if(smp_cpu_in_msg[p])
 629                         return;
 630         }
 631 
 632         /*
 633          *      Sanity check we don't re-enter this across CPU's. Only the kernel
 634          *      lock holder may send messages. For a STOP_CPU we are bringing the
 635          *      entire box to the fastest halt we can.. 
 636          */
 637          
 638         if(message_cpu!=NO_PROC_ID && msg!=MSG_STOP_CPU)
 639         {
 640                 panic("CPU #%d: Message pass %d but pass in progress by %d of %d\n",
 641                         smp_processor_id(),msg,message_cpu, smp_msg_id);
 642         }
 643         message_cpu=smp_processor_id();
 644         
 645 
 646         /*
 647          *      We are busy
 648          */
 649                 
 650         smp_cpu_in_msg[p]++;
 651         
 652         /*
 653          *      Reschedule is currently special
 654          */
 655          
 656         if(msg!=MSG_RESCHEDULE)
 657         {
 658                 smp_src_cpu=p;
 659                 smp_msg_id=msg;
 660                 smp_msg_data=data;
 661         }
 662         
 663 /*      printk("SMP message pass #%d to %d of %d\n",
 664                 p, msg, target);*/
 665         
 666         /*
 667          *      Wait for the APIC to become ready - this should never occur. Its
 668          *      a debugging check really.
 669          */
 670          
 671         while(ct<1000)
 672         {
 673                 cfg=apic_read(APIC_ICR);
 674                 if(!(cfg&(1<<12)))
 675                         break;
 676                 ct++;
 677                 udelay(10);
 678         }
 679         
 680         /*
 681          *      Just pray... there is nothing more we can do
 682          */
 683          
 684         if(ct==1000)
 685                 printk("CPU #%d: previous IPI still not cleared after 10mS", smp_processor_id());
 686                 
 687         /*
 688          *      Program the APIC to deliver the IPI
 689          */
 690          
 691         cfg=apic_read(APIC_ICR2);
 692         cfg&=0x00FFFFFF;
 693         apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(target));                 /* Target chip                  */
 694         cfg=apic_read(APIC_ICR);
 695         cfg&=~0xFDFFF;                                                          /* Clear bits                   */
 696         cfg|=APIC_DEST_FIELD|APIC_DEST_DM_FIXED|irq;                            /* Send an IRQ 13               */              
 697 
 698         /*
 699          *      Set the target requirement
 700          */
 701          
 702         if(target==MSG_ALL_BUT_SELF)
 703         {
 704                 cfg|=APIC_DEST_ALLBUT;
 705                 target_map=cpu_present_map;
 706                 cpu_callin_map[0]=(1<<smp_src_cpu);
 707         }
 708         else if(target==MSG_ALL)
 709         {
 710                 cfg|=APIC_DEST_ALLINC;
 711                 target_map=cpu_present_map;
 712                 cpu_callin_map[0]=0;
 713         }
 714         else
 715         {
 716                 target_map=(1<<target);
 717                 cpu_callin_map[0]=0;
 718         }
 719                 
 720         /*
 721          *      Send the IPI. The write to APIC_ICR fires this off.
 722          */
 723          
 724         apic_write(APIC_ICR, cfg);      
 725         
 726         /*
 727          *      Spin waiting for completion
 728          */
 729          
 730         switch(wait)
 731         {
 732                 case 1:
 733                         while(cpu_callin_map[0]!=target_map);           /* Spin on the pass             */
 734                         break;
 735                 case 2:
 736                         while(smp_invalidate_needed);                   /* Wait for invalidate map to clear */
 737                         break;
 738         }
 739         
 740         /*
 741          *      Record our completion
 742          */
 743          
 744         smp_cpu_in_msg[p]--;
 745         message_cpu=NO_PROC_ID;
 746 }
 747 
 748 /*
 749  *      This is fraught with deadlocks. Linus does an invalidate at a whim
 750  *      even with IRQ's off. We have to avoid a pair of crossing invalidates
 751  *      or we are doomed.  See the notes about smp_message_pass.
 752  */
 753  
 754 void smp_invalidate(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 755 {
 756         unsigned long flags;
 757         if(smp_activated && smp_processor_id()!=active_kernel_processor)
 758                 panic("CPU #%d:Attempted invalidate IPI when not AKP(=%d)\n",smp_processor_id(),active_kernel_processor);
 759 /*      printk("SMI-");*/
 760         
 761         /*
 762          *      The assignment is safe because its volatile so the compiler cannot reorder it,
 763          *      because the i586 has strict memory ordering and because only the kernel lock holder
 764          *      may issue an invalidate. If you break any one of those three change this to an atomic
 765          *      bus locked or.
 766          */
 767         
 768         smp_invalidate_needed=cpu_present_map&~(1<<smp_processor_id());
 769         
 770         /*
 771          *      Processors spinning on the lock will see this IRQ late. The smp_invalidate_needed map will
 772          *      ensure they dont do a spurious invalidate or miss one.
 773          */
 774          
 775         save_flags(flags);
 776         cli();
 777         smp_message_pass(MSG_ALL_BUT_SELF, MSG_INVALIDATE_TLB, 0L, 2);
 778         
 779         /*
 780          *      Flush the local TLB
 781          */
 782          
 783         local_invalidate();
 784         
 785         restore_flags(flags);
 786         
 787         /*
 788          *      Completed.
 789          */
 790          
 791 /*      printk("SMID\n");*/
 792 }
 793 
 794 /*      
 795  *      Reschedule call back
 796  */
 797 
 798 void smp_reschedule_irq(int cpl, struct pt_regs *regs)
     /* [previous][next][first][last][top][bottom][index][help] */
 799 {
 800         static int ct=0;
 801         if(ct==0)
 802         {
 803                 printk("Beginning scheduling on CPU#%d\n",smp_processor_id());
 804                 ct=1;
 805         }
 806         
 807         if(smp_processor_id()!=active_kernel_processor)
 808                 panic("SMP Reschedule on CPU #%d, but #%d is active.\n",
 809                         smp_processor_id(), active_kernel_processor);
 810         /*
 811          *      Update resource usage on the slave timer tick.
 812          */
 813                         
 814         if (user_mode(regs)) 
 815         {
 816                 current->utime++;
 817                 if (current->pid) 
 818                 {
 819                         if (current->priority < 15)
 820                                 kstat.cpu_nice++;
 821                         else
 822                                 kstat.cpu_user++;
 823                 }
 824                 /* Update ITIMER_VIRT for current task if not in a system call */
 825                 if (current->it_virt_value && !(--current->it_virt_value)) {
 826                         current->it_virt_value = current->it_virt_incr;
 827                         send_sig(SIGVTALRM,current,1);
 828                 }
 829         } else {
 830                 current->stime++;
 831                 if(current->pid)
 832                         kstat.cpu_system++;
 833 #ifdef CONFIG_PROFILE
 834                 if (prof_buffer && current->pid) {
 835                         extern int _stext;
 836                         unsigned long eip = regs->eip - (unsigned long) &_stext;
 837                         eip >>= CONFIG_PROFILE_SHIFT;
 838                         if (eip < prof_len)
 839                                 prof_buffer[eip]++;
 840                 }
 841 #endif
 842         }
 843         /*
 844          * check the cpu time limit on the process.
 845          */
 846         if ((current->rlim[RLIMIT_CPU].rlim_max != RLIM_INFINITY) &&
 847             (((current->stime + current->utime) / HZ) >= current->rlim[RLIMIT_CPU].rlim_max))
 848                 send_sig(SIGKILL, current, 1);
 849         if ((current->rlim[RLIMIT_CPU].rlim_cur != RLIM_INFINITY) &&
 850             (((current->stime + current->utime) % HZ) == 0)) {
 851                 unsigned long psecs = (current->stime + current->utime) / HZ;
 852                 /* send when equal */
 853                 if (psecs == current->rlim[RLIMIT_CPU].rlim_cur)
 854                         send_sig(SIGXCPU, current, 1);
 855                 /* and every five seconds thereafter. */
 856                 else if ((psecs > current->rlim[RLIMIT_CPU].rlim_cur) &&
 857                         ((psecs - current->rlim[RLIMIT_CPU].rlim_cur) % 5) == 0)
 858                         send_sig(SIGXCPU, current, 1);
 859         }
 860 
 861         /* Update ITIMER_PROF for the current task */
 862         if (current->it_prof_value && !(--current->it_prof_value)) {
 863                 current->it_prof_value = current->it_prof_incr;
 864                 send_sig(SIGPROF,current,1);
 865         }
 866 
 867 
 868         /*
 869          *      Don't reschedule if we are in an interrupt...
 870          *      [This is test code and not needed in the end]
 871          */
 872          
 873 /*      if(intr_count==1)
 874         {*/
 875 
 876                 /*
 877                  *      See if the slave processors need a schedule.
 878                  */
 879 
 880                 if ( 0 > --current->counter || current->pid == 0) 
 881                 {
 882                         current->counter = 0;
 883                         need_resched=1;
 884                 }
 885 /*      }*/
 886 
 887         /*
 888          *      Clear the IPI
 889          */
 890         apic_read(APIC_SPIV);           /* Dummy read */
 891         apic_write(APIC_EOI, 0);        /* Docs say use 0 for future compatibility */
 892 }       
 893 
 894 /*
 895  *      Message call back.
 896  */
 897  
 898 void smp_message_irq(int cpl, struct pt_regs *regs)
     /* [previous][next][first][last][top][bottom][index][help] */
 899 {
 900         int i=smp_processor_id();
 901 /*      static int n=0;
 902         if(n++<NR_CPUS)
 903                 printk("IPI %d->%d(%d,%ld)\n",smp_src_cpu,i,smp_msg_id,smp_msg_data);*/
 904         switch(smp_msg_id)
 905         {
 906                 case 0: /* IRQ 13 testing - boring */
 907                         return;
 908                         
 909                 /*
 910                  *      A TLB flush is needed.
 911                  */
 912                  
 913                 case MSG_INVALIDATE_TLB:
 914                         if(clear_bit(i,&smp_invalidate_needed))
 915                                 local_invalidate();
 916                         set_bit(i, &cpu_callin_map[0]);
 917                         cpu_callin_map[0]|=1<<smp_processor_id();
 918                         break;
 919                         
 920                 /*
 921                  *      Halt other CPU's for a panic or reboot
 922                  */
 923                 case MSG_STOP_CPU:
 924                         while(1)
 925                         {
 926                                 if(cpu_data[smp_processor_id()].hlt_works_ok)
 927                                         __asm__("hlt");
 928                         }
 929                 default:
 930                         printk("CPU #%d sent invalid cross CPU message to CPU #%d: %X(%lX).\n",
 931                                 smp_src_cpu,smp_processor_id(),smp_msg_id,smp_msg_data);
 932                         break;
 933         }
 934         /*
 935          *      Clear the IPI, so we can receive future IPI's
 936          */
 937          
 938         apic_read(APIC_SPIV);           /* Dummy read */
 939         apic_write(APIC_EOI, 0);        /* Docs say use 0 for future compatibility */
 940 }

/* [previous][next][first][last][top][bottom][index][help] */