arch/ppc/kernel/test.S

/* */
   1 #include "ppc_asm.tmpl"
   2 #include "ppc_defs.h"
   3 
   4 #define SYNC() \
   5         isync; \
   6         sync
   7 
   8 #define BEEF ori r0,r0,0; ori r0,r0,0 ;.word 0 ; .word 0xBEEF
   9 _BEG:   
  10         lis     r7,0xF000               /* To mask upper 4 bits */
  11         
  12 
  13 /* Initialize BAT registers */
  14         lis     r3,OFF_BAT@h
  15         ori     r3,r3,OFF_BAT@l
  16         andc    r3,r3,r7        /* make unmapped address */
  17         lwz     r0,0(r3)
  18 
  19         mtspr   IBAT0U,r0
  20         mtspr   DBAT0U,r0
  21         lwz     r0,4(r3)
  22         mtspr   IBAT0L,r0
  23         mtspr   DBAT0L,r0
  24         
  25         lis     r3,OFF_BAT@h
  26         ori     r3,r3,OFF_BAT@l
  27         andc    r3,r3,r7        /* make unmapped address */
  28         lwz     r0,0(r3)
  29         mtspr   IBAT1U,r0
  30         mtspr   DBAT1U,r0
  31         lwz     r0,4(r3)
  32         mtspr   IBAT1L,r0
  33         mtspr   DBAT1L,r0
  34         
  35         lis     r3,ZERO_BAT@h
  36         ori     r3,r3,ZERO_BAT@l
  37         andc    r3,r3,r7        /* make unmapped address */
  38         lwz     r0,0(r3)
  39         mtspr   IBAT2U,r0
  40         mtspr   DBAT2U,r0
  41         lwz     r0,4(r3)
  42         mtspr   IBAT2L,r0
  43         mtspr   DBAT2L,r0
  44 
  45 
  46         lis     r3,TMP_BAT2@h
  47         ori     r3,r3,TMP_BAT2@l
  48         andc    r3,r3,r7        /* make unmapped address */
  49         lwz     r0,0(r3)
  50         mtspr   IBAT3U,r0
  51         mtspr   DBAT3U,r0
  52         lwz     r0,4(r3)
  53         mtspr   IBAT3L,r0
  54         mtspr   DBAT3L,r0
  55         
  56 
  57 /* Now we can turn on the MMU */
  58 /* set srr1 for rfi */
  59         mfmsr   r3
  60         ori     r3,r3,MSR_DR|MSR_IR|MSR_
  61 
  62         mtspr   SRR1,r3
  63 
  64 /* set srr0 for rfi */
  65         subf    r2, r2, r2
  66 /*      lis     r2,10f@h*/
  67         lis     r2,0
  68         ori     r2,r2,10f@l
  69         mtspr   SRR0,r2
  70 
  71         SYNC()
  72         rfi
  73 
  74         ori r0, r0, 0
  75         ori r0, r0, 0
  76 10:     ori r0, r0, 0
  77         ori r0, r0, 0
  78         BEEF
  79         
  80 #if 0   
  81 /* check bptr to see if it actually has the correct values */
  82 
  83         subf    r2,r2,r2
  84         lis     r2,bptr@h
  85         ori     r2,r2,bptr@l
  86         lwz     r0,0(r2)
  87 
  88 /* rfi to the beef */
  89         mtspr   SRR1,r3
  90         mtspr   SRR0,r2
  91 
  92         SYNC()
  93         rfi     
  94                 
  95 bptr:   ori r0, r0, 0
  96         BEEF
  97         BEEF
  98         BEEF
  99 #endif
 100 _END:
/* */
root/arch/ppc/kernel/test.S
