root/drivers/sound/ad1848.c

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DEFINITIONS

This source file includes following definitions.
  1. ad_read
  2. ad_write
  3. wait_for_calibration
  4. ad_mute
  5. ad_unmute
  6. ad_enter_MCE
  7. ad_leave_MCE
  8. ad1848_set_recmask
  9. change_bits
  10. ad1848_mixer_get
  11. ad1848_mixer_set
  12. ad1848_mixer_reset
  13. ad1848_mixer_ioctl
  14. ad1848_open
  15. ad1848_close
  16. set_speed
  17. set_channels
  18. set_format
  19. ad1848_ioctl
  20. ad1848_output_block
  21. ad1848_start_input
  22. ad1848_prepare_for_IO
  23. ad1848_reset
  24. ad1848_halt
  25. ad1848_halt_input
  26. ad1848_halt_output
  27. ad1848_trigger
  28. ad1848_detect
  29. ad1848_init
  30. ad1848_unload
  31. ad1848_interrupt
  32. check_opl3
  33. probe_ms_sound
  34. attach_ms_sound
  35. unload_ms_sound
  36. probe_pnp_ad1848
  37. attach_pnp_ad1848
  38. unload_pnp_ad1848
  39. ad1848_tmr_start
  40. ad1848_tmr_reprogram
  41. ad1848_tmr_disable
  42. ad1848_tmr_restart
  43. ad1848_tmr_install

   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  *
  16  * Copyright by Hannu Savolainen 1994, 1995
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: 1. Redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer. 2.
  22  * Redistributions in binary form must reproduce the above copyright notice,
  23  * this list of conditions and the following disclaimer in the documentation
  24  * and/or other materials provided with the distribution.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  27  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  30  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  33  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  * Modified:
  39  *  Riccardo Facchetti  24 Mar 1995
  40  *  - Added the Audio Excel DSP 16 initialization routine.
  41  */
  42 
  43 #define DEB(x)
  44 #define DEB1(x)
  45 #include "sound_config.h"
  46 
  47 #if defined(CONFIG_AD1848)
  48 
  49 #include "ad1848_mixer.h"
  50 
  51 typedef struct
  52   {
  53     int             base;
  54     int             irq;
  55     int             dual_dma;   /* 1, when two DMA channels allocated */
  56     unsigned char   MCE_bit;
  57     unsigned char   saved_regs[16];
  58 
  59     int             speed;
  60     unsigned char   speed_bits;
  61     int             channels;
  62     int             audio_format;
  63     unsigned char   format_bits;
  64 
  65     int             xfer_count;
  66     int             irq_mode;
  67     int             intr_active;
  68     int             opened;
  69     char           *chip_name;
  70     int             mode;
  71 #define MD_1848         1
  72 #define MD_4231         2
  73 #define MD_4231A        3
  74 #define MD_1845         4
  75 #define MD_4232         5
  76 
  77     /* Mixer parameters */
  78     int             recmask;
  79     int             supported_devices;
  80     int             supported_rec_devices;
  81     unsigned short  levels[32];
  82     int             dev_no;
  83     volatile unsigned long timer_ticks;
  84     int             timer_running;
  85     int             irq_ok;
  86     sound_os_info  *osp;
  87   }
  88 
  89 ad1848_info;
  90 
  91 static int      nr_ad1848_devs = 0;
  92 static volatile char irq2dev[17] =
  93 {-1, -1, -1, -1, -1, -1, -1, -1,
  94  -1, -1, -1, -1, -1, -1, -1, -1, -1};
  95 
  96 static int      timer_installed = -1;
  97 
  98 static char     mixer2codec[MAX_MIXER_DEV] =
  99 {0};
 100 
 101 static int      ad_format_mask[5 /*devc->mode */ ] =
 102 {
 103   0,
 104   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 105   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 106   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 107   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW      /* AD1845 */
 108 };
 109 
 110 static ad1848_info dev_info[MAX_AUDIO_DEV];
 111 
 112 #define io_Index_Addr(d)        ((d)->base)
 113 #define io_Indexed_Data(d)      ((d)->base+1)
 114 #define io_Status(d)            ((d)->base+2)
 115 #define io_Polled_IO(d)         ((d)->base+3)
 116 
 117 static int      ad1848_open (int dev, int mode);
 118 static void     ad1848_close (int dev);
 119 static int      ad1848_ioctl (int dev, unsigned int cmd, ioctl_arg arg, int local);
 120 static void     ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 121 static void     ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 122 static int      ad1848_prepare_for_IO (int dev, int bsize, int bcount);
 123 static void     ad1848_reset (int dev);
 124 static void     ad1848_halt (int dev);
 125 static void     ad1848_halt_input (int dev);
 126 static void     ad1848_halt_output (int dev);
 127 static void     ad1848_trigger (int dev, int bits);
 128 static int      ad1848_tmr_install (int dev);
 129 static void     ad1848_tmr_reprogram (int dev);
 130 
 131 static int
 132 ad_read (ad1848_info * devc, int reg)
     /* [previous][next][first][last][top][bottom][index][help] */
 133 {
 134   unsigned long   flags;
 135   int             x;
 136   int             timeout = 900000;
 137 
 138   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 139     timeout--;
 140 
 141   save_flags (flags);
 142   cli ();
 143   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 144   x = inb (io_Indexed_Data (devc));
 145   /*  printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
 146   restore_flags (flags);
 147 
 148   return x;
 149 }
 150 
 151 static void
 152 ad_write (ad1848_info * devc, int reg, int data)
     /* [previous][next][first][last][top][bottom][index][help] */
 153 {
 154   unsigned long   flags;
 155   int             timeout = 90000;
 156 
 157   while (timeout > 0 &&
 158          inb (devc->base) == 0x80)      /*Are we initializing */
 159     timeout--;
 160 
 161   save_flags (flags);
 162   cli ();
 163   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 164   outb ((unsigned char) (data & 0xff), io_Indexed_Data (devc));
 165   /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
 166   restore_flags (flags);
 167 }
 168 
 169 static void
 170 wait_for_calibration (ad1848_info * devc)
     /* [previous][next][first][last][top][bottom][index][help] */
 171 {
 172   int             timeout = 0;
 173 
 174   /*
 175      * Wait until the auto calibration process has finished.
 176      *
 177      * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 178      * 2)       Wait until the ACI bit of I11 gets on and then off.
 179    */
 180 
 181   timeout = 100000;
 182   while (timeout > 0 && inb (devc->base) & 0x80)
 183     timeout--;
 184   if (inb (devc->base) & 0x80)
 185     printk ("ad1848: Auto calibration timed out(1).\n");
 186 
 187   timeout = 100;
 188   while (timeout > 0 && !(ad_read (devc, 11) & 0x20))
 189     timeout--;
 190   if (!(ad_read (devc, 11) & 0x20))
 191     return;
 192 
 193   timeout = 20000;
 194   while (timeout > 0 && ad_read (devc, 11) & 0x20)
 195     timeout--;
 196   if (ad_read (devc, 11) & 0x20)
 197     printk ("ad1848: Auto calibration timed out(3).\n");
 198 }
 199 
 200 static void
 201 ad_mute (ad1848_info * devc)
     /* [previous][next][first][last][top][bottom][index][help] */
 202 {
 203   int             i;
 204   unsigned char   prev;
 205 
 206   /*
 207      * Save old register settings and mute output channels
 208    */
 209   for (i = 6; i < 8; i++)
 210     {
 211       prev = devc->saved_regs[i] = ad_read (devc, i);
 212       ad_write (devc, i, prev | 0x80);
 213     }
 214 }
 215 
 216 static void
 217 ad_unmute (ad1848_info * devc)
     /* [previous][next][first][last][top][bottom][index][help] */
 218 {
 219   int             i;
 220 
 221   /*
 222      * Restore back old volume registers (unmute)
 223    */
 224   for (i = 6; i < 8; i++)
 225     {
 226       ad_write (devc, i, devc->saved_regs[i] & ~0x80);
 227     }
 228 }
 229 
 230 static void
 231 ad_enter_MCE (ad1848_info * devc)
     /* [previous][next][first][last][top][bottom][index][help] */
 232 {
 233   unsigned long   flags;
 234   int             timeout = 1000;
 235   unsigned short  prev;
 236 
 237   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 238     timeout--;
 239 
 240   save_flags (flags);
 241   cli ();
 242 
 243   devc->MCE_bit = 0x40;
 244   prev = inb (io_Index_Addr (devc));
 245   if (prev & 0x40)
 246     {
 247       restore_flags (flags);
 248       return;
 249     }
 250 
 251   outb (devc->MCE_bit, io_Index_Addr (devc));
 252   restore_flags (flags);
 253 }
 254 
 255 static void
 256 ad_leave_MCE (ad1848_info * devc)
     /* [previous][next][first][last][top][bottom][index][help] */
 257 {
 258   unsigned long   flags;
 259   unsigned char   prev;
 260   int             timeout = 1000;
 261 
 262   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 263     timeout--;
 264 
 265   save_flags (flags);
 266   cli ();
 267 
 268   devc->MCE_bit = 0x00;
 269   prev = inb (io_Index_Addr (devc));
 270   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 271 
 272   if ((prev & 0x40) == 0)       /* Not in MCE mode */
 273     {
 274       restore_flags (flags);
 275       return;
 276     }
 277 
 278   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 279   wait_for_calibration (devc);
 280   restore_flags (flags);
 281 }
 282 
 283 
 284 static int
 285 ad1848_set_recmask (ad1848_info * devc, int mask)
     /* [previous][next][first][last][top][bottom][index][help] */
 286 {
 287   unsigned char   recdev;
 288   int             i, n;
 289 
 290   mask &= devc->supported_rec_devices;
 291 
 292   n = 0;
 293   for (i = 0; i < 32; i++)      /* Count selected device bits */
 294     if (mask & (1 << i))
 295       n++;
 296 
 297   if (n == 0)
 298     mask = SOUND_MASK_MIC;
 299   else if (n != 1)              /* Too many devices selected */
 300     {
 301       mask &= ~devc->recmask;   /* Filter out active settings */
 302 
 303       n = 0;
 304       for (i = 0; i < 32; i++)  /* Count selected device bits */
 305         if (mask & (1 << i))
 306           n++;
 307 
 308       if (n != 1)
 309         mask = SOUND_MASK_MIC;
 310     }
 311 
 312   switch (mask)
 313     {
 314     case SOUND_MASK_MIC:
 315       recdev = 2;
 316       break;
 317 
 318     case SOUND_MASK_LINE:
 319     case SOUND_MASK_LINE3:
 320       recdev = 0;
 321       break;
 322 
 323     case SOUND_MASK_CD:
 324     case SOUND_MASK_LINE1:
 325       recdev = 1;
 326       break;
 327 
 328     case SOUND_MASK_IMIX:
 329       recdev = 3;
 330       break;
 331 
 332     default:
 333       mask = SOUND_MASK_MIC;
 334       recdev = 2;
 335     }
 336 
 337   recdev <<= 6;
 338   ad_write (devc, 0, (ad_read (devc, 0) & 0x3f) | recdev);
 339   ad_write (devc, 1, (ad_read (devc, 1) & 0x3f) | recdev);
 340 
 341   devc->recmask = mask;
 342   return mask;
 343 }
 344 
 345 static void
 346 change_bits (unsigned char *regval, int dev, int chn, int newval)
     /* [previous][next][first][last][top][bottom][index][help] */
 347 {
 348   unsigned char   mask;
 349   int             shift;
 350 
 351   if (mix_devices[dev][chn].polarity == 1)      /* Reverse */
 352     newval = 100 - newval;
 353 
 354   mask = (1 << mix_devices[dev][chn].nbits) - 1;
 355   shift = mix_devices[dev][chn].bitpos;
 356   newval = (int) ((newval * mask) + 50) / 100;  /* Scale it */
 357 
 358   *regval &= ~(mask << shift);  /* Clear bits */
 359   *regval |= (newval & mask) << shift;  /* Set new value */
 360 }
 361 
 362 static int
 363 ad1848_mixer_get (ad1848_info * devc, int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
 364 {
 365   if (!((1 << dev) & devc->supported_devices))
 366     return -EINVAL;
 367 
 368   return devc->levels[dev];
 369 }
 370 
 371 static int
 372 ad1848_mixer_set (ad1848_info * devc, int dev, int value)
     /* [previous][next][first][last][top][bottom][index][help] */
 373 {
 374   int             left = value & 0x000000ff;
 375   int             right = (value & 0x0000ff00) >> 8;
 376   int             retvol;
 377 
 378   int             regoffs;
 379   unsigned char   val;
 380 
 381   if (left > 100)
 382     left = 100;
 383   if (right > 100)
 384     right = 100;
 385 
 386   if (mix_devices[dev][RIGHT_CHN].nbits == 0)   /* Mono control */
 387     right = left;
 388 
 389   retvol = left | (left << 8);
 390 
 391   /* Scale volumes */
 392   left = mix_cvt[left];
 393   right = mix_cvt[right];
 394 
 395   /* Scale it again */
 396   left = mix_cvt[left];
 397   right = mix_cvt[right];
 398 
 399   if (dev > 31)
 400     return -EINVAL;
 401 
 402   if (!(devc->supported_devices & (1 << dev)))
 403     return -EINVAL;
 404 
 405   if (mix_devices[dev][LEFT_CHN].nbits == 0)
 406     return -EINVAL;
 407 
 408   devc->levels[dev] = retvol;
 409 
 410   /*
 411      * Set the left channel
 412    */
 413 
 414   regoffs = mix_devices[dev][LEFT_CHN].regno;
 415   val = ad_read (devc, regoffs);
 416   change_bits (&val, dev, LEFT_CHN, left);
 417   ad_write (devc, regoffs, val);
 418   devc->saved_regs[regoffs] = val;
 419 
 420   /*
 421      * Set the right channel
 422    */
 423 
 424   if (mix_devices[dev][RIGHT_CHN].nbits == 0)
 425     return retvol;              /* Was just a mono channel */
 426 
 427   regoffs = mix_devices[dev][RIGHT_CHN].regno;
 428   val = ad_read (devc, regoffs);
 429   change_bits (&val, dev, RIGHT_CHN, right);
 430   ad_write (devc, regoffs, val);
 431   devc->saved_regs[regoffs] = val;
 432 
 433   return retvol;
 434 }
 435 
 436 static void
 437 ad1848_mixer_reset (ad1848_info * devc)
     /* [previous][next][first][last][top][bottom][index][help] */
 438 {
 439   int             i;
 440 
 441   switch (devc->mode)
 442     {
 443     case MD_4231:
 444       devc->supported_devices = MODE2_MIXER_DEVICES;
 445       break;
 446 
 447     case MD_4232:
 448       devc->supported_devices = MODE3_MIXER_DEVICES;
 449       break;
 450 
 451     default:
 452       devc->supported_devices = MODE1_MIXER_DEVICES;
 453     }
 454 
 455   devc->supported_rec_devices = MODE1_REC_DEVICES;
 456 
 457   for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 458     if (devc->supported_devices & (1 << i))
 459       ad1848_mixer_set (devc, i, default_mixer_levels[i]);
 460   ad1848_set_recmask (devc, SOUND_MASK_MIC);
 461 }
 462 
 463 static int
 464 ad1848_mixer_ioctl (int dev, unsigned int cmd, ioctl_arg arg)
     /* [previous][next][first][last][top][bottom][index][help] */
 465 {
 466   ad1848_info    *devc;
 467 
 468   int             codec_dev = mixer2codec[dev];
 469 
 470   if (!codec_dev)
 471     return -ENXIO;
 472 
 473   codec_dev--;
 474 
 475   devc = (ad1848_info *) audio_devs[codec_dev]->devc;
 476 
 477   if (((cmd >> 8) & 0xff) == 'M')
 478     {
 479 
 480       if (_IOC_DIR (cmd) & _IOC_WRITE)
 481         switch (cmd & 0xff)
 482           {
 483           case SOUND_MIXER_RECSRC:
 484             return snd_ioctl_return ((int *) arg, ad1848_set_recmask (devc, get_fs_long ((long *) arg)));
 485             break;
 486 
 487           default:
 488             return snd_ioctl_return ((int *) arg, ad1848_mixer_set (devc, cmd & 0xff, get_fs_long ((long *) arg)));
 489           }
 490       else
 491         switch (cmd & 0xff)     /*
 492                                  * Return parameters
 493                                  */
 494           {
 495 
 496           case SOUND_MIXER_RECSRC:
 497             return snd_ioctl_return ((int *) arg, devc->recmask);
 498             break;
 499 
 500           case SOUND_MIXER_DEVMASK:
 501             return snd_ioctl_return ((int *) arg, devc->supported_devices);
 502             break;
 503 
 504           case SOUND_MIXER_STEREODEVS:
 505             return snd_ioctl_return ((int *) arg, devc->supported_devices & ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX));
 506             break;
 507 
 508           case SOUND_MIXER_RECMASK:
 509             return snd_ioctl_return ((int *) arg, devc->supported_rec_devices);
 510             break;
 511 
 512           case SOUND_MIXER_CAPS:
 513             return snd_ioctl_return ((int *) arg, SOUND_CAP_EXCL_INPUT);
 514             break;
 515 
 516           default:
 517             return snd_ioctl_return ((int *) arg, ad1848_mixer_get (devc, cmd & 0xff));
 518           }
 519     }
 520   else
 521     return -EINVAL;
 522 }
 523 
 524 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
 525 {
 526   {
 527     "Generic AD1848 codec",
 528     DMA_AUTOMODE,
 529     AFMT_U8,                    /* Will be set later */
 530     NULL,
 531     ad1848_open,
 532     ad1848_close,
 533     ad1848_output_block,
 534     ad1848_start_input,
 535     ad1848_ioctl,
 536     ad1848_prepare_for_IO,
 537     ad1848_prepare_for_IO,
 538     ad1848_reset,
 539     ad1848_halt,
 540     NULL,
 541     NULL,
 542     ad1848_halt_input,
 543     ad1848_halt_output,
 544     ad1848_trigger
 545   }};
 546 
 547 static struct mixer_operations ad1848_mixer_operations =
 548 {
 549   "AD1848/CS4248/CS4231",
 550   ad1848_mixer_ioctl
 551 };
 552 
 553 static int
 554 ad1848_open (int dev, int mode)
     /* [previous][next][first][last][top][bottom][index][help] */
 555 {
 556   ad1848_info    *devc = NULL;
 557   unsigned long   flags;
 558 
 559   if (dev < 0 || dev >= num_audiodevs)
 560     return -ENXIO;
 561 
 562   devc = (ad1848_info *) audio_devs[dev]->devc;
 563 
 564   save_flags (flags);
 565   cli ();
 566   if (devc->opened)
 567     {
 568       restore_flags (flags);
 569       printk ("ad1848: Already opened\n");
 570       return -EBUSY;
 571     }
 572 
 573 
 574   devc->dual_dma = 0;
 575 
 576   if (audio_devs[dev]->flags & DMA_DUPLEX)
 577     {
 578       devc->dual_dma = 1;
 579     }
 580 
 581   devc->intr_active = 0;
 582   devc->opened = 1;
 583   devc->irq_mode = 0;
 584   ad1848_trigger (dev, 0);
 585   restore_flags (flags);
 586 /*
 587  * Mute output until the playback really starts. This decreases clicking.
 588  */
 589   ad_mute (devc);
 590 
 591   return 0;
 592 }
 593 
 594 static void
 595 ad1848_close (int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
 596 {
 597   unsigned long   flags;
 598   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 599 
 600   DEB (printk ("ad1848_close(void)\n"));
 601 
 602   save_flags (flags);
 603   cli ();
 604 
 605   devc->intr_active = 0;
 606   ad1848_reset (dev);
 607 
 608 
 609   devc->opened = 0;
 610   devc->irq_mode = 0;
 611 
 612   ad_unmute (devc);
 613   restore_flags (flags);
 614 }
 615 
 616 static int
 617 set_speed (ad1848_info * devc, int arg)
     /* [previous][next][first][last][top][bottom][index][help] */
 618 {
 619   /*
 620      * The sampling speed is encoded in the least significant nible of I8. The
 621      * LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other
 622      * three bits select the divisor (indirectly):
 623      *
 624      * The available speeds are in the following table. Keep the speeds in
 625      * the increasing order.
 626    */
 627   typedef struct
 628   {
 629     int             speed;
 630     unsigned char   bits;
 631   }
 632   speed_struct;
 633 
 634   static speed_struct speed_table[] =
 635   {
 636     {5510, (0 << 1) | 1},
 637     {5510, (0 << 1) | 1},
 638     {6620, (7 << 1) | 1},
 639     {8000, (0 << 1) | 0},
 640     {9600, (7 << 1) | 0},
 641     {11025, (1 << 1) | 1},
 642     {16000, (1 << 1) | 0},
 643     {18900, (2 << 1) | 1},
 644     {22050, (3 << 1) | 1},
 645     {27420, (2 << 1) | 0},
 646     {32000, (3 << 1) | 0},
 647     {33075, (6 << 1) | 1},
 648     {37800, (4 << 1) | 1},
 649     {44100, (5 << 1) | 1},
 650     {48000, (6 << 1) | 0}
 651   };
 652 
 653   int             i, n, selected = -1;
 654 
 655   n = sizeof (speed_table) / sizeof (speed_struct);
 656 
 657   if (devc->mode == MD_1845)    /* AD1845 has different timer than others */
 658     {
 659       if (arg < 4000)
 660         arg = 4000;
 661       if (arg > 50000)
 662         arg = 50000;
 663 
 664       devc->speed = arg;
 665       devc->speed_bits = speed_table[selected].bits;
 666       return devc->speed;
 667     }
 668 
 669   if (arg < speed_table[0].speed)
 670     selected = 0;
 671   if (arg > speed_table[n - 1].speed)
 672     selected = n - 1;
 673 
 674   for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 675     if (speed_table[i].speed == arg)
 676       selected = i;
 677     else if (speed_table[i].speed > arg)
 678       {
 679         int             diff1, diff2;
 680 
 681         diff1 = arg - speed_table[i - 1].speed;
 682         diff2 = speed_table[i].speed - arg;
 683 
 684         if (diff1 < diff2)
 685           selected = i - 1;
 686         else
 687           selected = i;
 688       }
 689 
 690   if (selected == -1)
 691     {
 692       printk ("ad1848: Can't find speed???\n");
 693       selected = 3;
 694     }
 695 
 696   devc->speed = speed_table[selected].speed;
 697   devc->speed_bits = speed_table[selected].bits;
 698   return devc->speed;
 699 }
 700 
 701 static int
 702 set_channels (ad1848_info * devc, int arg)
     /* [previous][next][first][last][top][bottom][index][help] */
 703 {
 704   if (arg != 1 && arg != 2)
 705     return devc->channels;
 706 
 707   devc->channels = arg;
 708   return arg;
 709 }
 710 
 711 static int
 712 set_format (ad1848_info * devc, int arg)
     /* [previous][next][first][last][top][bottom][index][help] */
 713 {
 714 
 715   static struct format_tbl
 716   {
 717     int             format;
 718     unsigned char   bits;
 719   }
 720   format2bits[] =
 721   {
 722     {
 723       0, 0
 724     }
 725     ,
 726     {
 727       AFMT_MU_LAW, 1
 728     }
 729     ,
 730     {
 731       AFMT_A_LAW, 3
 732     }
 733     ,
 734     {
 735       AFMT_IMA_ADPCM, 5
 736     }
 737     ,
 738     {
 739       AFMT_U8, 0
 740     }
 741     ,
 742     {
 743       AFMT_S16_LE, 2
 744     }
 745     ,
 746     {
 747       AFMT_S16_BE, 6
 748     }
 749     ,
 750     {
 751       AFMT_S8, 0
 752     }
 753     ,
 754     {
 755       AFMT_U16_LE, 0
 756     }
 757     ,
 758     {
 759       AFMT_U16_BE, 0
 760     }
 761   };
 762   int             i, n = sizeof (format2bits) / sizeof (struct format_tbl);
 763 
 764   if (!(arg & ad_format_mask[devc->mode]))
 765     arg = AFMT_U8;
 766 
 767   devc->audio_format = arg;
 768 
 769   for (i = 0; i < n; i++)
 770     if (format2bits[i].format == arg)
 771       {
 772         if ((devc->format_bits = format2bits[i].bits) == 0)
 773           return devc->audio_format = AFMT_U8;  /* Was not supported */
 774 
 775         return arg;
 776       }
 777 
 778   /* Still hanging here. Something must be terribly wrong */
 779   devc->format_bits = 0;
 780   return devc->audio_format = AFMT_U8;
 781 }
 782 
 783 static int
 784 ad1848_ioctl (int dev, unsigned int cmd, ioctl_arg arg, int local)
     /* [previous][next][first][last][top][bottom][index][help] */
 785 {
 786   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 787 
 788   switch (cmd)
 789     {
 790     case SOUND_PCM_WRITE_RATE:
 791       if (local)
 792         return set_speed (devc, (int) arg);
 793       return snd_ioctl_return ((int *) arg, set_speed (devc, get_fs_long ((long *) arg)));
 794 
 795     case SOUND_PCM_READ_RATE:
 796       if (local)
 797         return devc->speed;
 798       return snd_ioctl_return ((int *) arg, devc->speed);
 799 
 800     case SNDCTL_DSP_STEREO:
 801       if (local)
 802         return set_channels (devc, (int) arg + 1) - 1;
 803       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg) + 1) - 1);
 804 
 805     case SOUND_PCM_WRITE_CHANNELS:
 806       if (local)
 807         return set_channels (devc, (int) arg);
 808       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg)));
 809 
 810     case SOUND_PCM_READ_CHANNELS:
 811       if (local)
 812         return devc->channels;
 813       return snd_ioctl_return ((int *) arg, devc->channels);
 814 
 815     case SNDCTL_DSP_SAMPLESIZE:
 816       if (local)
 817         return set_format (devc, (int) arg);
 818       return snd_ioctl_return ((int *) arg, set_format (devc, get_fs_long ((long *) arg)));
 819 
 820     case SOUND_PCM_READ_BITS:
 821       if (local)
 822         return devc->audio_format;
 823       return snd_ioctl_return ((int *) arg, devc->audio_format);
 824 
 825     default:;
 826     }
 827   return -EINVAL;
 828 }
 829 
 830 static void
 831 ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /* [previous][next][first][last][top][bottom][index][help] */
 832 {
 833   unsigned long   flags, cnt;
 834   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 835 
 836   cnt = count;
 837 
 838   if (devc->audio_format == AFMT_IMA_ADPCM)
 839     {
 840       cnt /= 4;
 841     }
 842   else
 843     {
 844       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 845         cnt >>= 1;
 846     }
 847   if (devc->channels > 1)
 848     cnt >>= 1;
 849   cnt--;
 850 
 851   if (devc->irq_mode & PCM_ENABLE_OUTPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 852       intrflag &&
 853       cnt == devc->xfer_count)
 854     {
 855       devc->irq_mode |= PCM_ENABLE_OUTPUT;
 856       devc->intr_active = 1;
 857       return;                   /*
 858                                  * Auto DMA mode on. No need to react
 859                                  */
 860     }
 861   save_flags (flags);
 862   cli ();
 863 
 864   if (dma_restart)
 865     {
 866       /* ad1848_halt (dev); */
 867       DMAbuf_start_dma (dev, buf, count, DMA_MODE_WRITE);
 868     }
 869 
 870   ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 871   ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 872 
 873   /* ad_write (devc, 9, ad_read (devc, 9) | 0x01); *//* Playback enable */
 874   ad_unmute (devc);
 875 
 876   devc->xfer_count = cnt;
 877   devc->irq_mode |= PCM_ENABLE_OUTPUT;
 878   devc->intr_active = 1;
 879   restore_flags (flags);
 880 }
 881 
 882 static void
 883 ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /* [previous][next][first][last][top][bottom][index][help] */
 884 {
 885   unsigned long   flags, cnt;
 886   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 887 
 888   cnt = count;
 889   if (devc->audio_format == AFMT_IMA_ADPCM)
 890     {
 891       cnt /= 4;
 892     }
 893   else
 894     {
 895       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 896         cnt >>= 1;
 897     }
 898   if (devc->channels > 1)
 899     cnt >>= 1;
 900   cnt--;
 901 
 902   if (devc->irq_mode & PCM_ENABLE_INPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 903       intrflag &&
 904       cnt == devc->xfer_count)
 905     {
 906       devc->irq_mode |= PCM_ENABLE_INPUT;
 907       devc->intr_active = 1;
 908       return;                   /*
 909                                  * Auto DMA mode on. No need to react
 910                                  */
 911     }
 912   save_flags (flags);
 913   cli ();
 914 
 915   if (dma_restart)
 916     {
 917       /* ad1848_halt (dev); */
 918       DMAbuf_start_dma (dev, buf, count, DMA_MODE_READ);
 919     }
 920 
 921   if (devc->mode == MD_1848 || !devc->dual_dma)         /* Single DMA channel mode */
 922     {
 923       ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 924       ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 925     }
 926   else
 927     /* Dual DMA channel mode */
 928     {
 929       ad_write (devc, 31, (unsigned char) (cnt & 0xff));
 930       ad_write (devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
 931     }
 932 
 933   /*  ad_write (devc, 9, ad_read (devc, 9) | 0x02); *//* Capture enable */
 934   ad_unmute (devc);
 935 
 936   devc->xfer_count = cnt;
 937   devc->irq_mode |= PCM_ENABLE_INPUT;
 938   devc->intr_active = 1;
 939   restore_flags (flags);
 940 }
 941 
 942 static int
 943 ad1848_prepare_for_IO (int dev, int bsize, int bcount)
     /* [previous][next][first][last][top][bottom][index][help] */
 944 {
 945   int             timeout;
 946   unsigned char   fs, old_fs;
 947   unsigned long   flags;
 948   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 949 
 950   if (devc->irq_mode)
 951     return 0;
 952 
 953   save_flags (flags);
 954   cli ();
 955   fs = devc->speed_bits | (devc->format_bits << 5);
 956 
 957   if (devc->channels > 1)
 958     fs |= 0x10;
 959 
 960   if (devc->mode == MD_1845)    /* Use alternate speed select registers */
 961     {
 962       fs &= 0xf0;               /* Mask off the rate select bits */
 963 
 964       ad_write (devc, 22, (devc->speed >> 8) & 0xff);   /* Speed MSB */
 965       ad_write (devc, 23, devc->speed & 0xff);  /* Speed LSB */
 966     }
 967 
 968   if (fs == (old_fs = ad_read (devc, 8)))       /* No change */
 969     {
 970       restore_flags (flags);
 971       devc->xfer_count = 0;
 972       return 0;
 973     }
 974 
 975   ad_enter_MCE (devc);          /* Enables changes to the format select reg */
 976   ad_write (devc, 8, fs);
 977   /*
 978    * Write to I8 starts resyncronization. Wait until it completes.
 979    */
 980   timeout = 10000;
 981   while (timeout > 0 && inb (devc->base) == 0x80)
 982     timeout--;
 983 
 984   /*
 985      * If mode == 2 (CS4231), set I28 also. It's the capture format register.
 986    */
 987   if (devc->mode != MD_1848)
 988     {
 989       ad_write (devc, 28, fs);
 990 
 991       /*
 992          * Write to I28 starts resyncronization. Wait until it completes.
 993        */
 994       timeout = 10000;
 995       while (timeout > 0 && inb (devc->base) == 0x80)
 996         timeout--;
 997 
 998     }
 999 
1000   ad_leave_MCE (devc);          /*
1001                                  * Starts the calibration process.
1002                                  */
1003   restore_flags (flags);
1004   devc->xfer_count = 0;
1005 
1006 #ifdef CONFIG_SEQUENCER
1007   if (dev == timer_installed && devc->timer_running)
1008     if ((fs & 0x01) != (old_fs & 0x01))
1009       {
1010         ad1848_tmr_reprogram (dev);
1011       }
1012 #endif
1013   return 0;
1014 }
1015 
1016 static void
1017 ad1848_reset (int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1018 {
1019   ad1848_halt (dev);
1020 }
1021 
1022 static void
1023 ad1848_halt (int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1024 {
1025   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1026   unsigned long   flags;
1027   int             timeout;
1028 
1029   save_flags (flags);
1030   cli ();
1031 
1032   ad_mute (devc);
1033   ad_enter_MCE (devc);
1034   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1035   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1036 
1037   ad_write (devc, 15, 0);       /* Clear DMA counter */
1038   ad_write (devc, 14, 0);       /* Clear DMA counter */
1039 
1040   if (devc->mode != MD_1848)
1041     {
1042       ad_write (devc, 30, 0);   /* Clear DMA counter */
1043       ad_write (devc, 31, 0);   /* Clear DMA counter */
1044     }
1045 
1046   for (timeout = 0; timeout < 1000 && !(inb (io_Status (devc)) & 0x80);
1047        timeout++);              /* Wait for interrupt */
1048 
1049   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1050   outb (0, io_Status (devc));   /* Clear interrupt status */
1051   outb (0, io_Status (devc));   /* Clear interrupt status */
1052   devc->irq_mode = 0;
1053   ad_leave_MCE (devc);
1054 
1055   /* DMAbuf_reset_dma (dev); */
1056   restore_flags (flags);
1057 }
1058 
1059 static void
1060 ad1848_halt_input (int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1061 {
1062   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1063   unsigned long   flags;
1064 
1065   if (devc->mode == MD_1848)
1066     {
1067       ad1848_halt (dev);
1068       return;
1069     }
1070 
1071   save_flags (flags);
1072   cli ();
1073 
1074   ad_mute (devc);
1075   ad_write (devc, 9, ad_read (devc, 9) & ~0x02);        /* Stop capture */
1076 
1077 
1078   devc->irq_mode &= ~PCM_ENABLE_INPUT;
1079 
1080   restore_flags (flags);
1081 }
1082 
1083 static void
1084 ad1848_halt_output (int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1085 {
1086   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1087   unsigned long   flags;
1088 
1089   if (devc->mode == MD_1848)
1090     {
1091       ad1848_halt (dev);
1092       return;
1093     }
1094 
1095   save_flags (flags);
1096   cli ();
1097 
1098   ad_mute (devc);
1099   ad_write (devc, 9, ad_read (devc, 9) & ~0x01);        /* Stop playback */
1100 
1101 
1102   devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1103 
1104   restore_flags (flags);
1105 }
1106 
1107 static void
1108 ad1848_trigger (int dev, int state)
     /* [previous][next][first][last][top][bottom][index][help] */
1109 {
1110   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1111   unsigned long   flags;
1112   unsigned char   tmp;
1113 
1114   save_flags (flags);
1115   cli ();
1116   state &= devc->irq_mode;
1117 
1118   tmp = ad_read (devc, 9) & ~0x03;
1119   if (state & PCM_ENABLE_INPUT)
1120     tmp |= 0x02;
1121   if (state & PCM_ENABLE_OUTPUT)
1122     tmp |= 0x01;
1123   ad_write (devc, 9, tmp);
1124 
1125   restore_flags (flags);
1126 }
1127 
1128 int
1129 ad1848_detect (int io_base, int *ad_flags, sound_os_info * osp)
     /* [previous][next][first][last][top][bottom][index][help] */
1130 {
1131 
1132   unsigned char   tmp;
1133   int             i;
1134   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1135   unsigned char   tmp1 = 0xff, tmp2 = 0xff;
1136 
1137   DDB (printk ("ad1848_detect(%x)\n", io_base));
1138 
1139   if (ad_flags)
1140     *ad_flags = 0;
1141 
1142   if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1143     {
1144       DDB (printk ("ad1848 detect error - step 0\n"));
1145       return 0;
1146     }
1147   if (check_region (io_base, 4))
1148     {
1149       printk ("\n\nad1848.c: Port %x not free.\n\n", io_base);
1150       return 0;
1151     }
1152 
1153   devc->base = io_base;
1154   devc->irq_ok = 0;
1155   devc->timer_running = 0;
1156   devc->MCE_bit = 0x40;
1157   devc->irq = 0;
1158   devc->opened = 0;
1159   devc->chip_name = "AD1848";
1160   devc->mode = MD_1848;         /* AD1848 or CS4248 */
1161   devc->osp = osp;
1162 
1163   /*
1164      * Check that the I/O address is in use.
1165      *
1166      * The bit 0x80 of the base I/O port is known to be 0 after the
1167      * chip has performed it's power on initialization. Just assume
1168      * this has happened before the OS is starting.
1169      *
1170      * If the I/O address is unused, it typically returns 0xff.
1171    */
1172 
1173   DDB (printk ("ad1848_detect() - step A\n"));
1174   if ((inb (devc->base) & 0x80) != 0x00)        /* Not a AD1848 */
1175     {
1176       DDB (printk ("ad1848 detect error - step A (%02x)\n",
1177                    inb (devc->base)));
1178       return 0;
1179     }
1180 
1181   /*
1182      * Test if it's possible to change contents of the indirect registers.
1183      * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1184      * so try to avoid using it.
1185    */
1186 
1187   DDB (printk ("ad1848_detect() - step B\n"));
1188   ad_write (devc, 0, 0xaa);
1189   ad_write (devc, 1, 0x45);     /* 0x55 with bit 0x10 clear */
1190 
1191   if ((tmp1 = ad_read (devc, 0)) != 0xaa || (tmp2 = ad_read (devc, 1)) != 0x45)
1192     {
1193       DDB (printk ("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1194       return 0;
1195     }
1196 
1197   DDB (printk ("ad1848_detect() - step C\n"));
1198   ad_write (devc, 0, 0x45);
1199   ad_write (devc, 1, 0xaa);
1200 
1201   if ((tmp1 = ad_read (devc, 0)) != 0x45 || (tmp2 = ad_read (devc, 1)) != 0xaa)
1202     {
1203       DDB (printk ("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1204       return 0;
1205     }
1206 
1207   /*
1208      * The indirect register I12 has some read only bits. Lets
1209      * try to change them.
1210    */
1211 
1212   DDB (printk ("ad1848_detect() - step D\n"));
1213   tmp = ad_read (devc, 12);
1214   ad_write (devc, 12, (~tmp) & 0x0f);
1215 
1216   if ((tmp & 0x0f) != ((tmp1 = ad_read (devc, 12)) & 0x0f))
1217     {
1218       DDB (printk ("ad1848 detect error - step D (%x)\n", tmp1));
1219       return 0;
1220     }
1221 
1222   /*
1223      * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1224      *   0x01=RevB and 0x0A=RevC.
1225    */
1226 
1227   /*
1228      * The original AD1848/CS4248 has just 15 indirect registers. This means
1229      * that I0 and I16 should return the same value (etc.).
1230      * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1231      * with CS4231.
1232    */
1233 
1234   DDB (printk ("ad1848_detect() - step F\n"));
1235   ad_write (devc, 12, 0);       /* Mode2=disabled */
1236 
1237   for (i = 0; i < 16; i++)
1238     if ((tmp1 = ad_read (devc, i)) != (tmp2 = ad_read (devc, i + 16)))
1239       {
1240         DDB (printk ("ad1848 detect error - step F(%d/%x/%x)\n", i, tmp1, tmp2));
1241         return 0;
1242       }
1243 
1244   /*
1245      * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1246      * The bit 0x80 is always 1 in CS4248 and CS4231.
1247    */
1248 
1249   DDB (printk ("ad1848_detect() - step G\n"));
1250   ad_write (devc, 12, 0x40);    /* Set mode2, clear 0x80 */
1251 
1252   tmp1 = ad_read (devc, 12);
1253   if (tmp1 & 0x80)
1254     {
1255       if (ad_flags)
1256         *ad_flags |= AD_F_CS4248;
1257 
1258       devc->chip_name = "CS4248";       /* Our best knowledge just now */
1259     }
1260 
1261   if ((tmp1 & 0xc0) == (0x80 | 0x40))
1262     {
1263       /*
1264          *      CS4231 detected - is it?
1265          *
1266          *      Verify that setting I0 doesn't change I16.
1267        */
1268       DDB (printk ("ad1848_detect() - step H\n"));
1269       ad_write (devc, 16, 0);   /* Set I16 to known value */
1270 
1271       ad_write (devc, 0, 0x45);
1272       if ((tmp1 = ad_read (devc, 16)) != 0x45)  /* No change -> CS4231? */
1273         {
1274 
1275           ad_write (devc, 0, 0xaa);
1276           if ((tmp1 = ad_read (devc, 16)) == 0xaa)      /* Rotten bits? */
1277             {
1278               DDB (printk ("ad1848 detect error - step H(%x)\n", tmp1));
1279               return 0;
1280             }
1281 
1282           /*
1283              * Verify that some bits of I25 are read only.
1284            */
1285 
1286           DDB (printk ("ad1848_detect() - step I\n"));
1287           tmp1 = ad_read (devc, 25);    /* Original bits */
1288           ad_write (devc, 25, ~tmp1);   /* Invert all bits */
1289           if ((ad_read (devc, 25) & 0xe7) == (tmp1 & 0xe7))
1290             {
1291               int             id;
1292 
1293               /*
1294                *      It's at least CS4231
1295                */
1296               devc->chip_name = "CS4231";
1297 
1298               devc->mode = MD_4231;
1299 
1300               /*
1301                * It could be an AD1845 or CS4231A as well.
1302                * CS4231 and AD1845 report the same revision info in I25
1303                * while the CS4231A reports different.
1304                */
1305 
1306               DDB (printk ("ad1848_detect() - step I\n"));
1307               id = ad_read (devc, 25) & 0xe7;
1308 
1309               switch (id)
1310                 {
1311 
1312                 case 0xa0:
1313                   devc->chip_name = "CS4231A";
1314                   devc->mode = MD_4231A;
1315                   break;
1316 
1317                 case 0xa2:
1318                   devc->chip_name = "CS4232";
1319                   devc->mode = MD_4232;
1320                   break;
1321 
1322                 case 0xb2:
1323                   devc->chip_name = "CS4232A";
1324                   devc->mode = MD_4232;
1325                   break;
1326 
1327                 case 0x80:
1328                   {
1329                     /* 
1330                      * It must be a CS4231 or AD1845. The register I23 of
1331                      * CS4231 is undefined and it appears to be read only.
1332                      * AD1845 uses I23 for setting sample rate. Assume
1333                      * the chip is AD1845 if I23 is changeable.
1334                      */
1335 
1336                     unsigned char   tmp = ad_read (devc, 23);
1337 
1338                     ad_write (devc, 23, ~tmp);
1339                     if (ad_read (devc, 23) != tmp)      /* AD1845 ? */
1340                       {
1341                         devc->chip_name = "AD1845";
1342                         devc->mode = MD_1845;
1343                       }
1344 
1345                     ad_write (devc, 23, tmp);   /* Restore */
1346                   }
1347                   break;
1348 
1349                 default:        /* Assume CS4231 */
1350                   devc->mode = MD_4231;
1351 
1352                 }
1353             }
1354           ad_write (devc, 25, tmp1);    /* Restore bits */
1355 
1356           DDB (printk ("ad1848_detect() - step K\n"));
1357         }
1358     }
1359 
1360   DDB (printk ("ad1848_detect() - step L\n"));
1361   if (ad_flags)
1362     {
1363       if (devc->mode != MD_1848)
1364         *ad_flags |= AD_F_CS4231;
1365     }
1366 
1367   DDB (printk ("ad1848_detect() - Detected OK\n"));
1368   return 1;
1369 }
1370 
1371 void
1372 ad1848_init (char *name, int io_base, int irq, int dma_playback, int dma_capture, int share_dma, sound_os_info * osp)
     /* [previous][next][first][last][top][bottom][index][help] */
1373 {
1374   /*
1375      * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1376      *   so that this driver doesn't need to allocate/deallocate it.
1377      *   The actually used IRQ is ABS(irq).
1378    */
1379 
1380   /*
1381      * Initial values for the indirect registers of CS4248/AD1848.
1382    */
1383   static int      init_values[] =
1384   {
1385     0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x80, 0x80,
1386     0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1387 
1388   /* Positions 16 to 31 just for CS4231 */
1389     0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1390     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1391   };
1392   int             i, my_dev;
1393 
1394   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1395 
1396   if (!ad1848_detect (io_base, NULL, osp))
1397     return;
1398 
1399   request_region (devc->base, 4, devc->chip_name);
1400 
1401   devc->irq = (irq > 0) ? irq : 0;
1402   devc->opened = 0;
1403   devc->timer_ticks = 0;
1404   devc->osp = osp;
1405 
1406   if (nr_ad1848_devs != 0)
1407     {
1408       memcpy ((char *) &ad1848_pcm_operations[nr_ad1848_devs],
1409               (char *) &ad1848_pcm_operations[0],
1410               sizeof (struct audio_operations));
1411     }
1412 
1413   for (i = 0; i < 16; i++)
1414     ad_write (devc, i, init_values[i]);
1415 
1416   ad_mute (devc);               /* Initialize some variables */
1417   ad_unmute (devc);             /* Leave it unmuted now */
1418 
1419   if (devc->mode > MD_1848)
1420     {
1421       if (dma_capture == dma_playback || dma_capture == -1 || dma_playback == -1)
1422         {
1423           ad_write (devc, 9, ad_read (devc, 9) | 0x04);         /* Single DMA mode */
1424           ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1425         }
1426       else
1427         {
1428           ad_write (devc, 9, ad_read (devc, 9) & ~0x04);        /* Dual DMA mode */
1429           ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_DUPLEX;
1430         }
1431 
1432       ad_write (devc, 12, ad_read (devc, 12) | 0x40);   /* Mode2 = enabled */
1433       for (i = 16; i < 32; i++)
1434         ad_write (devc, i, init_values[i]);
1435 
1436       if (devc->mode == MD_4231A || devc->mode == MD_4232)
1437         ad_write (devc, 9, init_values[9] | 0x18);      /* Enable full calibration */
1438 
1439       if (devc->mode == MD_1845)
1440         ad_write (devc, 27, init_values[27] | 0x08);    /* Alternate freq select enabled */
1441     }
1442   else
1443     {
1444       ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1445       ad_write (devc, 9, ad_read (devc, 9) | 0x04);     /* Single DMA mode */
1446     }
1447 
1448   outb (0, io_Status (devc));   /* Clear pending interrupts */
1449 
1450   if (name != NULL && name[0] != 0)
1451     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1452              "%s (%s)", name, devc->chip_name);
1453   else
1454     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1455              "Generic audio codec (%s)", devc->chip_name);
1456 
1457   conf_printf2 (ad1848_pcm_operations[nr_ad1848_devs].name,
1458                 devc->base, devc->irq, dma_playback, dma_capture);
1459 
1460   if (num_audiodevs < MAX_AUDIO_DEV)
1461     {
1462       audio_devs[my_dev = num_audiodevs++] = &ad1848_pcm_operations[nr_ad1848_devs];
1463       if (irq > 0)
1464         {
1465           audio_devs[my_dev]->devc = devc;
1466           irq2dev[irq] = my_dev;
1467           if (snd_set_irq_handler (devc->irq, ad1848_interrupt,
1468                                    audio_devs[my_dev]->name,
1469                                    devc->osp) < 0)
1470             {
1471               printk ("ad1848: IRQ in use\n");
1472             }
1473 
1474 #ifdef NO_IRQ_TEST
1475           if (devc->mode != MD_1848)
1476             {
1477               int             x;
1478               unsigned char   tmp = ad_read (devc, 16);
1479 
1480               devc->timer_ticks = 0;
1481 
1482               ad_write (devc, 21, 0x00);        /* Timer msb */
1483               ad_write (devc, 20, 0x10);        /* Timer lsb */
1484 
1485               ad_write (devc, 16, tmp | 0x40);  /* Enable timer */
1486               for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1487               ad_write (devc, 16, tmp & ~0x40);         /* Disable timer */
1488 
1489               if (devc->timer_ticks == 0)
1490                 printk ("[IRQ conflict???]");
1491               else
1492                 devc->irq_ok = 1;
1493 
1494             }
1495           else
1496             devc->irq_ok = 1;   /* Couldn't test. assume it's OK */
1497 #else
1498           devc->irq_ok = 1;
1499 #endif
1500         }
1501       else if (irq < 0)
1502         irq2dev[-irq] = devc->dev_no = my_dev;
1503 
1504       audio_devs[my_dev]->dmachan1 = dma_playback;
1505       audio_devs[my_dev]->dmachan2 = dma_capture;
1506       audio_devs[my_dev]->buffsize = DSP_BUFFSIZE;
1507       audio_devs[my_dev]->devc = devc;
1508       audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1509       nr_ad1848_devs++;
1510 
1511 #ifdef CONFIG_SEQUENCER
1512       if (devc->mode != MD_1848 && devc->irq_ok)
1513         ad1848_tmr_install (my_dev);
1514 #endif
1515 
1516       if (!share_dma)
1517         {
1518           if (sound_alloc_dma (dma_playback, "Sound System"))
1519             printk ("ad1848.c: Can't allocate DMA%d\n", dma_playback);
1520 
1521           if (dma_capture != dma_playback)
1522             if (sound_alloc_dma (dma_capture, "Sound System (capture)"))
1523               printk ("ad1848.c: Can't allocate DMA%d\n", dma_capture);
1524         }
1525 
1526       /*
1527          * Toggle the MCE bit. It completes the initialization phase.
1528        */
1529 
1530       ad_enter_MCE (devc);      /* In case the bit was off */
1531       ad_leave_MCE (devc);
1532 
1533       if (num_mixers < MAX_MIXER_DEV)
1534         {
1535           mixer2codec[num_mixers] = my_dev + 1;
1536           audio_devs[my_dev]->mixer_dev = num_mixers;
1537           mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1538           ad1848_mixer_reset (devc);
1539         }
1540     }
1541   else
1542     printk ("AD1848: Too many PCM devices available\n");
1543 }
1544 
1545 void
1546 ad1848_unload (int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
     /* [previous][next][first][last][top][bottom][index][help] */
1547 {
1548   int             i, dev = 0;
1549   ad1848_info    *devc = NULL;
1550 
1551   for (i = 0; devc == NULL && nr_ad1848_devs; i++)
1552     if (dev_info[i].base == io_base)
1553       {
1554         devc = &dev_info[i];
1555         dev = devc->dev_no;
1556       }
1557 
1558   if (devc != NULL)
1559     {
1560       release_region (devc->base, 4);
1561 
1562       if (!share_dma)
1563         {
1564           if (irq > 0)
1565             snd_release_irq (devc->irq);
1566 
1567           sound_free_dma (audio_devs[dev]->dmachan1);
1568 
1569           if (audio_devs[dev]->dmachan2 != audio_devs[dev]->dmachan1)
1570             sound_free_dma (audio_devs[dev]->dmachan2);
1571         }
1572     }
1573   else
1574     printk ("ad1848: Can't find device to be undoaded. Base=%x\n",
1575             io_base);
1576 }
1577 
1578 void
1579 ad1848_interrupt (int irq, struct pt_regs *dummy)
     /* [previous][next][first][last][top][bottom][index][help] */
1580 {
1581   unsigned char   status;
1582   ad1848_info    *devc;
1583   int             dev;
1584   int             alt_stat = 0xff;
1585 
1586   if (irq < 0 || irq > 15)
1587     {
1588       dev = -1;
1589     }
1590   else
1591     dev = irq2dev[irq];
1592 
1593   if (dev < 0 || dev >= num_audiodevs)
1594     {
1595       for (irq = 0; irq < 17; irq++)
1596         if (irq2dev[irq] != -1)
1597           break;
1598 
1599       if (irq > 15)
1600         {
1601           printk ("ad1848.c: Bogus interrupt %d\n", irq);
1602           return;
1603         }
1604 
1605       dev = irq2dev[irq];
1606       devc = (ad1848_info *) audio_devs[dev]->devc;
1607     }
1608   else
1609     devc = (ad1848_info *) audio_devs[dev]->devc;
1610 
1611   status = inb (io_Status (devc));
1612 
1613   if (status == 0x80)
1614     printk ("ad1848_interrupt: Why?\n");
1615 
1616   if (status & 0x01)
1617     {
1618 
1619       if (devc->mode != MD_1848)
1620         alt_stat = ad_read (devc, 24);
1621 
1622       if (devc->opened && devc->irq_mode & PCM_ENABLE_INPUT && alt_stat & 0x20)
1623         {
1624           DMAbuf_inputintr (dev);
1625         }
1626 
1627       if (devc->opened && devc->irq_mode & PCM_ENABLE_OUTPUT &&
1628           alt_stat & 0x10)
1629         {
1630           DMAbuf_outputintr (dev, 1);
1631         }
1632 
1633       if (devc->mode != MD_1848 && alt_stat & 0x40)     /* Timer interrupt */
1634         {
1635           devc->timer_ticks++;
1636 #ifdef CONFIG_SEQUENCER
1637           if (timer_installed == dev && devc->timer_running)
1638             sound_timer_interrupt ();
1639 #endif
1640         }
1641     }
1642 
1643   if (devc->mode != MD_1848)
1644     ad_write (devc, 24, ad_read (devc, 24) & ~alt_stat);        /* Selective ack */
1645   else
1646     outb (0, io_Status (devc)); /* Clear interrupt status */
1647 }
1648 
1649 /*
1650  * Some extra code for the MS Sound System
1651  */
1652 
1653 void
1654 check_opl3 (int base, struct address_info *hw_config)
     /* [previous][next][first][last][top][bottom][index][help] */
1655 {
1656 
1657   if (check_region (base, 4))
1658     {
1659       printk ("\n\nopl3.c: I/O port %x already in use\n\n", base);
1660       return;
1661     }
1662 
1663   if (!opl3_detect (base, hw_config->osp))
1664     return;
1665 
1666   opl3_init (0, base, hw_config->osp);
1667   request_region (base, 4, "OPL3/OPL2");
1668 }
1669 
1670 int
1671 probe_ms_sound (struct address_info *hw_config)
     /* [previous][next][first][last][top][bottom][index][help] */
1672 {
1673   unsigned char   tmp;
1674 
1675   DDB (printk ("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
1676 
1677   if (check_region (hw_config->io_base, 8))
1678     {
1679       printk ("MSS: I/O port conflict\n");
1680       return 0;
1681     }
1682 
1683   if (hw_config->card_subtype == 1)     /* Has no IRQ/DMA registers */
1684     {
1685       /* check_opl3(0x388, hw_config); */
1686       return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1687     }
1688 
1689 #if defined(CONFIG_AEDSP16) && defined(AEDSP16_MSS)
1690   /*
1691      * Initialize Audio Excel DSP 16 to MSS: before any operation
1692      * we must enable MSS I/O ports.
1693    */
1694 
1695   InitAEDSP16_MSS (hw_config);
1696 #endif
1697 
1698   /*
1699      * Check if the IO port returns valid signature. The original MS Sound
1700      * system returns 0x04 while some cards (AudioTriX Pro for example)
1701      * return 0x00 or 0x0f.
1702    */
1703 
1704   if ((tmp = inb (hw_config->io_base + 3)) == 0xff)     /* Bus float */
1705     {
1706       DDB (printk ("I/O address is inactive (%x)\n", tmp));
1707       return 0;
1708     }
1709   if ((tmp & 0x3f) != 0x04 &&
1710       (tmp & 0x3f) != 0x0f &&
1711       (tmp & 0x3f) != 0x00)
1712     {
1713       DDB (printk ("No MSS signature detected on port 0x%x (0x%x)\n",
1714                    hw_config->io_base, inb (hw_config->io_base + 3)));
1715       return 0;
1716     }
1717 
1718   if (hw_config->irq > 11)
1719     {
1720       printk ("MSS: Bad IRQ %d\n", hw_config->irq);
1721       return 0;
1722     }
1723 
1724   if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
1725     {
1726       printk ("MSS: Bad DMA %d\n", hw_config->dma);
1727       return 0;
1728     }
1729 
1730   /*
1731      * Check that DMA0 is not in use with a 8 bit board.
1732    */
1733 
1734   if (hw_config->dma == 0 && inb (hw_config->io_base + 3) & 0x80)
1735     {
1736       printk ("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1737       return 0;
1738     }
1739 
1740   if (hw_config->irq > 7 && hw_config->irq != 9 && inb (hw_config->io_base + 3) & 0x80)
1741     {
1742       printk ("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1743       return 0;
1744     }
1745 
1746   return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1747 }
1748 
1749 long
1750 attach_ms_sound (long mem_start, struct address_info *hw_config)
     /* [previous][next][first][last][top][bottom][index][help] */
1751 {
1752   static char     interrupt_bits[12] =
1753   {
1754     -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1755   };
1756   char            bits;
1757 
1758   static char     dma_bits[4] =
1759   {
1760     1, 2, 0, 3
1761   };
1762 
1763   int             config_port = hw_config->io_base + 0;
1764   int             version_port = hw_config->io_base + 3;
1765 
1766   if (!ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp))
1767     return mem_start;
1768 
1769   if (hw_config->card_subtype == 1)     /* Has no IRQ/DMA registers */
1770     {
1771       ad1848_init ("MS Sound System", hw_config->io_base + 4,
1772                    hw_config->irq,
1773                    hw_config->dma,
1774                    hw_config->dma2, 0, hw_config->osp);
1775       request_region (hw_config->io_base, 4, "WSS config");
1776       return mem_start;
1777     }
1778 
1779   /*
1780      * Set the IRQ and DMA addresses.
1781    */
1782 
1783   bits = interrupt_bits[hw_config->irq];
1784   if (bits == -1)
1785     return mem_start;
1786 
1787   outb (bits | 0x40, config_port);
1788   if ((inb (version_port) & 0x40) == 0)
1789     printk ("[IRQ Conflict?]");
1790 
1791   outb (bits | dma_bits[hw_config->dma], config_port);  /* Write IRQ+DMA setup */
1792 
1793   ad1848_init ("MS Sound System", hw_config->io_base + 4,
1794                hw_config->irq,
1795                hw_config->dma,
1796                hw_config->dma, 0, hw_config->osp);
1797   request_region (hw_config->io_base, 4, "WSS config");
1798   return mem_start;
1799 }
1800 
1801 void
1802 unload_ms_sound (struct address_info *hw_config)
     /* [previous][next][first][last][top][bottom][index][help] */
1803 {
1804   ad1848_unload (hw_config->io_base + 4,
1805                  hw_config->irq,
1806                  hw_config->dma,
1807                  hw_config->dma, 0);
1808   release_region (hw_config->io_base, 4);
1809 }
1810 
1811 /*
1812  * WSS compatible PnP codec support
1813  */
1814 
1815 int
1816 probe_pnp_ad1848 (struct address_info *hw_config)
     /* [previous][next][first][last][top][bottom][index][help] */
1817 {
1818   return ad1848_detect (hw_config->io_base, NULL, hw_config->osp);
1819 }
1820 
1821 long
1822 attach_pnp_ad1848 (long mem_start, struct address_info *hw_config)
     /* [previous][next][first][last][top][bottom][index][help] */
1823 {
1824 
1825   ad1848_init (hw_config->name, hw_config->io_base,
1826                hw_config->irq,
1827                hw_config->dma,
1828                hw_config->dma2, 0, hw_config->osp);
1829   return mem_start;
1830 }
1831 
1832 void
1833 unload_pnp_ad1848 (struct address_info *hw_config)
     /* [previous][next][first][last][top][bottom][index][help] */
1834 {
1835   ad1848_unload (hw_config->io_base,
1836                  hw_config->irq,
1837                  hw_config->dma,
1838                  hw_config->dma2, 0);
1839   release_region (hw_config->io_base, 4);
1840 }
1841 
1842 #ifdef CONFIG_SEQUENCER
1843 /*
1844  * Timer stuff (for /dev/music).
1845  */
1846 
1847 static unsigned int current_interval = 0;
1848 
1849 static unsigned int
1850 ad1848_tmr_start (int dev, unsigned int usecs)
     /* [previous][next][first][last][top][bottom][index][help] */
1851 {
1852   unsigned long   flags;
1853   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1854   unsigned long   xtal_nsecs;   /* nanoseconds per xtal oscillaror tick */
1855   unsigned long   divider;
1856 
1857   save_flags (flags);
1858   cli ();
1859 
1860 /*
1861  * Length of the timer interval (in nanoseconds) depends on the
1862  * selected crystal oscillator. Check this from bit 0x01 of I8.
1863  *
1864  * AD1845 has just one oscillator which has cycle time of 10.050 us
1865  * (when a 24.576 MHz xtal oscillator is used).
1866  *
1867  * Convert requested interval to nanoseconds before computing
1868  * the timer divider.
1869  */
1870 
1871   if (devc->mode == MD_1845)
1872     xtal_nsecs = 10050;
1873   else if (ad_read (devc, 8) & 0x01)
1874     xtal_nsecs = 9920;
1875   else
1876     xtal_nsecs = 9969;
1877 
1878   divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
1879 
1880   if (divider < 100)            /* Don't allow shorter intervals than about 1ms */
1881     divider = 100;
1882 
1883   if (divider > 65535)          /* Overflow check */
1884     divider = 65535;
1885 
1886   ad_write (devc, 21, (divider >> 8) & 0xff);   /* Set upper bits */
1887   ad_write (devc, 20, divider & 0xff);  /* Set lower bits */
1888   ad_write (devc, 16, ad_read (devc, 16) | 0x40);       /* Start the timer */
1889   devc->timer_running = 1;
1890   restore_flags (flags);
1891 
1892   return current_interval = (divider * xtal_nsecs + 500) / 1000;
1893 }
1894 
1895 static void
1896 ad1848_tmr_reprogram (int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1897 {
1898 /*
1899  *    Audio driver has changed sampling rate so that a different xtal
1900  *      oscillator was selected. We have to reprogram the timer rate.
1901  */
1902 
1903   ad1848_tmr_start (dev, current_interval);
1904   sound_timer_syncinterval (current_interval);
1905 }
1906 
1907 static void
1908 ad1848_tmr_disable (int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1909 {
1910   unsigned long   flags;
1911   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1912 
1913   save_flags (flags);
1914   cli ();
1915   ad_write (devc, 16, ad_read (devc, 16) & ~0x40);
1916   devc->timer_running = 0;
1917   restore_flags (flags);
1918 }
1919 
1920 static void
1921 ad1848_tmr_restart (int dev)
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1922 {
1923   unsigned long   flags;
1924   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1925 
1926   if (current_interval == 0)
1927     return;
1928 
1929   save_flags (flags);
1930   cli ();
1931   ad_write (devc, 16, ad_read (devc, 16) | 0x40);
1932   devc->timer_running = 1;
1933   restore_flags (flags);
1934 }
1935 
1936 static struct sound_lowlev_timer ad1848_tmr =
1937 {
1938   0,
1939   ad1848_tmr_start,
1940   ad1848_tmr_disable,
1941   ad1848_tmr_restart
1942 };
1943 
1944 static int
1945 ad1848_tmr_install (int dev)
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1946 {
1947 
1948   if (timer_installed != -1)
1949     return 0;                   /* Don't install another timer */
1950 
1951   timer_installed = ad1848_tmr.dev = dev;
1952   sound_timer_init (&ad1848_tmr, audio_devs[dev]->name);
1953 
1954   return 1;
1955 }
1956 #endif
1957 #endif

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