| tag | line | file | source code |
|---|
| NCR5380_read | 365 | drivers/scsi/NCR5380.c | data = NCR5380_read(CURRENT_SCSI_DATA_REG); |
| NCR5380_read | 366 | drivers/scsi/NCR5380.c | status = NCR5380_read(STATUS_REG); |
| NCR5380_read | 367 | drivers/scsi/NCR5380.c | mr = NCR5380_read(MODE_REG); |
| NCR5380_read | 368 | drivers/scsi/NCR5380.c | icr = NCR5380_read(INITIATOR_COMMAND_REG); |
| NCR5380_read | 369 | drivers/scsi/NCR5380.c | basr = NCR5380_read(BUS_AND_STATUS_REG); |
| NCR5380_read | 412 | drivers/scsi/NCR5380.c | status = NCR5380_read(STATUS_REG); |
| NCR5380_read | 858 | drivers/scsi/NCR5380.c | for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && |
| NCR5380_read | 867 | drivers/scsi/NCR5380.c | while (jiffies < timeout && (NCR5380_read(STATUS_REG) & SR_BSY)); |
| NCR5380_read | 1140 | drivers/scsi/NCR5380.c | basr = NCR5380_read(BUS_AND_STATUS_REG); |
| NCR5380_read | 1146 | drivers/scsi/NCR5380.c | if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == |
| NCR5380_read | 1154 | drivers/scsi/NCR5380.c | (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1159 | drivers/scsi/NCR5380.c | (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1160 | drivers/scsi/NCR5380.c | } else if ((NCR5380_read(STATUS_REG) & SR_RST) == SR_RST) { |
| NCR5380_read | 1164 | drivers/scsi/NCR5380.c | (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1178 | drivers/scsi/NCR5380.c | if ((NCR5380_read(MODE_REG) & MR_DMA) && ((basr & |
| NCR5380_read | 1192 | drivers/scsi/NCR5380.c | (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1197 | drivers/scsi/NCR5380.c | while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK |
| NCR5380_read | 1205 | drivers/scsi/NCR5380.c | while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK); |
| NCR5380_read | 1213 | drivers/scsi/NCR5380.c | printk("scsi : unknown interrupt, BASR 0x%X, MR 0x%X, SR 0x%x\n", basr, NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG)); |
| NCR5380_read | 1215 | drivers/scsi/NCR5380.c | (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1297 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_PROGRESS) |
| NCR5380_read | 1309 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_PROGRESS)); |
| NCR5380_read | 1328 | drivers/scsi/NCR5380.c | if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) || |
| NCR5380_read | 1329 | drivers/scsi/NCR5380.c | (NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_higher_mask) || |
| NCR5380_read | 1330 | drivers/scsi/NCR5380.c | (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST)) { |
| NCR5380_read | 1343 | drivers/scsi/NCR5380.c | if (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) { |
| NCR5380_read | 1434 | drivers/scsi/NCR5380.c | while ((jiffies < timeout) && !(NCR5380_read(STATUS_REG) & |
| NCR5380_read | 1437 | drivers/scsi/NCR5380.c | if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == |
| NCR5380_read | 1457 | drivers/scsi/NCR5380.c | if (!(NCR5380_read(STATUS_REG) & SR_BSY)) { |
| NCR5380_read | 1502 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(STATUS_REG) & SR_REQ) && jiffies < timeout); |
| NCR5380_read | 1511 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(STATUS_REG) & SR_REQ)); |
| NCR5380_read | 1615 | drivers/scsi/NCR5380.c | while (!((tmp = NCR5380_read(STATUS_REG)) & SR_REQ)); |
| NCR5380_read | 1634 | drivers/scsi/NCR5380.c | *d = NCR5380_read(CURRENT_SCSI_DATA_REG); |
| NCR5380_read | 1670 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 1701 | drivers/scsi/NCR5380.c | tmp = NCR5380_read(STATUS_REG); |
| NCR5380_read | 1719 | drivers/scsi/NCR5380.c | PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); |
| NCR5380_read | 1755 | drivers/scsi/NCR5380.c | while (!(tmp = NCR5380_read(STATUS_REG)) & SR_REQ); |
| NCR5380_read | 1762 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 1819 | drivers/scsi/NCR5380.c | if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) { |
| NCR5380_read | 1865 | drivers/scsi/NCR5380.c | printk("scsi%d : mode reg = 0x%X\n", instance->host_no, NCR5380_read(MODE_REG)); |
| NCR5380_read | 1898 | drivers/scsi/NCR5380.c | tmp = NCR5380_read(BUS_AND_STATUS_REG); |
| NCR5380_read | 1941 | drivers/scsi/NCR5380.c | if (((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH|BASR_ACK)) == |
| NCR5380_read | 1943 | drivers/scsi/NCR5380.c | saved_data = NCR5380_read(INPUT_DATA_REGISTER); |
| NCR5380_read | 1949 | drivers/scsi/NCR5380.c | while (((tmp = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_ACK) || |
| NCR5380_read | 1950 | drivers/scsi/NCR5380.c | (NCR5380_read(STATUS_REG) & SR_REQ)) { |
| NCR5380_read | 1959 | drivers/scsi/NCR5380.c | instance->host_no, tmp, NCR5380_read(STATUS_REG)); |
| NCR5380_read | 1969 | drivers/scsi/NCR5380.c | *phase = NCR5380_read(STATUS_REG) & PHASE_MASK; |
| NCR5380_read | 2032 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)); |
| NCR5380_read | 2034 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 2035 | drivers/scsi/NCR5380.c | d[c - 1] = NCR5380_read(INPUT_DATA_REG); |
| NCR5380_read | 2052 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(BUS_AND_STATUS_REG) & |
| NCR5380_read | 2053 | drivers/scsi/NCR5380.c | BASR_DRQ) && (NCR5380_read(BUS_AND_STATUS_REG) & |
| NCR5380_read | 2056 | drivers/scsi/NCR5380.c | if (NCR5380_read(STATUS_REG) & SR_REQ) { |
| NCR5380_read | 2058 | drivers/scsi/NCR5380.c | !(NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK); |
| NCR5380_read | 2060 | drivers/scsi/NCR5380.c | for (; timeout && (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 2075 | drivers/scsi/NCR5380.c | if (NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT) { |
| NCR5380_read | 2087 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)); |
| NCR5380_read | 2105 | drivers/scsi/NCR5380.c | if (NCR5380_read(BUS_AND_STATUS_REG) & BASR_IRQ) { |
| NCR5380_read | 2109 | drivers/scsi/NCR5380.c | NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 2117 | drivers/scsi/NCR5380.c | *phase = (NCR5380_read(STATUS_REG & PHASE_MASK)); |
| NCR5380_read | 2162 | drivers/scsi/NCR5380.c | tmp = NCR5380_read(STATUS_REG); |
| NCR5380_read | 2178 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 2399 | drivers/scsi/NCR5380.c | while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected) |
| NCR5380_read | 2440 | drivers/scsi/NCR5380.c | while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected) |
| NCR5380_read | 2652 | drivers/scsi/NCR5380.c | target_mask = NCR5380_read(CURRENT_SCSI_DATA_REG) & ~(hostdata->id_mask); |
| NCR5380_read | 2669 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_SEL); |
| NCR5380_read | 2676 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(STATUS_REG) & SR_REQ)); |
| NCR5380_read | 2784 | drivers/scsi/NCR5380.c | while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK); |
| NCR5380_read | 2846 | drivers/scsi/NCR5380.c | NCR5380_read(BUS_AND_STATUS_REG), NCR5380_read(STATUS_REG)); |
| NCR5380_read | 345 | drivers/scsi/g_NCR5380.c | if ((bl=NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { |
| NCR5380_read | 356 | drivers/scsi/g_NCR5380.c | if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { |
| NCR5380_read | 366 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) |
| NCR5380_read | 374 | drivers/scsi/g_NCR5380.c | dst[start+i] = NCR5380_read(C400_HOST_BUFFER); |
| NCR5380_read | 386 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) |
| NCR5380_read | 394 | drivers/scsi/g_NCR5380.c | dst[start+i] = NCR5380_read(C400_HOST_BUFFER); |
| NCR5380_read | 406 | drivers/scsi/g_NCR5380.c | if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) |
| NCR5380_read | 419 | drivers/scsi/g_NCR5380.c | if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) |
| NCR5380_read | 427 | drivers/scsi/g_NCR5380.c | NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 448 | drivers/scsi/g_NCR5380.c | if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { |
| NCR5380_read | 453 | drivers/scsi/g_NCR5380.c | if ((bl=NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { |
| NCR5380_read | 468 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) |
| NCR5380_read | 488 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) |
| NCR5380_read | 516 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) |
| NCR5380_read | 525 | drivers/scsi/g_NCR5380.c | while (!(i = NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) |
| NCR5380_read | 536 | drivers/scsi/g_NCR5380.c | if (!((i=NCR5380_read(BUS_AND_STATUS_REG)) & BASR_END_DMA_TRANSFER)) |
| NCR5380_read | 547 | drivers/scsi/g_NCR5380.c | if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) { |
| NCR5380_read | 555 | drivers/scsi/g_NCR5380.c | while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) |
| NCR5380_read | 225 | drivers/scsi/pas16.c | NCR5380_read( RESET_PARITY_INTERRUPT_REG ); |
| NCR5380_read | 301 | drivers/scsi/pas16.c | if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */ |
| NCR5380_read | 304 | drivers/scsi/pas16.c | if( NCR5380_read( MODE_REG ) != 0x00 ) |