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1 /*
2 * linux/drivers/block/triton.c Version 1.06 Feb 6, 1996
3 *
4 * Copyright (c) 1995-1996 Mark Lord
5 * May be copied or modified under the terms of the GNU General Public License
6 */
7
8 /*
9 * This module provides support for the Bus Master IDE DMA function
10 * of the Intel PCI Triton chipset (82371FB).
11 *
12 * DMA is currently supported only for hard disk drives (not cdroms).
13 *
14 * Support for cdroms will likely be added at a later date,
15 * after broader experience has been obtained with hard disks.
16 *
17 * Up to four drives may be enabled for DMA, and the Triton chipset will
18 * (hopefully) arbitrate the PCI bus among them. Note that the 82371FB chip
19 * provides a single "line buffer" for the BM IDE function, so performance of
20 * multiple (two) drives doing DMA simultaneously will suffer somewhat,
21 * as they contest for that resource bottleneck. This is handled transparently
22 * inside the 82371FB chip.
23 *
24 * By default, DMA support is prepared for use, but is currently enabled only
25 * for drives which support multi-word DMA mode2 (mword2), or which are
26 * recognized as "good" (see table below). Drives with only mode0 or mode1
27 * (single or multi) DMA should also work with this chipset/driver (eg. MC2112A)
28 * but are not enabled by default. Use "hdparm -i" to view modes supported
29 * by a given drive.
30 *
31 * The hdparm-2.4 (or later) utility can be used for manually enabling/disabling
32 * DMA support, but must be (re-)compiled against this kernel version or later.
33 *
34 * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
35 * If problems arise, ide.c will disable DMA operation after a few retries.
36 * This error recovery mechanism works and has been extremely well exercised.
37 *
38 * IDE drives, depending on their vintage, may support several different modes
39 * of DMA operation. The boot-time modes are indicated with a "*" in
40 * the "hdparm -i" listing, and can be changed with *knowledgeable* use of
41 * the "hdparm -X" feature. There is seldom a need to do this, as drives
42 * normally power-up with their "best" PIO/DMA modes enabled.
43 *
44 * Testing was done with an ASUS P55TP4XE/100 system and the following drives:
45 *
46 * Quantum Fireball 1080A (1Gig w/83kB buffer), DMA mode2, PIO mode4.
47 * - DMA mode2 works well (7.4MB/sec), despite the tiny on-drive buffer.
48 * - This drive also does PIO mode4, at about the same speed as DMA mode2.
49 * An awesome drive for the price!
50 *
51 * Fujitsu M1606TA (1Gig w/256kB buffer), DMA mode2, PIO mode4.
52 * - DMA mode2 gives horrible performance (1.6MB/sec), despite the good
53 * size of the on-drive buffer and a boasted 10ms average access time.
54 * - PIO mode4 was better, but peaked at a mere 4.5MB/sec.
55 *
56 * Micropolis MC2112A (1Gig w/508kB buffer), drive pre-dates EIDE and ATA2.
57 * - DMA works fine (2.2MB/sec), probably due to the large on-drive buffer.
58 * - This older drive can also be tweaked for fastPIO (3.7MB/sec) by using
59 * maximum clock settings (5,4) and setting all flags except prefetch.
60 *
61 * Western Digital AC31000H (1Gig w/128kB buffer), DMA mode1, PIO mode3.
62 * - DMA does not work reliably. The drive appears to be somewhat tardy
63 * in deasserting DMARQ at the end of a sector. This is evident in
64 * the observation that WRITEs work most of the time, depending on
65 * cache-buffer occupancy, but multi-sector reads seldom work.
66 *
67 * Testing was done with a Gigabyte GA-586 ATE system and the following drive:
68 * (Uwe Bonnes - bon@elektron.ikp.physik.th-darmstadt.de)
69 *
70 * Western Digital AC31600H (1.6Gig w/128kB buffer), DMA mode2, PIO mode4.
71 * - much better than its 1Gig cousin, this drive is reported to work
72 * very well with DMA (7.3MB/sec).
73 *
74 * Other drives:
75 *
76 * Maxtor 7540AV (515Meg w/32kB buffer), DMA modes mword0/sword2, PIO mode3.
77 * - a budget drive, with budget performance, around 3MB/sec.
78 *
79 * Western Digital AC2850F (814Meg w/64kB buffer), DMA mode1, PIO mode3.
80 * - another "caviar" drive, similar to the AC31000, except that this one
81 * worked with DMA in at least one system. Throughput is about 3.8MB/sec
82 * for both DMA and PIO.
83 *
84 * Conner CFS850A (812Meg w/64kB buffer), DMA mode2, PIO mode4.
85 * - like most Conner models, this drive proves that even a fast interface
86 * cannot improve slow media. Both DMA and PIO peak around 3.5MB/sec.
87 *
88 * If you have any drive models to add, email your results to: mlord@bnr.ca
89 * Keep an eye on /var/adm/messages for "DMA disabled" messages.
90 *
91 * Some people have reported trouble with Intel Zappa motherboards.
92 * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
93 * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
94 * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this).
95 *
96 * And, yes, Intel Zappa boards really *do* use the Triton IDE ports.
97 */
98 #include <linux/types.h>
99 #include <linux/kernel.h>
100 #include <linux/timer.h>
101 #include <linux/mm.h>
102 #include <linux/ioport.h>
103 #include <linux/interrupt.h>
104 #include <linux/blkdev.h>
105 #include <linux/hdreg.h>
106 #include <linux/pci.h>
107 #include <linux/bios32.h>
108
109 #include <asm/io.h>
110 #include <asm/dma.h>
111
112 #include "ide.h"
113
114 /*
115 * good_dma_drives() lists the model names (from "hdparm -i")
116 * of drives which do not support mword2 DMA but which are
117 * known to work fine with this interface under Linux.
118 */
119 const char *good_dma_drives[] = {"Micropolis 2112A"};
120
121 /*
122 * Our Physical Region Descriptor (PRD) table should be large enough
123 * to handle the biggest I/O request we are likely to see. Since requests
124 * can have no more than 256 sectors, and since the typical blocksize is
125 * two sectors, we could get by with a limit of 128 entries here for the
126 * usual worst case. Most requests seem to include some contiguous blocks,
127 * further reducing the number of table entries required.
128 *
129 * The driver reverts to PIO mode for individual requests that exceed
130 * this limit (possible with 512 byte blocksizes, eg. MSDOS f/s), so handling
131 * 100% of all crazy scenarios here is not necessary.
132 *
133 * As it turns out though, we must allocate a full 4KB page for this,
134 * so the two PRD tables (ide0 & ide1) will each get half of that,
135 * allowing each to have about 256 entries (8 bytes each) from this.
136 */
137 #define PRD_BYTES 8
138 #define PRD_ENTRIES (PAGE_SIZE / (2 * PRD_BYTES))
139
140 /*
141 * dma_intr() is the handler for disk read/write DMA interrupts
142 */
143 static void dma_intr (ide_drive_t *drive)
/* ![[next]](../icons/right.png)
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*/
144 {
145 byte stat, dma_stat;
146 int i;
147 struct request *rq = HWGROUP(drive)->rq;
148 unsigned short dma_base = HWIF(drive)->dma_base;
149
150 dma_stat = inb(dma_base+2); /* get DMA status */
151 outb(inb(dma_base)&~1, dma_base); /* stop DMA operation */
152 stat = GET_STAT(); /* get drive status */
153 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
154 if ((dma_stat & 7) == 4) { /* verify good DMA status */
155 rq = HWGROUP(drive)->rq;
156 for (i = rq->nr_sectors; i > 0;) {
157 i -= rq->current_nr_sectors;
158 ide_end_request(1, HWGROUP(drive));
159 }
160 return;
161 }
162 printk("%s: bad DMA status: 0x%02x\n", drive->name, dma_stat);
163 }
164 sti();
165 ide_error(drive, "dma_intr", stat);
166 }
167
168 /*
169 * build_dmatable() prepares a dma request.
170 * Returns 0 if all went okay, returns 1 otherwise.
171 */
172 static int build_dmatable (ide_drive_t *drive)
/* ![[previous]](../icons/left.png)
*/
173 {
174 struct request *rq = HWGROUP(drive)->rq;
175 struct buffer_head *bh = rq->bh;
176 unsigned long size, addr, *table = HWIF(drive)->dmatable;
177 unsigned int count = 0;
178
179 do {
180 /*
181 * Determine addr and size of next buffer area. We assume that
182 * individual virtual buffers are always composed linearly in
183 * physical memory. For example, we assume that any 8kB buffer
184 * is always composed of two adjacent physical 4kB pages rather
185 * than two possibly non-adjacent physical 4kB pages.
186 */
187 if (bh == NULL) { /* paging requests have (rq->bh == NULL) */
188 addr = virt_to_bus (rq->buffer);
189 size = rq->nr_sectors << 9;
190 } else {
191 /* group sequential buffers into one large buffer */
192 addr = virt_to_bus (bh->b_data);
193 size = bh->b_size;
194 while ((bh = bh->b_reqnext) != NULL) {
195 if ((addr + size) != virt_to_bus (bh->b_data))
196 break;
197 size += bh->b_size;
198 }
199 }
200
201 /*
202 * Fill in the dma table, without crossing any 64kB boundaries.
203 * We assume 16-bit alignment of all blocks.
204 */
205 while (size) {
206 if (++count >= PRD_ENTRIES) {
207 printk("%s: DMA table too small\n", drive->name);
208 return 1; /* revert to PIO for this request */
209 } else {
210 unsigned long bcount = 0x10000 - (addr & 0xffff);
211 if (bcount > size)
212 bcount = size;
213 *table++ = addr;
214 *table++ = bcount;
215 addr += bcount;
216 size -= bcount;
217 }
218 }
219 } while (bh != NULL);
220 if (count) {
221 *--table |= 0x80000000; /* set End-Of-Table (EOT) bit */
222 return 0;
223 }
224 printk("%s: empty DMA table?\n", drive->name);
225 return 1; /* let the PIO routines handle this weirdness */
226 }
227
228 static int config_drive_for_dma (ide_drive_t *drive)
/* */
229 {
230 const char **list;
231
232 struct hd_driveid *id = drive->id;
233 if (id && (id->capability & 1)) {
234 /* Enable DMA on any drive that supports mword2 DMA */
235 if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
236 drive->using_dma = 1;
237 return 0; /* DMA enabled */
238 }
239 /* Consult the list of known "good" drives */
240 list = good_dma_drives;
241 while (*list) {
242 if (!strcmp(*list++,id->model)) {
243 drive->using_dma = 1;
244 return 0; /* DMA enabled */
245 }
246 }
247 }
248 return 1; /* DMA not enabled */
249 }
250
251 /*
252 * triton_dmaproc() initiates/aborts DMA read/write operations on a drive.
253 *
254 * The caller is assumed to have selected the drive and programmed the drive's
255 * sector address using CHS or LBA. All that remains is to prepare for DMA
256 * and then issue the actual read/write DMA/PIO command to the drive.
257 *
258 * Returns 0 if all went well.
259 * Returns 1 if DMA read/write could not be started, in which case
260 * the caller should revert to PIO for the current request.
261 */
262 static int triton_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
/* */
263 {
264 unsigned long dma_base = HWIF(drive)->dma_base;
265 unsigned int reading = (1 << 3);
266
267 switch (func) {
268 case ide_dma_abort:
269 outb(inb(dma_base)&~1, dma_base); /* stop DMA */
270 return 0;
271 case ide_dma_check:
272 return config_drive_for_dma (drive);
273 case ide_dma_write:
274 reading = 0;
275 case ide_dma_read:
276 break;
277 default:
278 printk("triton_dmaproc: unsupported func: %d\n", func);
279 return 1;
280 }
281 if (build_dmatable (drive))
282 return 1;
283 outl(virt_to_bus (HWIF(drive)->dmatable), dma_base + 4); /* PRD table */
284 outb(reading, dma_base); /* specify r/w */
285 outb(0x26, dma_base+2); /* clear status bits */
286 ide_set_handler(drive, &dma_intr, WAIT_CMD); /* issue cmd to drive */
287 OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
288 outb(inb(dma_base)|1, dma_base); /* begin DMA */
289 return 0;
290 }
291
292 /*
293 * print_triton_drive_flags() displays the currently programmed options
294 * in the Triton chipset for a given drive.
295 *
296 * If fastDMA is "no", then slow ISA timings are used for DMA data xfers.
297 * If fastPIO is "no", then slow ISA timings are used for PIO data xfers.
298 * If IORDY is "no", then IORDY is assumed to always be asserted.
299 * If PreFetch is "no", then data pre-fetch/post are not used.
300 *
301 * When "fastPIO" and/or "fastDMA" are "yes", then faster PCI timings and
302 * back-to-back 16-bit data transfers are enabled, using the sample_CLKs
303 * and recovery_CLKs (PCI clock cycles) timing parameters for that interface.
304 */
305 static void print_triton_drive_flags (unsigned int unit, byte flags)
/* */
306 {
307 printk(" %s ", unit ? "slave :" : "master:");
308 printk( "fastDMA=%s", (flags&9) ? "on " : "off");
309 printk(" PreFetch=%s", (flags&4) ? "on " : "off");
310 printk(" IORDY=%s", (flags&2) ? "on " : "off");
311 printk(" fastPIO=%s\n", ((flags&9)==1) ? "on " : "off");
312 }
313
314 static void init_triton_dma (ide_hwif_t *hwif, unsigned short base)
/* */
315 {
316 static unsigned long dmatable = 0;
317
318 printk(" %s: BusMaster DMA at 0x%04x-0x%04x", hwif->name, base, base+7);
319 if (check_region(base, 8)) {
320 printk(" -- ERROR, PORTS ALREADY IN USE");
321 } else {
322 request_region(base, 8, "triton DMA");
323 hwif->dma_base = base;
324 if (!dmatable) {
325 /*
326 * Since we know we are on a PCI bus, we could
327 * actually use __get_free_pages() here instead
328 * of __get_dma_pages() -- no ISA limitations.
329 */
330 dmatable = __get_dma_pages(GFP_KERNEL, 0);
331 }
332 if (dmatable) {
333 hwif->dmatable = (unsigned long *) dmatable;
334 dmatable += (PRD_ENTRIES * PRD_BYTES);
335 outl(virt_to_bus(hwif->dmatable), base + 4);
336 hwif->dmaproc = &triton_dmaproc;
337 }
338 }
339 printk("\n");
340 }
341
342 /*
343 * calc_mode() returns the ATA PIO mode number, based on the number
344 * of cycle clks passed in. Assumes 33Mhz bus operation (30ns per clk).
345 */
346 byte calc_mode (byte clks)
/* */
347 {
348 if (clks == 3) return 5;
349 if (clks == 4) return 4;
350 if (clks < 6) return 3;
351 if (clks < 8) return 2;
352 if (clks < 13) return 1;
353 return 0;
354 }
355
356 /*
357 * ide_init_triton() prepares the IDE driver for DMA operation.
358 * This routine is called once, from ide.c during driver initialization,
359 * for each triton chipset which is found (unlikely to be more than one).
360 */
361 void ide_init_triton (byte bus, byte fn)
/* ![[last]](../icons/n_last.png)
*/
362 {
363 int rc = 0, h;
364 int dma_enabled = 0;
365 unsigned short bmiba, pcicmd;
366 unsigned int timings;
367
368 printk("ide: Triton BM-IDE on PCI bus %d function %d\n", bus, fn);
369 /*
370 * See if IDE and BM-DMA features are enabled:
371 */
372 if ((rc = pcibios_read_config_word(bus, fn, 0x04, &pcicmd)))
373 goto quit;
374 if ((pcicmd & 1) == 0) {
375 printk("ide: Triton IDE ports are not enabled\n");
376 goto quit;
377 }
378 if ((pcicmd & 4) == 0) {
379 printk("ide: Triton BM-DMA feature is not enabled -- upgrade your BIOS\n");
380 } else {
381 /*
382 * Get the bmiba base address
383 */
384 if ((rc = pcibios_read_config_word(bus, fn, 0x20, &bmiba)))
385 goto quit;
386 bmiba &= 0xfff0; /* extract port base address */
387 dma_enabled = 1;
388 }
389
390 /*
391 * See if ide port(s) are enabled
392 */
393 if ((rc = pcibios_read_config_dword(bus, fn, 0x40, &timings)))
394 goto quit;
395 if (!(timings & 0x80008000)) {
396 printk("ide: neither Triton IDE port is enabled\n");
397 goto quit;
398 }
399
400 /*
401 * Save the dma_base port addr for each interface
402 */
403 for (h = 0; h < MAX_HWIFS; ++h) {
404 byte s_clks, r_clks;
405 ide_hwif_t *hwif = &ide_hwifs[h];
406 unsigned short time;
407 if (hwif->io_base == 0x1f0) {
408 time = timings & 0xffff;
409 if ((timings & 0x8000) == 0) /* interface enabled? */
410 continue;
411 hwif->chipset = ide_triton;
412 if (dma_enabled)
413 init_triton_dma(hwif, bmiba);
414 } else if (hwif->io_base == 0x170) {
415 time = timings >> 16;
416 if ((timings & 0x8000) == 0) /* interface enabled? */
417 continue;
418 hwif->chipset = ide_triton;
419 if (dma_enabled)
420 init_triton_dma(hwif, bmiba + 8);
421 } else
422 continue;
423 s_clks = ((~time >> 12) & 3) + 2;
424 r_clks = ((~time >> 8) & 3) + 1;
425 printk(" %s timing: (0x%04x) sample_CLKs=%d, recovery_CLKs=%d (PIO mode%d)\n",
426 hwif->name, time, s_clks, r_clks, calc_mode(s_clks+r_clks));
427 print_triton_drive_flags (0, time & 0xf);
428 print_triton_drive_flags (1, (time >> 4) & 0xf);
429 }
430
431 quit: if (rc) printk("ide: pcibios access failed - %s\n", pcibios_strerror(rc));
432 }
433
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*/