![[first]](../icons/first.png){kind=icon}
![[previous]](../icons/n_left.png){kind=icon}
![[next]](../icons/n_right.png){kind=icon}
![[last]](../icons/last.png){kind=icon}
![[top]](../icons/n_top.png){kind=icon}
![[bottom]](../icons/bottom.png){kind=icon}
![[index]](../icons/index.png){kind=icon}
![[help]](../icons/help.png){kind=icon}
*/
1 /*
2 * Intel MP v1.1 specification support routines for multi-pentium
3 * hosts.
4 *
5 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
6 * Supported by Caldera http://www.caldera.com.
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * This code is released under the GNU public license version 2 or
11 * later.
12 *
13 * Fixes
14 * Felix Koop : NR_CPUS used properly
15 * Jose Renau : Handle single CPU case.
16 * Alan Cox : By repeated request 8) - Total BogoMIP report.
17 * Greg Wright : Fix for kernel stacks panic.
18 *
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/string.h>
23 #include <linux/config.h>
24 #include <linux/timer.h>
25 #include <linux/sched.h>
26 #include <linux/mm.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/delay.h>
29 #include <asm/i82489.h>
30 #include <linux/smp.h>
31 #include <asm/pgtable.h>
32 #include <asm/bitops.h>
33 #include <asm/pgtable.h>
34 #include <asm/smp.h>
35
36 extern void *vremap(unsigned long offset, unsigned long size); /* Linus hasnt put this in the headers yet */
37
38 static int smp_found_config=0; /* Have we found an SMP box */
39
40 unsigned long cpu_present_map = 0; /* Bitmask of existing CPU's */
41 int smp_num_cpus; /* Total count of live CPU's */
42 int smp_threads_ready=0; /* Set when the idlers are all forked */
43 volatile unsigned long cpu_callin_map[NR_CPUS] = {0,}; /* We always use 0 the rest is ready for parallel delivery */
44 volatile unsigned long smp_invalidate_needed; /* Used for the invalidate map thats also checked in the spinlock */
45 struct cpuinfo_x86 cpu_data[NR_CPUS]; /* Per cpu bogomips and other parameters */
46 static unsigned int num_processors = 1; /* Internal processor count */
47 static unsigned long io_apic_addr = 0; /* Address of the I/O apic (not yet used) */
48 unsigned char boot_cpu_id = 0; /* Processor that is doing the boot up */
49 static unsigned char *kstack_base,*kstack_end; /* Kernel stack list pointers */
50 static int smp_activated = 0; /* Tripped once we need to start cross invalidating */
51 static volatile int smp_commenced=0; /* Tripped when we start scheduling */
52 static unsigned char nlong=0; /* Apparent value for boot CPU */
53 unsigned char *apic_reg=((unsigned char *)&nlong)-0x20; /* Later set to the vremap() of the APIC */
54 unsigned long apic_retval; /* Just debugging the assembler.. */
55 unsigned char *kernel_stacks[NR_CPUS]; /* Kernel stack pointers for CPU's (debugging) */
56
57 static volatile unsigned char smp_cpu_in_msg[NR_CPUS]; /* True if this processor is sending an IPI */
58 static volatile unsigned long smp_msg_data; /* IPI data pointer */
59 static volatile int smp_src_cpu; /* IPI sender processor */
60 static volatile int smp_msg_id; /* Message being sent */
61
62 volatile unsigned long kernel_flag=0; /* Kernel spinlock */
63 volatile unsigned char active_kernel_processor = NO_PROC_ID; /* Processor holding kernel spinlock */
64 volatile unsigned long kernel_counter=0; /* Number of times the processor holds the lock */
65 volatile unsigned long syscall_count=0; /* Number of times the processor holds the syscall lock */
66
67 volatile unsigned long ipi_count; /* Number of IPI's delivered */
68 #ifdef __SMP_PROF__
69 volatile unsigned long smp_spins[NR_CPUS]={0}; /* Count interrupt spins */
70 volatile unsigned long smp_spins_syscall[NR_CPUS]={0}; /* Count syscall spins */
71 volatile unsigned long smp_spins_syscall_cur[NR_CPUS]={0};/* Count spins for the actual syscall */
72 volatile unsigned long smp_spins_sys_idle[NR_CPUS]={0}; /* Count spins for sys_idle */
73 volatile unsigned long smp_idle_count[1+NR_CPUS]={0,}; /* Count idle ticks */
74 #endif
75 #if defined (__SMP_PROF__)
76 volatile unsigned long smp_idle_map=0; /* Map for idle processors */
77 #endif
78
79
80 /*
81 * Checksum an MP configuration block.
82 */
83
84 static int mpf_checksum(unsigned char *mp, int len)
/* ![[next]](../icons/right.png)
![[first]](../icons/n_first.png)
![[top]](../icons/top.png)
*/
85 {
86 int sum=0;
87 while(len--)
88 sum+=*mp++;
89 return sum&0xFF;
90 }
91
92 /*
93 * Processor encoding in an MP configuration block
94 */
95
96 static char *mpc_family(int family,int model)
/* ![[previous]](../icons/left.png)
*/
97 {
98 static char n[32];
99 static char *model_defs[]=
100 {
101 "80486DX","80486DX",
102 "80486SX","80486DX/2 or 80487",
103 "80486SL","Intel5X2(tm)",
104 "Unknown","Unknown",
105 "80486DX/4"
106 };
107 if(family==0x5)
108 return("Pentium(tm)");
109 if(family==0x0F && model==0x0F)
110 return("Special controller");
111 if(family==0x04 && model<9)
112 return model_defs[model];
113 sprintf(n,"Unknown CPU [%d:%d]",family, model);
114 return n;
115 }
116
117 /*
118 * Read the MPC
119 */
120
121 static int smp_read_mpc(struct mp_config_table *mpc)
/* */
122 {
123 char str[16];
124 int count=sizeof(*mpc);
125 int apics=0;
126 unsigned char *mpt=((unsigned char *)mpc)+count;
127
128 if(memcmp(mpc->mpc_signature,MPC_SIGNATURE,4))
129 {
130 printk("Bad signature [%c%c%c%c].\n",
131 mpc->mpc_signature[0],
132 mpc->mpc_signature[1],
133 mpc->mpc_signature[2],
134 mpc->mpc_signature[3]);
135 return 1;
136 }
137 if(mpf_checksum((unsigned char *)mpc,mpc->mpc_length))
138 {
139 printk("Checksum error.\n");
140 return 1;
141 }
142 if(mpc->mpc_spec!=0x01)
143 {
144 printk("Unsupported version (%d)\n",mpc->mpc_spec);
145 return 1;
146 }
147 memcpy(str,mpc->mpc_oem,8);
148 str[8]=0;
149 printk("OEM ID: %s ",str);
150 memcpy(str,mpc->mpc_productid,12);
151 str[12]=0;
152 printk("Product ID: %s ",str);
153 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
154
155 /*
156 * Now process the configuration blocks.
157 */
158
159 while(count<mpc->mpc_length)
160 {
161 switch(*mpt)
162 {
163 case MP_PROCESSOR:
164 {
165 struct mpc_config_processor *m=
166 (struct mpc_config_processor *)mpt;
167 if(m->mpc_cpuflag&CPU_ENABLED)
168 {
169 printk("Processor #%d %s APIC version %d\n",
170 m->mpc_apicid,
171 mpc_family((m->mpc_cpufeature&
172 CPU_FAMILY_MASK)>>8,
173 (m->mpc_cpufeature&
174 CPU_MODEL_MASK)>>4),
175 m->mpc_apicver);
176 if(m->mpc_featureflag&(1<<0))
177 printk(" Floating point unit present.\n");
178 if(m->mpc_featureflag&(1<<7))
179 printk(" Machine Exception supported.\n");
180 if(m->mpc_featureflag&(1<<8))
181 printk(" 64 bit compare & exchange supported.\n");
182 if(m->mpc_featureflag&(1<<9))
183 printk(" Internal APIC present.\n");
184 if(m->mpc_cpuflag&CPU_BOOTPROCESSOR)
185 {
186 printk(" Bootup CPU\n");
187 boot_cpu_id=m->mpc_apicid;
188 nlong = boot_cpu_id<<24; /* Dummy 'self' for bootup */
189 }
190 else /* Boot CPU already counted */
191 num_processors++;
192
193 if(m->mpc_apicid>NR_CPUS)
194 printk("Processor #%d unused. (Max %d processors).\n",m->mpc_apicid, NR_CPUS);
195 else
196 cpu_present_map|=(1<<m->mpc_apicid);
197 }
198 mpt+=sizeof(*m);
199 count+=sizeof(*m);
200 break;
201 }
202 case MP_BUS:
203 {
204 struct mpc_config_bus *m=
205 (struct mpc_config_bus *)mpt;
206 memcpy(str,m->mpc_bustype,6);
207 str[6]=0;
208 printk("Bus #%d is %s\n",
209 m->mpc_busid,
210 str);
211 mpt+=sizeof(*m);
212 count+=sizeof(*m);
213 break;
214 }
215 case MP_IOAPIC:
216 {
217 struct mpc_config_ioapic *m=
218 (struct mpc_config_ioapic *)mpt;
219 if(m->mpc_flags&MPC_APIC_USABLE)
220 {
221 apics++;
222 printk("I/O APIC #%d Version %d at 0x%lX.\n",
223 m->mpc_apicid,m->mpc_apicver,
224 m->mpc_apicaddr);
225 io_apic_addr = m->mpc_apicaddr;
226 }
227 mpt+=sizeof(*m);
228 count+=sizeof(*m);
229 break;
230 }
231 case MP_INTSRC:
232 {
233 struct mpc_config_intsrc *m=
234 (struct mpc_config_intsrc *)mpt;
235
236 mpt+=sizeof(*m);
237 count+=sizeof(*m);
238 break;
239 }
240 case MP_LINTSRC:
241 {
242 struct mpc_config_intlocal *m=
243 (struct mpc_config_intlocal *)mpt;
244 mpt+=sizeof(*m);
245 count+=sizeof(*m);
246 break;
247 }
248 }
249 }
250 if(apics>1)
251 printk("Warning: Multiple APIC's not supported.\n");
252 return num_processors;
253 }
254
255 /*
256 * Scan the memory blocks for an SMP configuration block.
257 */
258
259 void smp_scan_config(unsigned long base, unsigned long length)
/* */
260 {
261 unsigned long *bp=(unsigned long *)base;
262 struct intel_mp_floating *mpf;
263
264 /* printk("Scan SMP from %p for %ld bytes.\n",
265 bp,length);*/
266 if(sizeof(*mpf)!=16)
267 printk("Error: MPF size\n");
268
269 while(length>0)
270 {
271 if(*bp==SMP_MAGIC_IDENT)
272 {
273 mpf=(struct intel_mp_floating *)bp;
274 if(mpf->mpf_length==1 &&
275 !mpf_checksum((unsigned char *)bp,16) &&
276 mpf->mpf_specification==1)
277 {
278 printk("Intel multiprocessing (MPv1.1) available.\n");
279 if(mpf->mpf_feature2&(1<<7))
280 printk(" IMCR and PIC mode supported.\n");
281 smp_found_config=1;
282 /*
283 * Now see if we need to read further.
284 */
285 if(mpf->mpf_feature1!=0)
286 {
287 num_processors=2;
288 printk("I/O APIC at 0xFEC00000.\n");
289 printk("Bus#0 is ");
290 }
291 switch(mpf->mpf_feature1)
292 {
293 case 1:
294 printk("ISA");
295 break;
296 case 2:
297 printk("EISA with no IRQ8 chaining");
298 break;
299 case 3:
300 printk("EISA");
301 break;
302 case 4:
303 printk("MCA");
304 break;
305 case 5:
306 printk("ISA\nBus#1 is PCI");
307 break;
308 case 6:
309 printk("EISA\nBus #1 is PCI");
310 break;
311 case 7:
312 printk("MCA\nBus #1 is PCI");
313 break;
314 case 0:
315 break;
316 default:
317 printk("???\nUnknown standard configuration %d\n",
318 mpf->mpf_feature1);
319 return;
320 }
321 /*
322 * Read the physical hardware table. If there isn't one
323 * the processors present are 0 and 1.
324 */
325 if(mpf->mpf_physptr)
326 smp_read_mpc((void *)mpf->mpf_physptr);
327 else
328 cpu_present_map=3;
329 printk("Processors: %d\n", num_processors);
330 }
331 }
332 bp+=4;
333 length-=16;
334 }
335 }
336
337 /*
338 * Trampoline 80x86 program as an array.
339 */
340
341 static unsigned char trampoline_data[]={
342 #include "trampoline.hex"
343 };
344
345 /*
346 * Currently trivial. Write the real->protected mode
347 * bootstrap into the page concerned. The caller
348 * has made sure its suitably aligned.
349 */
350
351 static void install_trampoline(unsigned char *mp)
/* */
352 {
353 memcpy(mp,trampoline_data,sizeof(trampoline_data));
354 }
355
356 /*
357 * We are called very early to get the low memory for the trampoline/kernel stacks
358 * This has to be done by mm/init.c to parcel us out nice low memory. We allocate
359 * the kernel stacks at 4K, 8K, 12K... currently (0-03FF is preserved for SMM and
360 * other things).
361 */
362
363 unsigned long smp_alloc_memory(unsigned long mem_base)
/* */
364 {
365 int size=(num_processors-1)*PAGE_SIZE; /* Number of stacks needed */
366 /*
367 * Our stacks have to be below the 1Mb line, and mem_base on entry
368 * is 4K aligned.
369 */
370
371 if(mem_base+size>=0x9F000)
372 panic("smp_alloc_memory: Insufficient low memory for kernel stacks.\n");
373 kstack_base=(void *)mem_base;
374 mem_base+=size;
375 kstack_end=(void *)mem_base;
376 return mem_base;
377 }
378
379 /*
380 * Hand out stacks one at a time.
381 */
382
383 static void *get_kernel_stack(void)
/* */
384 {
385 void *stack=kstack_base;
386 if(kstack_base>=kstack_end)
387 return NULL;
388 kstack_base+=PAGE_SIZE;
389 return stack;
390 }
391
392
393 /*
394 * The bootstrap kernel entry code has set these up. Save them for
395 * a given CPU
396 */
397
398 void smp_store_cpu_info(int id)
/* */
399 {
400 struct cpuinfo_x86 *c=&cpu_data[id];
401 c->hard_math=hard_math; /* Always assumed same currently */
402 c->x86=x86;
403 c->x86_model=x86_model;
404 c->x86_mask=x86_mask;
405 c->x86_capability=x86_capability;
406 c->fdiv_bug=fdiv_bug;
407 c->wp_works_ok=wp_works_ok; /* Always assumed the same currently */
408 c->hlt_works_ok=hlt_works_ok;
409 c->udelay_val=loops_per_sec;
410 strcpy(c->x86_vendor_id, x86_vendor_id);
411 }
412
413 /*
414 * Architecture specific routine called by the kernel just before init is
415 * fired off. This allows the BP to have everything in order [we hope].
416 * At the end of this all the AP's will hit the system scheduling and off
417 * we go. Each AP will load the system gdt's and jump through the kernel
418 * init into idle(). At this point the scheduler will one day take over
419 * and give them jobs to do. smp_callin is a standard routine
420 * we use to track CPU's as they power up.
421 */
422
423 void smp_commence(void)
/* */
424 {
425 /*
426 * Lets the callin's below out of their loop.
427 */
428 smp_commenced=1;
429 }
430
431 void smp_callin(void)
/* */
432 {
433 int cpuid=GET_APIC_ID(apic_read(APIC_ID));
434 unsigned long l;
435 /*
436 * Activate our APIC
437 */
438
439 /* printk("CALLIN %d\n",smp_processor_id());*/
440 l=apic_read(APIC_SPIV);
441 l|=(1<<8); /* Enable */
442 apic_write(APIC_SPIV,l);
443 sti();
444 /*
445 * Get our bogomips.
446 */
447 calibrate_delay();
448 /*
449 * Save our processor parameters
450 */
451 smp_store_cpu_info(cpuid);
452 /*
453 * Allow the master to continue.
454 */
455 set_bit(cpuid, &cpu_callin_map[0]);
456 /*
457 * Until we are ready for SMP scheduling
458 */
459 load_ldt(0);
460 /* printk("Testing faulting...\n");
461 *(long *)0=1; OOPS... */
462 local_invalidate();
463 while(!smp_commenced);
464 local_invalidate();
465 /* printk("Commenced..\n");*/
466
467 /* This assumes the processor id's are consecutive 0..n-1 - FIXME */
468 load_TR(cpuid);
469 /* while(1);*/
470 }
471
472 /*
473 * Cycle through the processors sending pentium IPI's to boot each.
474 */
475
476 void smp_boot_cpus(void)
/* */
477 {
478 int i=0;
479 int cpucount=0;
480 void *stack;
481 extern unsigned long init_user_stack[];
482
483 /*
484 * Map the local APIC into kernel space
485 */
486
487 /* Mapping on non-Intel conforming platforms is a bad move. */
488 if (1<cpu_present_map)
489 apic_reg = vremap(0xFEE00000,4096);
490
491
492 if(apic_reg == NULL)
493 panic("Unable to map local apic.\n");
494
495 /*
496 * Now scan the cpu present map and fire up anything we find.
497 */
498
499
500 kernel_stacks[boot_cpu_id]=(void *)init_user_stack; /* Set up for boot processor first */
501
502 smp_store_cpu_info(boot_cpu_id); /* Final full version of the data */
503
504 active_kernel_processor=boot_cpu_id;
505
506 for(i=0;i<NR_CPUS;i++)
507 {
508 if((cpu_present_map&(1<<i)) && i!=boot_cpu_id) /* Rebooting yourself is a bad move */
509 {
510 unsigned long cfg;
511 int timeout;
512
513 /*
514 * We need a kernel stack for each processor.
515 */
516
517 stack=get_kernel_stack(); /* We allocated these earlier */
518 if(stack==NULL)
519 panic("No memory for processor stacks.\n");
520 kernel_stacks[i]=stack;
521 install_trampoline(stack);
522
523 printk("Booting processor %d stack %p: ",i,stack); /* So we set whats up */
524
525 /*
526 * Enable the local APIC
527 */
528
529 cfg=apic_read(APIC_SPIV);
530 cfg|=(1<<8); /* Enable APIC */
531 apic_write(APIC_SPIV,cfg);
532
533 for(timeout=0;timeout<50000;timeout++)
534 {
535 /*
536 * This gunge sends an IPI (Inter Processor Interrupt) to the
537 * processor we wish to wake. When the startup IPI is received
538 * the target CPU does a real mode jump to the stack base.
539 *
540 * We do the following
541 *
542 * Time 0 : Send a STARTUP IPI (This is all that is needed).
543 * Time 20000 : Send an INIT IPI for broken boards.
544 * Time 20001 : Send a second STARTUP IPI for broken boards.
545 *
546 * We can't just do INIT/STARTUP - that breaks the correctly
547 * implemented ASUS boards.
548 */
549
550 if(timeout==20000)
551 {
552 cfg=apic_read(APIC_ICR2);
553 cfg&=0x00FFFFFF;
554 apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(i)); /* Target chip */
555 cfg=apic_read(APIC_ICR);
556 cfg&=~0xFDFFF ; /* Clear bits */
557 cfg|=APIC_DEST_DM_INIT; /* INIT the CPU */
558 apic_write(APIC_ICR, cfg); /* Kick the second */
559 printk("\nBuggy motherboard ?, trying an INIT IPI: ");
560 udelay(10); /* Masses of time */
561 }
562 if(timeout==0||timeout==20001)
563 {
564 cfg=apic_read(APIC_ICR);
565 cfg&=~0xFDFFF ; /* Clear bits */
566 cfg|=APIC_DEST_FIELD|APIC_DEST_DM_STARTUP|(((unsigned long)stack)>>12); /* Boot on the stack */
567 apic_write(APIC_ICR, cfg); /* Kick the second */
568 udelay(10); /* Masses of time */
569 cfg=apic_read(APIC_ESR);
570 if(cfg&4) /* Send accept error */
571 printk("Processor refused startup request.\n");
572 }
573 if(cpu_callin_map[0]&(1<<i))
574 break; /* It has booted */
575 udelay(100); /* Wait 5s total for a response */
576 }
577 if(cpu_callin_map[0]&(1<<i))
578 cpucount++;
579 else
580 {
581 /*
582 * At this point we should set up a BIOS warm start and try
583 * a RESTART IPI. The 486+82489 MP pair don't support STARTUP IPI's
584 */
585 if(*((unsigned char *)8192)==0xA5)
586 printk("Stuck ??\n");
587 else
588 printk("Not responding.\n");
589 cpu_present_map&=~(1<<i);
590 }
591 }
592 }
593 /*
594 * Allow the user to impress friends.
595 */
596 if(cpucount==0)
597 {
598 printk("Error: only one processor found.\n");
599 cpu_present_map=(1<<smp_processor_id());
600 }
601 else
602 {
603 unsigned long bogosum=0;
604 for(i=0;i<32;i++)
605 {
606 if(cpu_present_map&(1<<i))
607 bogosum+=cpu_data[i].udelay_val;
608 }
609 printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
610 cpucount+1,
611 (bogosum+2500)/500000,
612 ((bogosum+2500)/5000)%100);
613 smp_activated=1;
614 smp_num_cpus=cpucount+1;
615 }
616 }
617
618
619 /*
620 * A non wait message cannot pass data or cpu source info. This current setup
621 * is only safe because the kernel lock owner is the only person who can send a message.
622 *
623 * Wrapping this whole block in a spinlock is not the safe answer either. A processor may
624 * get stuck with irq's off waiting to send a message and thus not replying to the person
625 * spinning for a reply....
626 *
627 * In the end invalidate ought to be the NMI and a very very short function (to avoid the old
628 * IDE disk problems), and other messages sent with IRQ's enabled in a civilised fashion. That
629 * will also boost performance.
630 */
631
632 void smp_message_pass(int target, int msg, unsigned long data, int wait)
/* */
633 {
634 unsigned long cfg;
635 unsigned long target_map;
636 int p=smp_processor_id();
637 int irq=0x2d; /* IRQ 13 */
638 int ct=0;
639 static volatile int message_cpu = NO_PROC_ID;
640
641 /*
642 * During boot up send no messages
643 */
644
645 if(!smp_activated || !smp_commenced)
646 return;
647
648
649 /*
650 * Skip the reschedule if we are waiting to clear a
651 * message at this time. The reschedule cannot wait
652 * but is not critical.
653 */
654
655 if(msg==MSG_RESCHEDULE) /* Reschedules we do via trap 0x30 */
656 {
657 irq=0x30;
658 if(smp_cpu_in_msg[p])
659 return;
660 }
661
662 /*
663 * Sanity check we don't re-enter this across CPU's. Only the kernel
664 * lock holder may send messages. For a STOP_CPU we are bringing the
665 * entire box to the fastest halt we can..
666 */
667
668 if(message_cpu!=NO_PROC_ID && msg!=MSG_STOP_CPU)
669 {
670 panic("CPU #%d: Message pass %d but pass in progress by %d of %d\n",
671 smp_processor_id(),msg,message_cpu, smp_msg_id);
672 }
673 message_cpu=smp_processor_id();
674
675
676 /*
677 * We are busy
678 */
679
680 smp_cpu_in_msg[p]++;
681
682 /*
683 * Reschedule is currently special
684 */
685
686 if(msg!=MSG_RESCHEDULE)
687 {
688 smp_src_cpu=p;
689 smp_msg_id=msg;
690 smp_msg_data=data;
691 }
692
693 /* printk("SMP message pass #%d to %d of %d\n",
694 p, msg, target);*/
695
696 /*
697 * Wait for the APIC to become ready - this should never occur. Its
698 * a debugging check really.
699 */
700
701 while(ct<1000)
702 {
703 cfg=apic_read(APIC_ICR);
704 if(!(cfg&(1<<12)))
705 break;
706 ct++;
707 udelay(10);
708 }
709
710 /*
711 * Just pray... there is nothing more we can do
712 */
713
714 if(ct==1000)
715 printk("CPU #%d: previous IPI still not cleared after 10mS", smp_processor_id());
716
717 /*
718 * Program the APIC to deliver the IPI
719 */
720
721 cfg=apic_read(APIC_ICR2);
722 cfg&=0x00FFFFFF;
723 apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(target)); /* Target chip */
724 cfg=apic_read(APIC_ICR);
725 cfg&=~0xFDFFF; /* Clear bits */
726 cfg|=APIC_DEST_FIELD|APIC_DEST_DM_FIXED|irq; /* Send an IRQ 13 */
727
728 /*
729 * Set the target requirement
730 */
731
732 if(target==MSG_ALL_BUT_SELF)
733 {
734 cfg|=APIC_DEST_ALLBUT;
735 target_map=cpu_present_map;
736 cpu_callin_map[0]=(1<<smp_src_cpu);
737 }
738 else if(target==MSG_ALL)
739 {
740 cfg|=APIC_DEST_ALLINC;
741 target_map=cpu_present_map;
742 cpu_callin_map[0]=0;
743 }
744 else
745 {
746 target_map=(1<<target);
747 cpu_callin_map[0]=0;
748 }
749
750 /*
751 * Send the IPI. The write to APIC_ICR fires this off.
752 */
753
754 apic_write(APIC_ICR, cfg);
755
756 /*
757 * Spin waiting for completion
758 */
759
760 switch(wait)
761 {
762 case 1:
763 while(cpu_callin_map[0]!=target_map); /* Spin on the pass */
764 break;
765 case 2:
766 while(smp_invalidate_needed); /* Wait for invalidate map to clear */
767 break;
768 }
769
770 /*
771 * Record our completion
772 */
773
774 smp_cpu_in_msg[p]--;
775 message_cpu=NO_PROC_ID;
776 }
777
778 /*
779 * This is fraught with deadlocks. Linus does an invalidate at a whim
780 * even with IRQ's off. We have to avoid a pair of crossing invalidates
781 * or we are doomed. See the notes about smp_message_pass.
782 */
783
784 void smp_invalidate(void)
/* */
785 {
786 unsigned long flags;
787 if(smp_activated && smp_processor_id()!=active_kernel_processor)
788 panic("CPU #%d:Attempted invalidate IPI when not AKP(=%d)\n",smp_processor_id(),active_kernel_processor);
789 /* printk("SMI-");*/
790
791 /*
792 * The assignment is safe because its volatile so the compiler cannot reorder it,
793 * because the i586 has strict memory ordering and because only the kernel lock holder
794 * may issue an invalidate. If you break any one of those three change this to an atomic
795 * bus locked or.
796 */
797
798 smp_invalidate_needed=cpu_present_map&~(1<<smp_processor_id());
799
800 /*
801 * Processors spinning on the lock will see this IRQ late. The smp_invalidate_needed map will
802 * ensure they dont do a spurious invalidate or miss one.
803 */
804
805 save_flags(flags);
806 cli();
807 smp_message_pass(MSG_ALL_BUT_SELF, MSG_INVALIDATE_TLB, 0L, 2);
808
809 /*
810 * Flush the local TLB
811 */
812
813 local_invalidate();
814
815 restore_flags(flags);
816
817 /*
818 * Completed.
819 */
820
821 /* printk("SMID\n");*/
822 }
823
824 /*
825 * Reschedule call back
826 */
827
828 void smp_reschedule_irq(int cpl, struct pt_regs *regs)
/* */
829 {
830 #ifdef DEBUGGING_SMP_RESCHED
831 static int ct=0;
832 if(ct==0)
833 {
834 printk("Beginning scheduling on CPU#%d\n",smp_processor_id());
835 ct=1;
836 }
837 #endif
838 if(smp_processor_id()!=active_kernel_processor)
839 panic("SMP Reschedule on CPU #%d, but #%d is active.\n",
840 smp_processor_id(), active_kernel_processor);
841 /*
842 * Update resource usage on the slave timer tick.
843 */
844
845 if (user_mode(regs))
846 {
847 current->utime++;
848 if (current->pid)
849 {
850 if (current->priority < 15)
851 kstat.cpu_nice++;
852 else
853 kstat.cpu_user++;
854 }
855 /* Update ITIMER_VIRT for current task if not in a system call */
856 if (current->it_virt_value && !(--current->it_virt_value)) {
857 current->it_virt_value = current->it_virt_incr;
858 send_sig(SIGVTALRM,current,1);
859 }
860 } else {
861 current->stime++;
862 if(current->pid)
863 kstat.cpu_system++;
864 #ifdef CONFIG_PROFILE
865 if (prof_buffer && current->pid) {
866 extern int _stext;
867 unsigned long eip = regs->eip - (unsigned long) &_stext;
868 eip >>= CONFIG_PROFILE_SHIFT;
869 if (eip < prof_len)
870 prof_buffer[eip]++;
871 }
872 #endif
873 }
874 /*
875 * check the cpu time limit on the process.
876 */
877 if ((current->rlim[RLIMIT_CPU].rlim_max != RLIM_INFINITY) &&
878 (((current->stime + current->utime) / HZ) >= current->rlim[RLIMIT_CPU].rlim_max))
879 send_sig(SIGKILL, current, 1);
880 if ((current->rlim[RLIMIT_CPU].rlim_cur != RLIM_INFINITY) &&
881 (((current->stime + current->utime) % HZ) == 0)) {
882 unsigned long psecs = (current->stime + current->utime) / HZ;
883 /* send when equal */
884 if (psecs == current->rlim[RLIMIT_CPU].rlim_cur)
885 send_sig(SIGXCPU, current, 1);
886 /* and every five seconds thereafter. */
887 else if ((psecs > current->rlim[RLIMIT_CPU].rlim_cur) &&
888 ((psecs - current->rlim[RLIMIT_CPU].rlim_cur) % 5) == 0)
889 send_sig(SIGXCPU, current, 1);
890 }
891
892 /* Update ITIMER_PROF for the current task */
893 if (current->it_prof_value && !(--current->it_prof_value)) {
894 current->it_prof_value = current->it_prof_incr;
895 send_sig(SIGPROF,current,1);
896 }
897
898
899 /*
900 * Don't reschedule if we are in an interrupt...
901 * [This is test code and not needed in the end]
902 */
903
904 /* if(intr_count==1)
905 {*/
906
907 /*
908 * See if the slave processors need a schedule.
909 */
910
911 if ( 0 > --current->counter || current->pid == 0)
912 {
913 current->counter = 0;
914 need_resched=1;
915 }
916 /* }*/
917
918 /*
919 * Clear the IPI
920 */
921 apic_read(APIC_SPIV); /* Dummy read */
922 apic_write(APIC_EOI, 0); /* Docs say use 0 for future compatibility */
923 }
924
925 /*
926 * Message call back.
927 */
928
929 void smp_message_irq(int cpl, struct pt_regs *regs)
/* ![[last]](../icons/n_last.png)
*/
930 {
931 int i=smp_processor_id();
932 /* static int n=0;
933 if(n++<NR_CPUS)
934 printk("IPI %d->%d(%d,%ld)\n",smp_src_cpu,i,smp_msg_id,smp_msg_data);*/
935 switch(smp_msg_id)
936 {
937 case 0: /* IRQ 13 testing - boring */
938 return;
939
940 /*
941 * A TLB flush is needed.
942 */
943
944 case MSG_INVALIDATE_TLB:
945 if(clear_bit(i,&smp_invalidate_needed))
946 local_invalidate();
947 set_bit(i, &cpu_callin_map[0]);
948 cpu_callin_map[0]|=1<<smp_processor_id();
949 break;
950
951 /*
952 * Halt other CPU's for a panic or reboot
953 */
954 case MSG_STOP_CPU:
955 while(1)
956 {
957 if(cpu_data[smp_processor_id()].hlt_works_ok)
958 __asm__("hlt");
959 }
960 default:
961 printk("CPU #%d sent invalid cross CPU message to CPU #%d: %X(%lX).\n",
962 smp_src_cpu,smp_processor_id(),smp_msg_id,smp_msg_data);
963 break;
964 }
965 /*
966 * Clear the IPI, so we can receive future IPI's
967 */
968
969 apic_read(APIC_SPIV); /* Dummy read */
970 apic_write(APIC_EOI, 0); /* Docs say use 0 for future compatibility */
971 }
![[bottom]](../icons/n_bottom.png){kind=icon}
*/