1 /* 2 * bios32.c - PCI BIOS functions for Alpha systems not using BIOS 3 * emulation code. 4 * 5 * Written by Dave Rusling (david.rusling@reo.mts.dec.com) 6 * 7 * Adapted to 64-bit kernel and then rewritten by David Mosberger 8 * (davidm@cs.arizona.edu) 9 * 10 * For more information, please consult 11 * 12 * PCI BIOS Specification Revision 13 * PCI Local Bus Specification 14 * PCI System Design Guide 15 * 16 * PCI Special Interest Group 17 * M/S HF3-15A 18 * 5200 N.E. Elam Young Parkway 19 * Hillsboro, Oregon 97124-6497 20 * +1 (503) 696-2000 21 * +1 (800) 433-5177 22 * 23 * Manuals are $25 each or $50 for all three, plus $7 shipping 24 * within the United States, $35 abroad. 25 */ 26 #include <linux/config.h>
27
28 #ifndefCONFIG_PCI 29
30 intpcibios_present(void)
/* */ 31 { 32 return 0;
33 } 34
35 #else/* CONFIG_PCI */ 36
37 #include <linux/kernel.h>
38 #include <linux/bios32.h>
39 #include <linux/pci.h>
40 #include <linux/malloc.h>
41 #include <linux/mm.h>
42
43 #include <asm/hwrpb.h>
44 #include <asm/io.h>
45
46
47 #defineKB 1024
48 #defineMB (1024*KB)
49 #define GB (1024*MB)
50
51 #defineMAJOR_REV 0
52 #defineMINOR_REV 3
53
54 /* 55 * Align VAL to ALIGN, which must be a power of two. 56 */ 57 #defineALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
58
59
60 /* 61 * Temporary internal macro. If this 0, then do not write to any of 62 * the PCI registers, merely read them (i.e., use configuration as 63 * determined by SRM). The SRM seem do be doing a less than perfect 64 * job in configuring PCI devices, so for now we do it ourselves. 65 * Reconfiguring PCI devices breaks console (RPB) callbacks, but 66 * those don't work properly with 64 bit addresses anyways. 67 * 68 * The accepted convention seems to be that the console (POST 69 * software) should fully configure boot devices and configure the 70 * interrupt routing of *all* devices. In particular, the base 71 * addresses of non-boot devices need not be initialized. For 72 * example, on the AXPpci33 board, the base address a #9 GXE PCI 73 * graphics card reads as zero (this may, however, be due to a bug in 74 * the graphics card---there have been some rumor that the #9 BIOS 75 * incorrectly resets that address to 0...). 76 */ 77 #definePCI_MODIFY 1
78
79
80 externstructhwrpb_struct *hwrpb;
81
82
83 #ifPCI_MODIFY 84
85 staticunsignedintio_base = 64*KB; /* <64KB are (E)ISA ports */ 86 staticunsignedintmem_base = 16*MB; /* <16MB is ISA memory */ 87
88 /* 89 * Disable PCI device DEV so that it does not respond to I/O or memory 90 * accesses. 91 */ 92 staticvoiddisable_dev(structpci_dev *dev)
/* */ 93 { 94 structpci_bus *bus;
95 unsignedshortcmd;
96
97 bus = dev->bus;
98 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
99
100 /* hack, turn it off first... */ 101 cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
102 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND, cmd);
103 } 104
105
106 /* 107 * Layout memory and I/O for a device: 108 */ 109 #defineMAX(val1, val2) ( ((val1) > (val2)) ? val1 : val2)
110
111 staticvoidlayout_dev(structpci_dev *dev)
/* */ 112 { 113 structpci_bus *bus;
114 unsignedshortcmd;
115 unsignedintbase, mask, size, reg;
116 unsignedintalignto;
117
118 bus = dev->bus;
119 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
120
121 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) { 122 /* 123 * Figure out how much space and of what type this 124 * device wants. 125 */ 126 pcibios_write_config_dword(bus->number, dev->devfn, reg,
127 0xffffffff);
128 pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
129 if (!base) { 130 /* this base-address register is unused */ 131 continue;
132 } 133
134 /* 135 * We've read the base address register back after 136 * writing all ones and so now we must decode it. 137 */ 138 if (base & PCI_BASE_ADDRESS_SPACE_IO) { 139 /* 140 * I/O space base address register. 141 */ 142 cmd |= PCI_COMMAND_IO;
143
144 base &= PCI_BASE_ADDRESS_IO_MASK;
145 mask = (~base << 1) | 0x1;
146 size = (mask & base) & 0xffffffff;
147 /* align to multiple of size of minimum base */ 148 alignto = MAX(0x400, size) ;
149 base = ALIGN(io_base, alignto );
150 io_base = base + size;
151 pcibios_write_config_dword(bus->number, dev->devfn,
152 reg, base | 0x1);
153 }else{ 154 unsignedinttype;
155 /* 156 * Memory space base address register. 157 */ 158 cmd |= PCI_COMMAND_MEMORY;
159 type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
160 base &= PCI_BASE_ADDRESS_MEM_MASK;
161 mask = (~base << 1) | 0x1;
162 size = (mask & base) & 0xffffffff;
163 switch (type) { 164 casePCI_BASE_ADDRESS_MEM_TYPE_32:
165 break;
166
167 casePCI_BASE_ADDRESS_MEM_TYPE_64:
168 printk("bios32 WARNING: "
169 "ignoring 64-bit device in "
170 "slot %d, function %d: \n",
171 PCI_SLOT(dev->devfn),
172 PCI_FUNC(dev->devfn));
173 reg += 4; /* skip extra 4 bytes */ 174 continue;
175
176 casePCI_BASE_ADDRESS_MEM_TYPE_1M:
177 /* 178 * Allocating memory below 1MB is *very* 179 * tricky, as there may be all kinds of 180 * ISA devices lurking that we don't know 181 * about. For now, we just cross fingers 182 * and hope nobody tries to do this on an 183 * Alpha (or that the console has set it 184 * up properly). 185 */ 186 printk("bios32 WARNING: slot %d, function %d "
187 "requests memory below 1MB---don't "
188 "know how to do that.\n",
189 PCI_SLOT(dev->devfn),
190 PCI_FUNC(dev->devfn));
191 continue;
192 } 193 /* 194 * The following holds at least for the Low Cost 195 * Alpha implementation of the PCI interface: 196 * 197 * In sparse memory address space, the first 198 * octant (16MB) of every 128MB segment is 199 * aliased to the the very first 16MB of the 200 * address space (i.e., it aliases the ISA 201 * memory address space). Thus, we try to 202 * avoid allocating PCI devices in that range. 203 * Can be allocated in 2nd-7th octant only. 204 * Devices that need more than 112MB of 205 * address space must be accessed through 206 * dense memory space only! 207 */ 208 /* align to multiple of size of minimum base */ 209 alignto = MAX(0x1000, size) ;
210 base = ALIGN(mem_base, alignto);
211 if (size > 7 * 16*MB) { 212 printk("bios32 WARNING: slot %d, function %d "
213 "requests %dB of contiguous address "
214 " space---don't use sparse memory "
215 " accesses on this device!!\n",
216 PCI_SLOT(dev->devfn),
217 PCI_FUNC(dev->devfn), size);
218 }else{ 219 if (((base / (16*MB)) & 0x7) == 0) { 220 base &= ~(128*MB - 1);
221 base += 16*MB;
222 base = ALIGN(base, alignto);
223 } 224 if (base / (128*MB) != (base + size) / (128*MB)) { 225 base &= ~(128*MB - 1);
226 base += (128 + 16)*MB;
227 base = ALIGN(base, alignto);
228 } 229 } 230 mem_base = base + size;
231 pcibios_write_config_dword(bus->number, dev->devfn,
232 reg, base);
233 } 234 } 235 /* enable device: */ 236 if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
237 dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
238 dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
239 dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
240 { 241 /* 242 * All of these (may) have I/O scattered all around 243 * and may not use i/o-base address registers at all. 244 * So we just have to always enable I/O to these 245 * devices. 246 */ 247 cmd |= PCI_COMMAND_IO;
248 } 249
250 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
251 cmd | PCI_COMMAND_MASTER);
252 } 253
254
255 staticvoidlayout_bus(structpci_bus *bus)
/* */ 256 { 257 unsignedintl, tio, bio, tmem, bmem;
258 structpci_bus *child;
259 structpci_dev *dev;
260
261 if (!bus->devices && !bus->children)
262 return;
263
264 /* 265 * Align the current bases on appropriate boundaries (4K for 266 * IO and 1MB for memory). 267 */ 268 bio = io_base = ALIGN(io_base, 4*KB);
269 bmem = mem_base = ALIGN(mem_base, 1*MB);
270
271 /* 272 * There are times when the PCI devices have already been 273 * setup (e.g., by MILO or SRM). In these cases there is a 274 * window during which two devices may have an overlapping 275 * address range. To avoid this causing trouble, we first 276 * turn off the I/O and memory address decoders for all PCI 277 * devices. They'll be re-enabled only once all address 278 * decoders are programmed consistently. 279 */ 280 for (dev = bus->devices; dev; dev = dev->sibling) { 281 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) { 282 disable_dev(dev) ;
283 } 284 } 285
286 /* 287 * Allocate space to each device: 288 */ 289 for (dev = bus->devices; dev; dev = dev->sibling) { 290 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) { 291 layout_dev(dev);
292 } 293 } 294 /* 295 * Recursively allocate space for all of the sub-buses: 296 */ 297 for (child = bus->children; child; child = child->next) { 298 layout_bus(child);
299 } 300 /* 301 * Align the current bases on 4K and 1MB boundaries: 302 */ 303 tio = io_base = ALIGN(io_base, 4*KB);
304 tmem = mem_base = ALIGN(mem_base, 1*MB);
305
306 if (bus->self) { 307 structpci_dev *bridge = bus->self;
308 /* 309 * Set up the top and bottom of the I/O memory segment 310 * for this bus. 311 */ 312 pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
313 0x1c, &l);
314 l = l | (bio >> 8) | ((tio - 1) & 0xf000);
315 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
316 0x1c, l);
317
318 l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
319 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
320 0x20, l);
321 /* 322 * Turn off downstream PF memory address range: 323 */ 324 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
325 0x24, 0x0000ffff);
326 /* 327 * Tell bridge that there is an ISA bus in the system: 328 */ 329 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
330 0x3c, 0x00040000);
331 /* 332 * Clear status bits, enable I/O (for downstream I/O), 333 * turn on master enable (for upstream I/O), turn on 334 * memory enable (for downstream memory), turn on 335 * master enable (for upstream memory and I/O). 336 */ 337 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
338 0x4, 0xffff0007);
339 } 340 } 341
342 #endif/* !PCI_MODIFY */ 343
344
345 /* 346 * Given the vendor and device ids, find the n'th instance of that device 347 * in the system. 348 */ 349 intpcibios_find_device (unsignedshortvendor, unsignedshortdevice_id,
/* */ 350 unsignedshortindex, unsignedchar *bus,
351 unsignedchar *devfn)
352 { 353 unsignedintcurr = 0;
354 structpci_dev *dev;
355
356 for (dev = pci_devices; dev; dev = dev->next) { 357 if (dev->vendor == vendor && dev->device == device_id) { 358 if (curr == index) { 359 *devfn = dev->devfn;
360 *bus = dev->bus->number;
361 returnPCIBIOS_SUCCESSFUL;
362 } 363 ++curr;
364 } 365 } 366 returnPCIBIOS_DEVICE_NOT_FOUND;
367 } 368
369
370 /* 371 * Given the class, find the n'th instance of that device 372 * in the system. 373 */ 374 intpcibios_find_class (unsignedintclass_code, unsignedshortindex,
/* */ 375 unsignedchar *bus, unsignedchar *devfn)
376 { 377 unsignedintcurr = 0;
378 structpci_dev *dev;
379
380 for (dev = pci_devices; dev; dev = dev->next) { 381 if (dev->class == class_code) { 382 if (curr == index) { 383 *devfn = dev->devfn;
384 *bus = dev->bus->number;
385 returnPCIBIOS_SUCCESSFUL;
386 } 387 ++curr;
388 } 389 } 390 returnPCIBIOS_DEVICE_NOT_FOUND;
391 } 392
393
394 intpcibios_present(void)
/* */ 395 { 396 return 1;
397 } 398
399
400 unsignedlongpcibios_init(unsignedlongmem_start,
/* */ 401 unsignedlongmem_end)
402 { 403 printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
404
405 #if !PCI_MODIFY 406 printk("...NOT modifying existing (SRM) PCI configuration\n");
407 #endif 408 returnmem_start;
409 } 410
411 /* 412 * The SRM console *disables* the IDE interface, this code ensures its 413 * enabled. 414 * 415 * This code bangs on a control register of the 87312 Super I/O chip 416 * that implements parallel port/serial ports/IDE/FDI. Depending on 417 * the motherboard, the Super I/O chip can be configured through a 418 * pair of registers that are located either at I/O ports 0x26e/0x26f 419 * or 0x398/0x399. Unfortunately, autodetecting which base address is 420 * in use works only once (right after a reset). The Super I/O chip 421 * has the additional quirk that configuration register data must be 422 * written twice (I believe this is a saftey feature to prevent 423 * accidental modification---fun, isn't it?). 424 */ 425 staticinlinevoidenable_ide(longide_base)
/* */ 426 { 427 intdata;
428
429 outb(0, ide_base); /* set the index register for reg #0 */ 430 data = inb(ide_base+1); /* read the current contents */ 431 outb(0, ide_base); /* set the index register for reg #0 */ 432 outb(data | 0x40, ide_base+1); /* turn on IDE */ 433 outb(data | 0x40, ide_base+1); /* turn on IDE, really! */ 434 } 435
436 /* 437 * Most evaluation boards share most of the fixup code, which is isolated here. 438 * This function is declared "inline" as only one platform will ever be selected 439 * in any given kernel. If that platform doesn't need this code, we don't want 440 * it around as dead code. 441 */ 442 staticinlinevoidcommon_fixup(longmin_idsel, longmax_idsel, longirqs_per_slot,
/* */ 443 charirq_tab[max_idsel - min_idsel + 1][irqs_per_slot],
444 longide_base)
445 { 446 structpci_dev *dev;
447 unsignedcharpin;
448
449 /* 450 * Go through all devices, fixing up irqs as we see fit: 451 */ 452 for (dev = pci_devices; dev; dev = dev->next) { 453 dev->irq = 0;
454 /* 455 * Ignore things not on the primary bus - I'll figure 456 * this out one day - Dave Rusling 457 */ 458 if (dev->bus->number != 0)
459 continue;
460
461 /* read the pin */ 462 pcibios_read_config_byte(dev->bus->number, dev->devfn,
463 PCI_INTERRUPT_PIN, &pin);
464 if (irq_tab[PCI_SLOT(dev->devfn) - min_idsel][pin] != -1)
465 dev->irq = irq_tab[PCI_SLOT(dev->devfn) - min_idsel][pin];
466 #ifPCI_MODIFY 467 /* tell the device: */ 468 pcibios_write_config_byte(dev->bus->number, dev->devfn,
469 PCI_INTERRUPT_LINE, dev->irq);
470 #endif 471 /* 472 * if its a VGA, enable its BIOS ROM at C0000 473 */ 474 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { 475 pcibios_write_config_dword(dev->bus->number, dev->devfn,
476 PCI_ROM_ADDRESS,
477 0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
478 } 479 } 480 if (ide_base) { 481 enable_ide(ide_base);
482 } 483 } 484
485 /* 486 * The EB66+ is very similar to the EB66 except that it does not have 487 * the on-board NCR and Tulip chips. In the code below, I have used 488 * slot number to refer to the id select line and *not* the slot 489 * number used in the EB66+ documentation. However, in the table, 490 * I've given the slot number, the id select line and the Jxx number 491 * that's printed on the board. The interrupt pins from the PCI slots 492 * are wired into 3 interrupt summary registers at 0x804, 0x805 and 493 * 0x806 ISA. 494 * 495 * In the table, -1 means don't assign an IRQ number. This is usually 496 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip. 497 */ 498 staticinlinevoideb66p_fixup(void)
/* */ 499 { 500 charirq_tab[5][5] = { 501 {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */ 502 {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */ 503 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ 504 {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */ 505 {16+3, 16+3, 16+8, 16+12, 16+6}/* IdSel 10, slot 3, J28 */ 506 };
507 common_fixup(6, 10, 5, irq_tab, 0x398);
508 } 509
510
511 /* 512 * The AlphaPC64 is very similar to the EB66+ except that its slots 513 * are numbered differently. In the code below, I have used slot 514 * number to refer to the id select line and *not* the slot number 515 * used in the AlphaPC64 documentation. However, in the table, I've 516 * given the slot number, the id select line and the Jxx number that's 517 * printed on the board. The interrupt pins from the PCI slots are 518 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806 519 * ISA. 520 * 521 * In the table, -1 means don't assign an IRQ number. This is usually 522 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip. 523 */ 524 staticinlinevoidcabriolet_fixup(void)
/* */ 525 { 526 charirq_tab[5][5] = { 527 { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */ 528 { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */ 529 { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */ 530 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ 531 { 16+3, 16+3, 16+8, 16+12, 16+16}/* IdSel 9, slot 3, J22 */ 532 };
533
534 common_fixup(5, 9, 5, irq_tab, 0x398);
535 } 536
537
538 /* 539 * Fixup configuration for EB66/EB64+ boards. 540 * 541 * Both these boards use the same interrupt summary scheme. There are 542 * two 8 bit external summary registers as follows: 543 * 544 * Summary @ 0x26: 545 * Bit Meaning 546 * 0 Interrupt Line A from slot 0 547 * 1 Interrupt Line A from slot 1 548 * 2 Interrupt Line B from slot 0 549 * 3 Interrupt Line B from slot 1 550 * 4 Interrupt Line C from slot 0 551 * 5 Interrupt line from the two ISA PICs 552 * 6 Tulip (slot 553 * 7 NCR SCSI 554 * 555 * Summary @ 0x27 556 * Bit Meaning 557 * 0 Interrupt Line C from slot 1 558 * 1 Interrupt Line D from slot 0 559 * 2 Interrupt Line D from slot 1 560 * 3 RAZ 561 * 4 RAZ 562 * 5 RAZ 563 * 6 RAZ 564 * 7 RAZ 565 * 566 * The device to slot mapping looks like: 567 * 568 * Slot Device 569 * 5 NCR SCSI controller 570 * 6 PCI on board slot 0 571 * 7 PCI on board slot 1 572 * 8 Intel SIO PCI-ISA bridge chip 573 * 9 Tulip - DECchip 21040 ethernet controller 574 * 575 * 576 * This two layered interrupt approach means that we allocate IRQ 16 and 577 * above for PCI interrupts. The IRQ relates to which bit the interrupt 578 * comes in on. This makes interrupt processing much easier. 579 */ 580 staticinlinevoideb66_and_eb64p_fixup(void)
/* */ 581 { 582 charirq_tab[5][5] = { 583 {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */ 584 {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */ 585 {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */ 586 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ 587 {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */ 588 };
589 common_fixup(5, 9, 5, irq_tab, 0);
590 } 591
592
593 /* 594 * Fixup configuration for all boards that route the PCI interrupts 595 * through the SIO PCI/ISA bridge. This includes Noname (AXPpci33), 596 * Avanti (AlphaStation) and Kenetics's Platform 2000. 597 */ 598 staticinlinevoidsio_fixup(void)
/* */ 599 { 600 structpci_dev *dev;
601 /* 602 * The Noname board has 5 PCI slots with each of the 4 603 * interrupt pins routed to different pins on the PCI/ISA 604 * bridge (PIRQ0-PIRQ3). The table below is based on 605 * information available at: 606 * 607 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt 608 * 609 * I have no information on the Avanti interrupt routing, but 610 * the routing seems to be identical to the Noname except 611 * that the Avanti has an additional slot whose routing I'm 612 * unsure of. 613 * 614 * pirq_tab[0] is a fake entry to deal with old PCI boards 615 * that have the interrupt pin number hardwired to 0 (meaning 616 * that they use the default INTA line, if they are interrupt 617 * driven at all). 618 */ 619 staticconstcharpirq_tab[][5] = { 620 #ifdefCONFIG_ALPHA_P2K 621 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */ 622 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */ 623 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */ 624 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */ 625 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */ 626 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */ 627 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */ 628 #else 629 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */ 630 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */ 631 { 2, 2, -1, -1, -1}, /* idsel 8 (Noname hack: slot closest to ISA) */ 632 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */ 633 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */ 634 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */ 635 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */ 636 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */ 637 #endif 638 };
639 /* 640 * route_tab selects irq routing in PCI/ISA bridge so that: 641 * PIRQ0 -> irq 15 642 * PIRQ1 -> irq 9 643 * PIRQ2 -> irq 10 644 * PIRQ3 -> irq 11 645 * 646 * This probably ought to be configurable via MILO. For 647 * example, sound boards seem to like using IRQ 9. 648 */ 649 constunsignedintroute_tab = 0x0b0a090f;
650 unsignedintlevel_bits;
651 unsignedcharpin;
652 intpirq;
653
654 pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
655
656 /* 657 * Go through all devices, fixing up irqs as we see fit: 658 */ 659 level_bits = 0;
660 for (dev = pci_devices; dev; dev = dev->next) { 661 dev->irq = 0;
662 if (dev->bus->number != 0) { 663 printk("bios32.sio_fixup: don't know how to fixup devices on bus %d\n",
664 dev->bus->number);
665 continue;
666 } 667 if (PCI_SLOT(dev->devfn) < 6 ||
668 PCI_SLOT(dev->devfn) >= 6 + sizeof(pirq_tab)/sizeof(pirq_tab[0]))
669 { 670 printk("bios32.sio_fixup: "
671 "weird, found device %04x:%04x in non-existent slot %d!!\n",
672 dev->vendor, dev->device, PCI_SLOT(dev->devfn));
673 continue;
674 } 675 pcibios_read_config_byte(dev->bus->number, dev->devfn,
676 PCI_INTERRUPT_PIN, &pin);
677 pirq = pirq_tab[PCI_SLOT(dev->devfn) - 6][pin];
678 if (pirq < 0) { 679 continue;
680 } 681 /* 682 * if its a VGA, enable its BIOS ROM at C0000 683 */ 684 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { 685 pcibios_write_config_dword(dev->bus->number, dev->devfn,
686 PCI_ROM_ADDRESS,
687 0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
688 } 689 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) { 690 continue; /* for now, displays get no IRQ */ 691 } 692 dev->irq = (route_tab >> (8 * pirq)) & 0xff;
693
694 /* must set the PCI IRQs to level triggered */ 695 level_bits |= (1 << dev->irq);
696
697 #ifPCI_MODIFY 698 /* tell the device: */ 699 pcibios_write_config_byte(dev->bus->number, dev->devfn,
700 PCI_INTERRUPT_LINE, dev->irq);
701 #endif 702 } 703 /* 704 * Now, make all PCI interrupts level sensitive. Notice: 705 * these registers must be accessed byte-wise. outw() doesn't 706 * work. 707 */ 708 outb((level_bits >> 0) & 0xff, 0x4d0);
709 outb((level_bits >> 8) & 0xff, 0x4d1);
710 enable_ide(0x26e);
711 } 712
713
714 #ifdefCONFIG_TGA_CONSOLE 715 externvoidtga_console_init(void);
716 #endif/* CONFIG_TGA_CONSOLE */ 717
718 unsignedlongpcibios_fixup(unsignedlongmem_start, unsignedlongmem_end)
/* */ 719 { 720 #ifPCI_MODIFY 721 /* 722 * Scan the tree, allocating PCI memory and I/O space. 723 */ 724 layout_bus(&pci_root);
725 #endif 726
727 /* 728 * Now is the time to do all those dirty little deeds... 729 */ 730 #ifdefined(CONFIG_ALPHA_NONAME) || defined(CONFIG_ALPHA_AVANTI) || defined(CONFIG_ALPHA_P2K)
731 sio_fixup();
732 #elifdefined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB164)
733 cabriolet_fixup();
734 #elifdefined(CONFIG_ALPHA_EB66P)
735 eb66p_fixup();
736 #elifdefined(CONFIG_ALPHA_EB66)
737 eb66_and_eb64p_fixup();
738 #elifdefined(CONFIG_ALPHA_EB64P)
739 eb66_and_eb64p_fixup();
740 #else 741 # error You must tell me what kind of platform you want.
742 #endif 743
744 #ifdefCONFIG_TGA_CONSOLE 745 tga_console_init();
746 #endif/* CONFIG_TGA_CONSOLE */ 747
748 returnmem_start;
749 } 750
751
752 constchar *pcibios_strerror (interror)
/* */ 753 { 754 staticcharbuf[80];
755
756 switch (error) { 757 casePCIBIOS_SUCCESSFUL:
758 return "SUCCESSFUL";
759
760 casePCIBIOS_FUNC_NOT_SUPPORTED:
761 return "FUNC_NOT_SUPPORTED";
762
763 casePCIBIOS_BAD_VENDOR_ID:
764 return "SUCCESSFUL";
765
766 casePCIBIOS_DEVICE_NOT_FOUND:
767 return "DEVICE_NOT_FOUND";
768
769 casePCIBIOS_BAD_REGISTER_NUMBER:
770 return "BAD_REGISTER_NUMBER";
771
772 default:
773 sprintf (buf, "UNKNOWN RETURN 0x%x", error);
774 returnbuf;
775 } 776 } 777
778 #endif/* CONFIG_PCI */