drivers/net/pi2.c

/* */
This source file includes following definitions.
pi0_preprobe
random
wrtscc
rdscc
switchbuffers
hardware_send_packet
setup_rx_dma
setup_tx_dma
tdelay
free_p
a_txint
a_exint
a_rxint
b_rxint
b_txint
b_exint
hw_probe
rts
pi_header
pi_rebuild_header
scc_init
chipset_init
pi_init
valid_dma_page
pi_set_mac_address
get_dma_buffer
pi_probe
pi_open
pi_send_packet
pi_interrupt
pi_close
pi_ioctl
pi_get_stats
   1 /*
   2    pi2.c: Driver for the Ottawa Amateur Radio Club PI and PI2 interface.
   3    Copyright (c) 1994 David Perry
   4 
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License version 2, as
   7    published by the Free Software Foundation.
   8 
   9    This program is distributed in the hope that it will be useful, but
  10    WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12    General Public License for more details.
  13 
  14    You should have received a copy of the GNU General Public License
  15    along with this program; if not, write to the Free Software Foundation,
  16    Inc., 675 Mass Ave, Cambridge MA 02139, USA.
  17 
  18    The file skeleton.c by Donald Becker was used as a starting point
  19    for this driver.
  20 
  21    Revision History
  22 
  23    April 6, 1994  (dp) Created
  24                        version 0.0 ALPHA
  25    April 10, 1994 (dp) Included cleanup, suggestions from J. P. Morrison.
  26                        version 0.1 ALPHA
  27    April 13, 1994 (dp) Included address probing from JPM, autoirq
  28                        version 0.2 ALPHA
  29    April 14, 1994 (ac) Sketched in the NET3 changes.
  30    April 17, 1994 (dp) Finished the NET3 changes. Used init_etherdev()
  31                        instead of kmalloc() to ensure that DMA buffers will
  32                        reside under the 16 meg line.
  33                        version 0.4 ALPHA
  34    April 18, 1994 (dp) Now using the kernel provided sk_buff handling functions.
  35                        Fixed a nasty problem with DMA.
  36                        version 0.5 ALPHA
  37    June 6, 1994 (ac)   Fixed to match the buffer locking changes. Added a hack to
  38                        fix a funny I see (search for HACK) and fixed the calls in
  39                        init() so it doesn't migrate module based ethernet cards up
  40                        to eth2 Took out the old module ideas as they are no longer
  41                        relevant to the PI driver.
  42    July 16, 1994 (dp)  Fixed the B channel rx overrun problem ac referred to 
  43                        above. Also added a bit of a hack to improve the maximum
  44                        baud rate on the B channel (Search for STUFF2). Included
  45                        ioctl stuff from John Paul Morrison. version 0.6 ALPHA
  46    Feb 9, 1995 (dp)    Updated for 1.1.90 kernel
  47                        version 0.7 ALPHA
  48    Apr 6, 1995 (ac)    Tweaks for NET3 pre snapshot 002 AX.25
  49    April 23, 1995 (dp) Fixed ioctl so it works properly with piconfig program
  50                        when changing the baud rate or clock mode.
  51                        version 0.8 ALPHA
  52          
  53 */
  54 
  55 /* The following #define invokes a hack that will improve performance (baud)
  56    for the B port. The up side is it makes 9600 baud work ok on the B port.
  57    It may do 38400, depending on the host. The down side is it burns up
  58    CPU cycles with ints locked for up to 1 character time, at the beginning
  59    of each transmitted packet. If this causes you to lose sleep, #undefine it.
  60 */
  61 
  62 #define STUFF2 1
  63 
  64 /* The default configuration */
  65 #define PI_DMA 3
  66 
  67 #define DEF_A_SPEED 0           /* 0 means external clock */
  68 #define DEF_A_TXDELAY 15        /* 15 mS transmit delay */
  69 #define DEF_A_PERSIST 128       /* 50% persistence */
  70 #define DEF_A_SLOTIME 15        /* 15 mS slot time */
  71 #define DEF_A_SQUELDELAY 1      /* 1 mS squelch delay - allows fcs and flag */
  72 #define DEF_A_CLOCKMODE 0       /* clock mode - 0 is normal */
  73 
  74 #define DEF_B_SPEED 1200        /* 1200 baud */
  75 #define DEF_B_TXDELAY 40        /* 400 mS */
  76 #define DEF_B_PERSIST 128       /* 50% */
  77 #define DEF_B_SLOTIME 30        /* 300 mS */
  78 #define DEF_B_SQUELDELAY 3      /* 30 mS */
  79 #define DEF_B_CLOCKMODE 0       /* Normal clock mode */
  80 
  81 struct device *init_etherdev(struct device *dev, int sizeof_private,
  82                              unsigned long *mem_startp);
  83 
  84 static char *version =
  85 "PI: V0.8 ALPHA April 23 1995 David Perry (dp@hydra.carleton.ca)\n";
  86 
  87 /* The following #define is only really required for the PI card, not
  88    the PI2 - but it's safer to leave it in. */
  89 #define REALLY_SLOW_IO 1
  90 
  91 #define PI2_MODULE 0
  92 
  93 #if PI2_MODULE > 0
  94 #include <linux/modules.h>
  95 #endif
  96 
  97 #include <linux/config.h>
  98 #include <linux/kernel.h>
  99 #include <linux/sched.h>
 100 #include <linux/types.h>
 101 #include <linux/fcntl.h>
 102 #include <linux/interrupt.h>
 103 #include <linux/ptrace.h>
 104 #include <linux/ioport.h>
 105 #include <linux/in.h>
 106 #include <linux/malloc.h>
 107 #include <linux/string.h>
 108 #include <linux/errno.h>
 109 #include <asm/system.h>
 110 #include <asm/bitops.h>
 111 #include <asm/io.h>
 112 #include <asm/dma.h>
 113 #include <asm/segment.h>
 114 #include <linux/inet.h>
 115 #include <linux/netdevice.h>
 116 #include <linux/etherdevice.h>
 117 #include <linux/skbuff.h>
 118 #include <linux/timer.h>
 119 #include "pi2.h"
 120 #include "z8530.h"
 121 #include <net/ax25.h>
 122 
 123 
 124 struct mbuf {
 125     struct mbuf *next;
 126     int cnt;
 127     char data[0];
 128 };
 129 
 130 /*
 131  *      The actual devices we will use
 132  */
 133  
 134 /*
 135  *      PI device declarations.
 136  */
 137  
 138 static int pi0_preprobe(struct device *dev){return 0;}  /* Dummy probe function */
     /*  */
 139 static struct device pi0a = { "pi0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 140 static struct device pi0b = { "pi0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 141 
 142  
 143 /* The number of low I/O ports used by the card. */
 144 #define PI_TOTAL_SIZE   8
 145 
 146 
 147 /* Index to functions, as function prototypes. */
 148 
 149 static int pi_probe(struct device *dev, int card_type);
 150 static int pi_open(struct device *dev);
 151 static int pi_send_packet(struct sk_buff *skb, struct device *dev);
 152 static void pi_interrupt(int reg_ptr, struct pt_regs *regs);
 153 static int pi_close(struct device *dev);
 154 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
 155 static struct enet_statistics *pi_get_stats(struct device *dev);
 156 static void rts(struct pi_local *lp, int x);
 157 static void b_rxint(struct device *dev, struct pi_local *lp);
 158 static void b_txint(struct pi_local *lp);
 159 static void b_exint(struct pi_local *lp);
 160 static void a_rxint(struct device *dev, struct pi_local *lp);
 161 static void a_txint(struct pi_local *lp);
 162 static void a_exint(struct pi_local *lp);
 163 static char *get_dma_buffer(unsigned long *mem_ptr);
 164 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize);
 165 
 166 static char ax25_bcast[7] =
 167 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
 168 static char ax25_test[7] =
 169 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
 170 
 171 static int ext2_secrm_seed = 152;       /* Random generator base */
 172 
 173 static inline unsigned char random(void)
     /*  */
 174 {
 175     return (unsigned char) (ext2_secrm_seed = ext2_secrm_seed
 176                             * 69069l + 1);
 177 }
 178 
 179 static inline void wrtscc(int cbase, int ctl, int sccreg, int val)
     /*  */
 180 {
 181     /* assume caller disables interrupts! */
 182     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 183     outb_p(sccreg, ctl);        /* Select register */
 184     outb_p(val, ctl);           /* Output value */
 185     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 186 }
 187 
 188 static inline int rdscc(int cbase, int ctl, int sccreg)
     /*  */
 189 {
 190     int retval;
 191 
 192     /* assume caller disables interrupts! */
 193     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 194     outb_p(sccreg, ctl);        /* Select register */
 195     retval = inb_p(ctl);
 196     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 197     return retval;
 198 }
 199 
 200 static void switchbuffers(struct pi_local *lp)
     /*  */
 201 {
 202     if (lp->rcvbuf == lp->rxdmabuf1)
 203         lp->rcvbuf = lp->rxdmabuf2;
 204     else
 205         lp->rcvbuf = lp->rxdmabuf1;
 206 }
 207 
 208 static void hardware_send_packet(struct pi_local *lp, struct sk_buff *skb)
     /*  */
 209 {
 210     char kickflag;
 211     unsigned long flags;
 212 
 213     lp->stats.tx_packets++;
 214 
 215     save_flags(flags);
 216     cli();
 217     kickflag = (skb_peek(&lp->sndq) == NULL) && (lp->sndbuf == NULL);
 218     restore_flags(flags);
 219 
 220     skb_queue_tail(&lp->sndq, skb);
 221     if (kickflag) {
 222         /* simulate interrupt to xmit */
 223         switch (lp->base & 2) {
 224         case 2:
 225             a_txint(lp);        /* process interrupt */
 226             break;
 227         case 0:
 228             save_flags(flags);
 229             cli();
 230             if (lp->tstate == IDLE)
 231                 b_txint(lp);
 232             restore_flags(flags);
 233             break;
 234         }
 235     }
 236 }
 237 
 238 static void setup_rx_dma(struct pi_local *lp)
     /*  */
 239 {
 240     unsigned long flags;
 241     int cmd;
 242     unsigned long dma_abs;
 243     unsigned dmachan;
 244 
 245     save_flags(flags);
 246     cli();
 247 
 248     dma_abs = (unsigned long) (lp->rcvbuf->data);
 249     dmachan = lp->dmachan;
 250     cmd = lp->base + CTL;
 251 
 252     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 253         panic("PI: RX buffer violates DMA boundary!");
 254 
 255     /* Get ready for RX DMA */
 256     wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 257 
 258     disable_dma(dmachan);
 259     clear_dma_ff(dmachan);
 260 
 261     /* Set DMA mode register to single transfers, incrementing address,
 262      *  auto init, writes
 263      */
 264     set_dma_mode(dmachan, DMA_MODE_READ | 0x10);
 265     set_dma_addr(dmachan, dma_abs);
 266     set_dma_count(dmachan, lp->bufsiz);
 267     enable_dma(dmachan);
 268 
 269     /* If a packet is already coming in, this line is supposed to
 270            avoid receiving a partial packet.
 271      */
 272     wrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
 273 
 274     /* Enable RX dma */
 275     wrtscc(lp->cardbase, cmd, R1,
 276       WT_RDY_ENAB | WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 277 
 278     restore_flags(flags);
 279 }
 280 
 281 static void setup_tx_dma(struct pi_local *lp, int length)
     /*  */
 282 {
 283     unsigned long dma_abs;
 284     unsigned long flags;
 285     unsigned long dmachan;
 286 
 287     save_flags(flags);
 288     cli();
 289 
 290     dmachan = lp->dmachan;
 291     dma_abs = (unsigned long) (lp->txdmabuf);
 292 
 293     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 294         panic("PI: TX buffer violates DMA boundary!");
 295 
 296     disable_dma(dmachan);
 297     /* Set DMA mode register to single transfers, incrementing address,
 298      *  no auto init, reads
 299      */
 300     set_dma_mode(dmachan, DMA_MODE_WRITE);
 301     clear_dma_ff(dmachan);
 302     set_dma_addr(dmachan, dma_abs);
 303     /* output byte count */
 304     set_dma_count(dmachan, length);
 305 
 306     restore_flags(flags);
 307 }
 308 
 309 static void tdelay(struct pi_local *lp, int time)
     /*  */
 310 {
 311     int port;
 312     unsigned int t1;
 313     unsigned char sc;
 314 
 315     if (lp->base & 2) {         /* If A channel */
 316         sc = SC1;
 317         t1 = time;
 318         port = lp->cardbase + TMR1;
 319     } else {
 320         sc = SC2;
 321         t1 = 10 * time;         /* 10s of milliseconds for the B channel */
 322         port = lp->cardbase + TMR2;
 323         wrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
 324     }
 325 
 326     /* Setup timer sc */
 327     outb_p(sc | LSB_MSB | MODE0, lp->cardbase + TMRCMD);
 328 
 329     /* times 2 to make millisecs */
 330     outb_p((t1 << 1) & 0xFF, port);
 331     outb_p((t1 >> 7) & 0xFF, port);
 332 
 333     /* Enable correct int for timeout */
 334     wrtscc(lp->cardbase, lp->base + CTL, R15, CTSIE);
 335     wrtscc(lp->cardbase, lp->base + CTL, R0, RES_EXT_INT);
 336 }
 337 
 338 static void free_p(struct sk_buff *skb)
     /*  */
 339 {
 340         dev_kfree_skb(skb, FREE_WRITE);
 341 }
 342 
 343 static void a_txint(struct pi_local *lp)
     /*  */
 344 {
 345     int cmd;
 346     unsigned long flags;
 347 
 348     save_flags(flags);
 349     cli();
 350 
 351     cmd = CTL + lp->base;
 352 
 353     switch (lp->tstate) {
 354     case IDLE:
 355         /* Transmitter idle. Find a frame for transmission */
 356         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 357             rts(lp, OFF);
 358             restore_flags(flags);
 359             return;
 360         }
 361         /* If a buffer to send, we drop thru here */
 362     case DEFER:
 363         /* we may have deferred prev xmit attempt */
 364         /* Check DCD - debounce it
 365          * See Intel Microcommunications Handbook, p2-308
 366          */
 367         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 368         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 369         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 370             lp->tstate = DEFER;
 371             tdelay(lp, 100);
 372             /* defer until DCD transition or timeout */
 373             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 374             restore_flags(flags);
 375             return;
 376         }
 377         if (random() > lp->persist) {
 378             lp->tstate = DEFER;
 379             tdelay(lp, lp->slotime);
 380             restore_flags(flags);
 381             return;
 382         }
 383         /* Assert RTS early minimize collision window */
 384         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 385         rts(lp, ON);            /* Transmitter on */
 386         lp->tstate = ST_TXDELAY;
 387         tdelay(lp, lp->txdelay);
 388         restore_flags(flags);
 389         return;
 390     default:
 391         break;
 392     }                           /* end switch(lp->state) */
 393 
 394     restore_flags(flags);
 395 }                               /*a_txint */
 396 
 397 static void a_exint(struct pi_local *lp)
     /*  */
 398 {
 399     unsigned long flags;
 400     int cmd;
 401     char st;
 402     int length;
 403 
 404     save_flags(flags);
 405     cli();                      /* disable interrupts */
 406 
 407     st = rdscc(lp->cardbase, lp->base + CTL, R0);       /* Fetch status */
 408 
 409     /* reset external status latch */
 410     wrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
 411     cmd = lp->base + CTL;
 412 
 413     if ((lp->rstate >= ACTIVE) && (st & BRK_ABRT)) {
 414         setup_rx_dma(lp);
 415         lp->rstate = ACTIVE;
 416     }
 417     switch (lp->tstate) {
 418     case ACTIVE:
 419         free_p(lp->sndbuf);
 420         lp->sndbuf = NULL;
 421         lp->tstate = FLAGOUT;
 422         tdelay(lp, lp->squeldelay);
 423         break;
 424     case FLAGOUT:
 425         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 426             /* Nothing to send - return to receive mode */
 427             lp->tstate = IDLE;
 428             rts(lp, OFF);
 429             restore_flags(flags);
 430             return;
 431         }
 432         /* NOTE - fall through if more to send */
 433     case ST_TXDELAY:
 434         /* Disable DMA chan */
 435         disable_dma(lp->dmachan);
 436 
 437         /* Set up for TX dma */
 438         wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
 439 
 440 
 441         /* Get all chars */
 442         /* Strip KISS control byte */
 443         length = lp->sndbuf->len - 1;
 444         memcpy(lp->txdmabuf, &lp->sndbuf->data[1], length);
 445 
 446 
 447         /* Setup DMA controller for tx */
 448         setup_tx_dma(lp, length);
 449 
 450         /* select transmit interrupts to enable */
 451         /* Allow DMA on chan */
 452         enable_dma(lp->dmachan);
 453 
 454         /* reset CRC, Txint pend*/
 455         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
 456 
 457         /* allow Underrun int only */
 458         wrtscc(lp->cardbase, cmd, R15, TxUIE);
 459 
 460         /* Enable TX DMA */
 461         wrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
 462 
 463         /* Send CRC on underrun */
 464         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
 465 
 466 
 467         /* packet going out now */
 468         lp->tstate = ACTIVE;
 469         break;
 470     case DEFER:
 471         /* we have deferred prev xmit attempt
 472          * See Intel Microcommunications Handbook, p2-308
 473          */
 474         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 475         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 476         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 477             lp->tstate = DEFER;
 478             tdelay(lp, 100);
 479             /* Defer until dcd transition or 100mS timeout */
 480             wrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
 481             restore_flags(flags);
 482             return;
 483         }
 484         if (random() > lp->persist) {
 485             lp->tstate = DEFER;
 486             tdelay(lp, lp->slotime);
 487             restore_flags(flags);
 488             return;
 489         }
 490         /* Assert RTS early minimize collision window */
 491         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 492         rts(lp, ON);            /* Transmitter on */
 493         lp->tstate = ST_TXDELAY;
 494         tdelay(lp, lp->txdelay);
 495         restore_flags(flags);
 496         return;
 497     }                           /* switch(lp->tstate) */
 498 
 499     restore_flags(flags);
 500 }                               /* a_exint() */
 501 
 502 /* Receive interrupt handler for the A channel
 503  */
 504 static void a_rxint(struct device *dev, struct pi_local *lp)
     /*  */
 505 {
 506     unsigned long flags;
 507     int cmd;
 508     int bytecount;
 509     char rse;
 510     struct sk_buff *skb;
 511     int sksize, pkt_len;
 512     struct mbuf *cur_buf;
 513     unsigned char *cfix;
 514 
 515     save_flags(flags);
 516     cli();                      /* disable interrupts */
 517     cmd = lp->base + CTL;
 518 
 519     rse = rdscc(lp->cardbase, cmd, R1); /* Get special condition bits from R1 */
 520     if (rse & Rx_OVR)
 521         lp->rstate = RXERROR;
 522 
 523     if (rse & END_FR) {
 524         /* If end of frame */
 525         /* figure length of frame from 8237 */
 526         clear_dma_ff(lp->dmachan);
 527         bytecount = lp->bufsiz - get_dma_residue(lp->dmachan);
 528 
 529         if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (bytecount < 10)) {
 530             if ((bytecount >= 10) && (rse & CRC_ERR)) {
 531                 lp->stats.rx_crc_errors++;
 532             }
 533             if (lp->rstate == RXERROR) {
 534                 lp->stats.rx_errors++;
 535                 lp->stats.rx_over_errors++;
 536             }
 537             /* Reset buffer pointers */
 538             lp->rstate = ACTIVE;
 539             setup_rx_dma(lp);
 540         } else {
 541             /* Here we have a valid frame */
 542             /* Toss 2 crc bytes , add one for KISS */
 543             pkt_len = lp->rcvbuf->cnt = bytecount - 2 + 1;
 544 
 545             /* Get buffer for next frame */
 546             cur_buf = lp->rcvbuf;
 547             switchbuffers(lp);
 548             setup_rx_dma(lp);
 549 
 550 
 551             /* Malloc up new buffer. */
 552             sksize = pkt_len;
 553 
 554             skb = dev_alloc_skb(sksize);
 555             if (skb == NULL) {
 556                 printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 557                 lp->stats.rx_dropped++;
 558                 restore_flags(flags);
 559                 return;
 560             }
 561             skb->dev = dev;
 562 
 563             /* KISS kludge -  prefix with a 0 byte */
 564             cfix=skb_put(skb,pkt_len);
 565             *cfix++=0;
 566             /* 'skb->data' points to the start of sk_buff data area. */
 567             memcpy(cfix, (char *) cur_buf->data,
 568                    pkt_len - 1);
 569             skb->protocol=htons(ETH_P_AX25);
 570             skb->mac.raw=skb->data;
 571             IS_SKB(skb);
 572             netif_rx(skb);
 573             lp->stats.rx_packets++;
 574         }                       /* end good frame */
 575     }                           /* end EOF check */
 576     wrtscc(lp->cardbase, lp->base + CTL, R0, ERR_RES);  /* error reset */
 577     restore_flags(flags);
 578 }
 579 
 580 static void b_rxint(struct device *dev, struct pi_local *lp)
     /*  */
 581 {
 582     unsigned long flags;
 583     int cmd;
 584     char rse;
 585     struct sk_buff *skb;
 586     int sksize;
 587     int pkt_len;
 588     unsigned char *cfix;
 589 
 590     save_flags(flags);
 591     cli();                      /* disable interrupts */
 592     cmd = CTL + lp->base;
 593 
 594     rse = rdscc(lp->cardbase, cmd, R1); /* get status byte from R1 */
 595 
 596     if ((rdscc(lp->cardbase, cmd, R0)) & Rx_CH_AV) {
 597         /* there is a char to be stored
 598          * read special condition bits before reading the data char
 599          */
 600         if (rse & Rx_OVR) {
 601             /* Rx overrun - toss buffer */
 602             /* reset buffer pointers */
 603             lp->rcp = lp->rcvbuf->data;
 604             lp->rcvbuf->cnt = 0;
 605 
 606             lp->rstate = RXERROR;       /* set error flag */
 607             lp->stats.rx_errors++;
 608             lp->stats.rx_over_errors++;
 609         } else if (lp->rcvbuf->cnt >= lp->bufsiz) {
 610             /* Too large -- toss buffer */
 611             /* reset buffer pointers */
 612             lp->rcp = lp->rcvbuf->data;
 613             lp->rcvbuf->cnt = 0;
 614             lp->rstate = TOOBIG;/* when set, chars are not stored */
 615         }
 616         /* ok, we can store the received character now */
 617         if (lp->rstate == ACTIVE) {     /* If no errors... */
 618             *lp->rcp++ = rdscc(lp->cardbase, cmd, R8);  /* char to rcv buff */
 619             lp->rcvbuf->cnt++;  /* bump count */
 620         } else {
 621             /* got to empty FIFO */
 622             (void) rdscc(lp->cardbase, cmd, R8);
 623             wrtscc(lp->cardbase, cmd, R0, ERR_RES);     /* reset err latch */
 624             lp->rstate = ACTIVE;
 625         }
 626     }
 627     if (rse & END_FR) {
 628         /* END OF FRAME -- Make sure Rx was active */
 629         if (lp->rcvbuf->cnt > 0) {
 630             if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (lp->rcvbuf->cnt < 10)) {
 631                 if ((lp->rcvbuf->cnt >= 10) && (rse & CRC_ERR)) {
 632                     lp->stats.rx_crc_errors++;
 633                 }
 634                 lp->rcp = lp->rcvbuf->data;
 635                 lp->rcvbuf->cnt = 0;
 636             } else {
 637                 /* Here we have a valid frame */
 638                 pkt_len = lp->rcvbuf->cnt -= 2; /* Toss 2 crc bytes */
 639                 pkt_len += 1;   /* Make room for KISS control byte */
 640 
 641                 /* Malloc up new buffer. */
 642                 sksize = pkt_len;
 643                 skb = dev_alloc_skb(sksize);
 644                 if (skb == NULL) {
 645                     printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 646                     lp->stats.rx_dropped++;
 647                     restore_flags(flags);
 648                     return;
 649                 }
 650                 skb->dev = dev;
 651 
 652                 /* KISS kludge -  prefix with a 0 byte */
 653                 cfix=skb_put(skb,pkt_len);
 654                 *cfix++=0;
 655                 /* 'skb->data' points to the start of sk_buff data area. */
 656                 memcpy(cfix, lp->rcvbuf->data, pkt_len - 1);
 657                 skb->protocol=ntohs(ETH_P_AX25);
 658                 IS_SKB(skb);
 659                 netif_rx(skb);
 660                 lp->stats.rx_packets++;
 661                 /* packet queued - initialize buffer for next frame */
 662                 lp->rcp = lp->rcvbuf->data;
 663                 lp->rcvbuf->cnt = 0;
 664 
 665             }                   /* end good frame queued */
 666         }                       /* end check for active receive upon EOF */
 667         lp->rstate = ACTIVE;    /* and clear error status */
 668     }                           /* end EOF check */
 669     restore_flags(flags);
 670 }
 671 
 672 
 673 static void b_txint(struct pi_local *lp)
     /*  */
 674 {
 675     unsigned long flags;
 676     int cmd;
 677     unsigned char c;
 678 
 679     save_flags(flags);
 680     cli();
 681     cmd = CTL + lp->base;
 682 
 683     switch (lp->tstate) {
 684     case CRCOUT:
 685         lp->tstate = FLAGOUT;
 686         tdelay(lp, lp->squeldelay);
 687         restore_flags(flags);
 688         return;
 689     case IDLE:
 690         /* Transmitter idle. Find a frame for transmission */
 691         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 692             /* Nothing to send - return to receive mode
 693              * Tx OFF now - flag should have gone
 694              */
 695             rts(lp, OFF);
 696          
 697             restore_flags(flags);
 698             return;
 699         }
 700         lp->txptr = lp->sndbuf->data;
 701         lp->txptr++;            /* Ignore KISS control byte */
 702         lp->txcnt = (int) lp->sndbuf->len - 1;
 703         /* If a buffer to send, we drop thru here */
 704     case DEFER:         /* we may have deferred prev xmit attempt */
 705         /* Check DCD - debounce it */
 706         /* See Intel Microcommunications Handbook, p2-308 */
 707         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 708         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 709         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 710             lp->tstate = DEFER;
 711             tdelay(lp, 100);
 712             /* defer until DCD transition or timeout */
 713             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 714             restore_flags(flags);
 715             return;
 716         }
 717         if (random() > lp->persist) {
 718             lp->tstate = DEFER;
 719             tdelay(lp, lp->slotime);
 720             restore_flags(flags);
 721             return;
 722         }
 723         rts(lp, ON);            /* Transmitter on */
 724         lp->tstate = ST_TXDELAY;
 725         tdelay(lp, lp->txdelay);
 726         restore_flags(flags);
 727         return;
 728 
 729     case ACTIVE:
 730         /* Here we are actively sending a frame */
 731         if (lp->txcnt--) {
 732             c = *lp->txptr++;
 733             /* next char is gone */
 734             wrtscc(lp->cardbase, cmd, R8, c);
 735             /* stuffing a char satisfies Interrupt condition */
 736         } else {
 737             /* No more to send */
 738             free_p(lp->sndbuf);
 739             lp->sndbuf = NULL;
 740             if ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
 741                 /* Did we underrun? */
 742                 /* unexpected underrun */
 743                 lp->stats.tx_errors++;
 744                 lp->stats.tx_fifo_errors++;
 745                 wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 746                 lp->tstate = FLAGOUT;
 747                 tdelay(lp, lp->squeldelay);
 748                 restore_flags(flags);
 749                 return;
 750             }
 751             lp->tstate = UNDERRUN;      /* Now we expect to underrun */
 752             /* Send flags on underrun */
 753             if (lp->speed) {    /* If internally clocked */
 754                 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
 755             } else {
 756                 wrtscc(lp->cardbase, cmd, R10, CRCPS);
 757             }
 758             wrtscc(lp->cardbase, cmd, R0, RES_Tx_P);    /* reset Tx Int Pend */
 759         }
 760         restore_flags(flags);
 761         return;                 /* back to wait for interrupt */
 762     }                           /* end switch */
 763     restore_flags(flags);
 764 }
 765 
 766 /* Pi SIO External/Status interrupts (for the B channel)
 767  * This can be caused by a receiver abort, or a Tx UNDERRUN/EOM.
 768  * Receiver automatically goes to Hunt on an abort.
 769  *
 770  * If the Tx Underrun interrupt hits, change state and
 771  * issue a reset command for it, and return.
 772  */
 773 static void b_exint(struct pi_local *lp)
     /*  */
 774 {
 775     unsigned long flags;
 776     char st;
 777     int cmd;
 778     char c;
 779 
 780     cmd = CTL + lp->base;
 781     save_flags(flags);
 782     cli();                      /* disable interrupts */
 783     st = rdscc(lp->cardbase, cmd, R0);  /* Fetch status */
 784     /* reset external status latch */
 785     wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 786 
 787 
 788     switch (lp->tstate) {
 789     case ACTIVE:                /* Unexpected underrun */
 790         free_p(lp->sndbuf);
 791         lp->sndbuf = NULL;
 792         wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 793         lp->tstate = FLAGOUT;
 794         lp->stats.tx_errors++;
 795         lp->stats.tx_fifo_errors++;
 796         tdelay(lp, lp->squeldelay);
 797         restore_flags(flags);
 798         return;
 799     case UNDERRUN:
 800         lp->tstate = CRCOUT;
 801         restore_flags(flags);
 802         return;
 803     case FLAGOUT:
 804         /* Find a frame for transmission */
 805         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 806             /* Nothing to send - return to receive mode
 807              * Tx OFF now - flag should have gone
 808              */
 809             rts(lp, OFF);
 810             lp->tstate = IDLE;
 811             restore_flags(flags);
 812             return;
 813         }
 814         lp->txptr = lp->sndbuf->data;
 815         lp->txptr++;            /* Ignore KISS control byte */
 816         lp->txcnt = (int) lp->sndbuf->len - 1;
 817         /* Get first char to send */
 818         lp->txcnt--;
 819         c = *lp->txptr++;
 820         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 821 
 822         /* Send abort on underrun */
 823         if (lp->speed) {        /* If internally clocked */
 824             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 825         } else {
 826             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 827         }
 828 
 829         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 830         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 831 
 832 #ifdef STUFF2
 833         /* stuff an extra one if we can */
 834         if (lp->txcnt) {
 835             lp->txcnt--;
 836             c = *lp->txptr++;
 837             /* Wait for tx buffer empty */
 838             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 839                 ;   
 840             wrtscc(lp->cardbase, cmd, R8, c);
 841         }
 842 #endif
 843 
 844         /* select transmit interrupts to enable */
 845 
 846         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 847         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 848         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);       /* Tx/Ext ints */
 849 
 850         lp->tstate = ACTIVE;    /* char going out now */
 851         restore_flags(flags);
 852         return;
 853 
 854     case DEFER:
 855         /* Check DCD - debounce it
 856          * See Intel Microcommunications Handbook, p2-308
 857          */
 858         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 859         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 860         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 861             lp->tstate = DEFER;
 862             tdelay(lp, 100);
 863             /* defer until DCD transition or timeout */
 864             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 865             restore_flags(flags);
 866             return;
 867         }
 868         if (random() > lp->persist) {
 869             lp->tstate = DEFER;
 870             tdelay(lp, lp->slotime);
 871             restore_flags(flags);
 872             return;
 873         }
 874         rts(lp, ON);            /* Transmitter on */
 875         lp->tstate = ST_TXDELAY;
 876         tdelay(lp, lp->txdelay);
 877         restore_flags(flags);
 878         return;
 879 
 880     case ST_TXDELAY:
 881 
 882         /* Get first char to send */
 883         lp->txcnt--;
 884         c = *lp->txptr++;
 885         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 886 
 887         /* Send abort on underrun */
 888         if (lp->speed) {        /* If internally clocked */
 889             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 890         } else {
 891             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 892         }
 893 
 894         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 895         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 896 
 897 #ifdef STUFF2
 898         /* stuff an extra one if we can */
 899         if (lp->txcnt) {
 900             lp->txcnt--;
 901             c = *lp->txptr++;
 902             /* Wait for tx buffer empty */
 903             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 904                 ;   
 905             wrtscc(lp->cardbase, cmd, R8, c);
 906         }
 907 #endif
 908 
 909         /* select transmit interrupts to enable */
 910 
 911         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 912         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 913         /* Tx/Extern ints on */
 914         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
 915 
 916         lp->tstate = ACTIVE;    /* char going out now */
 917         restore_flags(flags);
 918         return;
 919     }
 920 
 921     /* Receive Mode only
 922      * This triggers when hunt mode is entered, & since an ABORT
 923      * automatically enters hunt mode, we use that to clean up
 924      * any waiting garbage
 925      */
 926     if ((lp->rstate == ACTIVE) && (st & BRK_ABRT)) {
 927         (void) rdscc(lp->cardbase, cmd, R8);
 928         (void) rdscc(lp->cardbase, cmd, R8);
 929         (void) rdscc(lp->cardbase, cmd, R8);
 930         lp->rcp = lp->rcvbuf->data;
 931         lp->rcvbuf->cnt = 0;    /* rewind on DCD transition */
 932     }
 933     restore_flags(flags);
 934 }
 935 
 936 /* Probe for a PI card. */
 937 /* This routine also initializes the timer chip */
 938 
 939 static int hw_probe(int ioaddr)
     /*  */
 940 {
 941     int time = 1000;            /* Number of milliseconds for test */
 942     unsigned long start_time, end_time;
 943 
 944     int base, tmr0, tmr1, tmrcmd;
 945     int a = 1;
 946     int b = 1;
 947 
 948     base = ioaddr & 0x3f0;
 949     tmr0 = TMR0 + base;
 950     tmr1 = TMR1 + base;
 951     tmrcmd = TMRCMD + base;
 952 
 953     /* Set up counter chip timer 0 for 500 uS period square wave */
 954     /* assuming a 3.68 mhz clock for now */
 955     outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 956     outb_p(922 & 0xFF, tmr0);
 957     outb_p(922 >> 8, tmr0);
 958 
 959     /* Setup timer control word for timer 1*/
 960     outb_p(SC1 | LSB_MSB | MODE0, tmrcmd);
 961     outb_p((time << 1) & 0xFF, tmr1);
 962     outb_p((time >> 7) & 0XFF, tmr1);
 963 
 964     /* wait until counter reg is loaded */
 965     do {
 966         /* Latch count for reading */
 967         outb_p(SC1, tmrcmd);
 968         a = inb_p(tmr1);
 969         b = inb_p(tmr1);
 970     } while (b == 0);
 971     start_time = jiffies;
 972     while (b != 0) {
 973         /* Latch count for reading */
 974         outb_p(SC1, tmrcmd);
 975         a = inb_p(tmr1);
 976         b = inb_p(tmr1);
 977         end_time = jiffies;
 978         /* Don't wait forever - there may be no card here */
 979         if ((end_time - start_time) > 200)
 980             return 0;           /* No card found */
 981     }
 982     end_time = jiffies;
 983     /* 87 jiffies, for a 3.68 mhz clock, half that for a double speed clock */
 984     if ((end_time - start_time) > 65) {
 985         return (1);             /* PI card found */
 986     } else {
 987         /* Faster crystal - tmr0 needs adjusting */
 988         /* Set up counter chip */
 989         /* 500 uS square wave */
 990         outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 991         outb_p(1844 & 0xFF, tmr0);
 992         outb_p(1844 >> 8, tmr0);
 993         return (2);             /* PI2 card found */
 994     }
 995 }
 996 
 997 static void rts(struct pi_local *lp, int x)
     /*  */
 998 {
 999     int tc;
1000     long br;
1001     int cmd;
1002     int dummy;
1003 
1004     /* assumes interrupts are off */
1005     cmd = CTL + lp->base;
1006 
1007     /* Reprogram BRG and turn on transmitter to send flags */
1008     if (x == ON) {              /* Turn Tx ON and Receive OFF */
1009         /* Exints off first to avoid abort int */
1010         wrtscc(lp->cardbase, cmd, R15, 0);
1011         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Rx off */
1012         lp->rstate = IDLE;
1013         if (cmd & 2) {          /* if channel a */
1014             /* Set up for TX dma */
1015             wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
1016         } else {
1017             wrtscc(lp->cardbase, cmd, R1, 0);   /* No interrupts */
1018         }
1019 
1020         if (!lp->clockmode) {
1021             if (lp->speed) {    /* if internally clocked */
1022                 br = lp->speed; /* get desired speed */
1023                 tc = (lp->xtal / br) - 2;       /* calc 1X BRG divisor */
1024                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1025                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1026             }
1027         }
1028         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
1029         /* Transmitter now on */
1030     } else {                    /* Tx OFF and Rx ON */
1031         lp->tstate = IDLE;
1032         wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);       /*  TX off */
1033 
1034         if (!lp->clockmode) {
1035             if (lp->speed) {    /* if internally clocked */
1036                 /* Reprogram BRG for 32x clock for receive DPLL */
1037                 /* BRG off, keep Pclk source */
1038                 wrtscc(lp->cardbase, cmd, R14, BRSRC);
1039                 br = lp->speed; /* get desired speed */
1040                 /* calc 32X BRG divisor */
1041                 tc = ((lp->xtal / 32) / br) - 2;
1042                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1043                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1044                 /* SEARCH mode, BRG source */
1045                 wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
1046                 /* Enable the BRG */
1047                 wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
1048             }
1049         }
1050         /* Flush rx fifo */
1051         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Make sure rx is off */
1052         wrtscc(lp->cardbase, cmd, R0, ERR_RES); /* reset err latch */
1053         dummy = rdscc(lp->cardbase, cmd, R1);   /* get status byte from R1 */
1054         (void) rdscc(lp->cardbase, cmd, R8);
1055         (void) rdscc(lp->cardbase, cmd, R8);
1056 
1057         (void) rdscc(lp->cardbase, cmd, R8);
1058 
1059         /* Now, turn on the receiver and hunt for a flag */
1060         wrtscc(lp->cardbase, cmd, R3, RxENABLE | Rx8);
1061         lp->rstate = ACTIVE;    /* Normal state */
1062 
1063         if (cmd & 2) {          /* if channel a */
1064             setup_rx_dma(lp);
1065         } else {
1066             /* reset buffer pointers */
1067             lp->rcp = lp->rcvbuf->data;
1068             lp->rcvbuf->cnt = 0;
1069             wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1070         }
1071         wrtscc(lp->cardbase, cmd, R15, BRKIE);  /* allow ABORT int */
1072     }
1073 }
1074 
1075 /* Fill in the MAC-level header. */
1076 static int pi_header(struct sk_buff *skb, struct device *dev, unsigned short type,
     /*  */
1077              void *daddr, void *saddr, unsigned len)
1078 {
1079     return ax25_encapsulate(skb, dev, type, daddr, saddr, len);
1080 }
1081 
1082 /* Rebuild the MAC-level header. */
1083 static int pi_rebuild_header(void *buff, struct device *dev, unsigned long raddr,
     /*  */
1084                              struct sk_buff *skb)
1085 {
1086     return ax25_rebuild_header(buff, dev, raddr, skb);
1087 }
1088 
1089 static void scc_init(struct device *dev)
     /*  */
1090 {
1091     unsigned long flags;
1092     struct pi_local *lp = (struct pi_local *) dev->priv;
1093 
1094     int tc;
1095     long br;
1096     register int cmd;
1097 
1098     /* Initialize 8530 channel for SDLC operation */
1099 
1100     cmd = CTL + lp->base;
1101     save_flags(flags);
1102     cli();
1103 
1104     switch (cmd & CHANA) {
1105     case CHANA:
1106         wrtscc(lp->cardbase, cmd, R9, CHRA);    /* Reset channel A */
1107         wrtscc(lp->cardbase, cmd, R2, 0xff);    /* Initialize interrupt vector */
1108         break;
1109     default:
1110         wrtscc(lp->cardbase, cmd, R9, CHRB);    /* Reset channel B */
1111         break;
1112     }
1113 
1114     /* Deselect all Rx and Tx interrupts */
1115     wrtscc(lp->cardbase, cmd, R1, 0);
1116 
1117     /* Turn off external interrupts (like CTS/CD) */
1118     wrtscc(lp->cardbase, cmd, R15, 0);
1119 
1120     /* X1 clock, SDLC mode */
1121     wrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
1122 
1123     /* Tx/Rx parameters */
1124     if (lp->speed) {            /* Use internal clocking */
1125         wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
1126         if (!lp->clockmode)
1127             /* Tx Clk from BRG. Rcv Clk from DPLL, TRxC pin outputs DPLL */
1128             wrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
1129         else
1130             /* Tx Clk from DPLL, Rcv Clk from DPLL, TRxC Outputs BRG */
1131             wrtscc(lp->cardbase, cmd, R11, TCDPLL | RCDPLL | TRxCBR | TRxCOI);
1132     } else {                    /* Use external clocking */
1133         wrtscc(lp->cardbase, cmd, R10, CRCPS);
1134         /* Tx Clk from Trxcl. Rcv Clk from Rtxcl, TRxC pin is input */
1135         wrtscc(lp->cardbase, cmd, R11, TCTRxCP);
1136     }
1137 
1138     /* Null out SDLC start address */
1139     wrtscc(lp->cardbase, cmd, R6, 0);
1140 
1141     /* SDLC flag */
1142     wrtscc(lp->cardbase, cmd, R7, FLAG);
1143 
1144     /* Set up the Transmitter but don't enable it
1145      *  DTR, 8 bit TX chars only
1146      */
1147     wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
1148 
1149     /* Receiver initial setup */
1150     wrtscc(lp->cardbase, cmd, R3, Rx8); /* 8 bits/char */
1151 
1152     /* Setting up BRG now - turn it off first */
1153     wrtscc(lp->cardbase, cmd, R14, BRSRC);      /* BRG off, keep Pclk source */
1154 
1155     /* set the 32x time constant for the BRG in Receive mode */
1156 
1157     if (lp->speed) {
1158         br = lp->speed;         /* get desired speed */
1159         tc = ((lp->xtal / 32) / br) - 2;        /* calc 32X BRG divisor */
1160     } else {
1161         tc = 14;
1162     }
1163 
1164     wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
1165     wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);   /* upper byte */
1166 
1167     /* Following subroutine sets up and ENABLES the receiver */
1168     rts(lp, OFF);               /* TX OFF and RX ON */
1169 
1170     if (lp->speed) {
1171         /* DPLL frm BRG, BRG src PCLK */
1172         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
1173     } else {
1174         /* DPLL frm rtxc,BRG src PCLK */
1175         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);
1176     }
1177     wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);     /* SEARCH mode, keep BRG src */
1178     wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);    /* Enable the BRG */
1179 
1180     if (!(cmd & 2))             /* if channel b */
1181         wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1182 
1183     wrtscc(lp->cardbase, cmd, R15, BRKIE);      /* ABORT int */
1184 
1185     /* Now, turn on the receiver and hunt for a flag */
1186     wrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | Rx8);
1187 
1188     restore_flags(flags);
1189 }
1190 
1191 static void chipset_init(struct device *dev)
     /*  */
1192 {
1193     int cardbase;
1194     unsigned long flags;
1195 
1196     cardbase = dev->base_addr & 0x3f0;
1197 
1198     save_flags(flags);
1199     cli();
1200     wrtscc(cardbase, dev->base_addr + CTL, R9, FHWRES); /* Hardware reset */
1201     /* Disable interrupts with master interrupt ctrl reg */
1202     wrtscc(cardbase, dev->base_addr + CTL, R9, 0);
1203     restore_flags(flags);
1204 
1205 }
1206 
1207 
1208 unsigned long pi_init(unsigned long mem_start, unsigned long mem_end)
     /*  */
1209 {
1210     int *port;
1211     int ioaddr = 0;
1212     int card_type = 0;
1213     int ports[] =
1214     {0x380, 0x300, 0x320, 0x340, 0x360, 0x3a0, 0};
1215 
1216     printk(version);
1217 
1218     /* Only one card supported for now */
1219     for (port = &ports[0]; *port && !card_type; port++) {
1220         ioaddr = *port;
1221 
1222         if (check_region(ioaddr, PI_TOTAL_SIZE) == 0) {
1223             printk("PI: Probing for card at address %#3x\n",ioaddr);
1224             card_type = hw_probe(ioaddr);
1225         }
1226     }
1227 
1228     switch (card_type) {
1229     case 1:
1230         printk("PI: Found a PI card at address %#3x\n", ioaddr);
1231         break;
1232     case 2:
1233         printk("PI: Found a PI2 card at address %#3x\n", ioaddr);
1234         break;
1235     default:
1236         printk("PI: ERROR: No card found\n");
1237         return mem_start;
1238     }
1239 
1240     /* Link a couple of device structures into the chain */
1241     /* For the A port */
1242     /* Allocate space for 4 buffers even though we only need 3,
1243        because one of them may cross a DMA page boundary and
1244        be rejected by get_dma_buffer().
1245     */
1246     register_netdev(&pi0a);
1247     
1248     pi0a.priv=(void *)mem_start;
1249     mem_start+=sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4
1250                          + 8;   /* for alignment */
1251                         
1252     pi0a.dma = PI_DMA;
1253     pi0a.base_addr = ioaddr + 2;
1254     pi0a.irq = 0;
1255 
1256     /* And the B port */
1257     register_netdev(&pi0b);
1258     pi0b.base_addr = ioaddr;
1259     pi0b.irq = 0;
1260     pi0b.priv=(void *)mem_start;
1261     mem_start+=sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4
1262                          + 8;   /* for alignment */
1263 
1264     /* Now initialize them */
1265     pi_probe(&pi0a, card_type);
1266     pi_probe(&pi0b, card_type);
1267 
1268     pi0b.irq = pi0a.irq;        /* IRQ is shared */
1269     
1270     return mem_start;
1271 }
1272 
1273 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize)
     /*  */
1274 {
1275     if (((addr & 0xffff) + dev_buffsize) <= 0x10000)
1276         return 1;
1277     else
1278         return 0;
1279 }
1280 
1281 static int pi_set_mac_address(struct device *dev, void *addr)
     /*  */
1282 {
1283     memcpy(dev->dev_addr, addr, 7);     /* addr is an AX.25 shifted ASCII */
1284     return 0;                   /* mac address */
1285 }
1286 
1287 /* Allocate a buffer which does not cross a DMA page boundary */
1288 static char *
1289 get_dma_buffer(unsigned long *mem_ptr)
     /*  */
1290 {
1291     char *ret;
1292 
1293     ret = (char *)*mem_ptr;
1294 
1295     if(!valid_dma_page(*mem_ptr, DMA_BUFF_SIZE + sizeof(struct mbuf))){
1296         *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1297         ret = (char *)*mem_ptr;
1298     }
1299     *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1300     return (ret);
1301 }
1302 
1303 static int pi_probe(struct device *dev, int card_type)
     /*  */
1304 {
1305     short ioaddr;
1306     struct pi_local *lp;
1307     int i;
1308     unsigned long flags;
1309     unsigned long mem_ptr;
1310 
1311     ioaddr = dev->base_addr;
1312 
1313     /* Initialize the device structure. */
1314     /* Must be done before chipset_init */
1315     /* Make certain the data structures used by the PI2 are aligned. */
1316     dev->priv = (void *) (((int) dev->priv + 7) & ~7);
1317     lp = (struct pi_local *) dev->priv;
1318 
1319     memset(dev->priv, 0, sizeof(struct pi_local));
1320 
1321     /* Allocate some buffers which do not cross DMA page boundaries */
1322     mem_ptr = (unsigned long) dev->priv + sizeof(struct pi_local);
1323     lp->txdmabuf = get_dma_buffer(&mem_ptr);
1324     lp->rxdmabuf1 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1325     lp->rxdmabuf2 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1326 
1327     /* Initialize rx buffer */
1328     lp->rcvbuf = lp->rxdmabuf1;
1329     lp->rcp = lp->rcvbuf->data;
1330     lp->rcvbuf->cnt = 0;
1331 
1332     /* Initialize the transmit queue head structure */
1333     skb_queue_head_init(&lp->sndq);
1334 
1335     /* These need to be initialized before scc_init is called. */
1336     if (card_type == 1)
1337         lp->xtal = (unsigned long) SINGLE / 2;
1338     else
1339         lp->xtal = (unsigned long) DOUBLE / 2;
1340     lp->base = dev->base_addr;
1341     lp->cardbase = dev->base_addr & 0x3f0;
1342     if (dev->base_addr & CHANA) {
1343         lp->speed = DEF_A_SPEED;
1344         /* default channel access Params */
1345         lp->txdelay = DEF_A_TXDELAY;
1346         lp->persist = DEF_A_PERSIST;
1347         lp->slotime = DEF_A_SLOTIME;
1348         lp->squeldelay = DEF_A_SQUELDELAY;
1349         lp->clockmode = DEF_A_CLOCKMODE;
1350 
1351     } else {
1352         lp->speed = DEF_B_SPEED;
1353         /* default channel access Params */
1354         lp->txdelay = DEF_B_TXDELAY;
1355         lp->persist = DEF_B_PERSIST;
1356         lp->slotime = DEF_B_SLOTIME;
1357         lp->squeldelay = DEF_B_SQUELDELAY;
1358         lp->clockmode = DEF_B_CLOCKMODE;
1359     }
1360     lp->bufsiz = DMA_BUFF_SIZE;
1361     lp->tstate = IDLE;
1362 
1363     chipset_init(dev);
1364 
1365     if (dev->base_addr & CHANA) {       /* Do these things only for the A port */
1366         /* Note that a single IRQ services 2 devices (A and B channels) */
1367 
1368         lp->dmachan = dev->dma;
1369         if (lp->dmachan < 1 || lp->dmachan > 3)
1370             printk("PI: DMA channel %d out of range\n", lp->dmachan);
1371 
1372         /* chipset_init() was already called */
1373 
1374         if (dev->irq < 2) {
1375             autoirq_setup(0);
1376             save_flags(flags);
1377             cli();
1378             wrtscc(lp->cardbase, CTL + lp->base, R1, EXT_INT_ENAB);
1379             /* enable PI card interrupts */
1380             wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1381             restore_flags(flags);
1382             /* request a timer interrupt for 1 mS hence */
1383             tdelay(lp, 1);
1384             /* 20 "jiffies" should be plenty of time... */
1385             dev->irq = autoirq_report(20);
1386             if (!dev->irq) {
1387                 printk(". Failed to detect IRQ line.\n");
1388             }
1389             save_flags(flags);
1390             cli();
1391             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, FHWRES);     /* Hardware reset */
1392             /* Disable interrupts with master interrupt ctrl reg */
1393             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, 0);
1394             restore_flags(flags);
1395         }
1396 
1397         printk("PI: Autodetected IRQ %d, assuming DMA %d.\n",
1398                dev->irq, dev->dma);
1399 
1400         /* This board has jumpered interrupts. Snarf the interrupt vector
1401                    now.  There is no point in waiting since no other device can use
1402                    the interrupt, and this marks the 'irqaction' as busy. */
1403         {
1404             int irqval = request_irq(dev->irq, &pi_interrupt,0, "pi2");
1405             if (irqval) {
1406                 printk("PI: unable to get IRQ %d (irqval=%d).\n",
1407                        dev->irq, irqval);
1408                 return EAGAIN;
1409             }
1410         }
1411 
1412         /* Grab the region */
1413         snarf_region(ioaddr & 0x3f0, PI_TOTAL_SIZE);
1414 
1415 
1416     }                           /* Only for A port */
1417     dev->open = pi_open;
1418     dev->stop = pi_close;
1419     dev->do_ioctl = pi_ioctl;
1420     dev->hard_start_xmit = pi_send_packet;
1421     dev->get_stats = pi_get_stats;
1422 
1423     /* Fill in the fields of the device structure */
1424     for (i = 0; i < DEV_NUMBUFFS; i++)
1425         skb_queue_head_init(&dev->buffs[i]);
1426 
1427 
1428     dev->hard_header = pi_header;
1429     dev->rebuild_header = pi_rebuild_header;
1430     dev->set_mac_address = pi_set_mac_address;
1431 
1432     dev->type = ARPHRD_AX25;    /* AF_AX25 device */
1433     dev->hard_header_len = 17;  /* We don't do digipeaters */
1434     dev->mtu = 1500;            /* eth_mtu is the default */
1435     dev->addr_len = 7;          /* sizeof an ax.25 address */
1436     memcpy(dev->broadcast, ax25_bcast, 7);
1437     memcpy(dev->dev_addr, ax25_test, 7);
1438 
1439     /* New-style flags. */
1440     dev->flags = 0;
1441     dev->family = AF_INET;
1442     dev->pa_addr = 0;
1443     dev->pa_brdaddr = 0;
1444     dev->pa_mask = 0;
1445     dev->pa_alen = sizeof(unsigned long);
1446 
1447     return 0;
1448 }
1449 
1450 /* Open/initialize the board.  This is called (in the current kernel)
1451    sometime after booting when the 'ifconfig' program is run.
1452 
1453    This routine should set everything up anew at each open, even
1454    registers that "should" only need to be set once at boot, so that
1455    there is non-reboot way to recover if something goes wrong.
1456    */
1457 static int pi_open(struct device *dev)
     /*  */
1458 {
1459     unsigned long flags;
1460     static first_time = 1;
1461 
1462     struct pi_local *lp = (struct pi_local *) dev->priv;
1463 
1464     if (dev->base_addr & 2) {   /* if A channel */
1465         if (first_time) {
1466             if (request_dma(dev->dma,"pi2")) {
1467                 free_irq(dev->irq);
1468                 return -EAGAIN;
1469             }
1470             irq2dev_map[dev->irq] = dev;
1471         }
1472         /* Reset the hardware here. */
1473         chipset_init(dev);
1474     }
1475     lp->tstate = IDLE;
1476 
1477     if (dev->base_addr & 2) {   /* if A channel */
1478         scc_init(dev);          /* Called once for each channel */
1479         scc_init(dev->next);
1480     }
1481     /* master interrupt enable */
1482     save_flags(flags);
1483     cli();
1484     wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1485     restore_flags(flags);
1486 
1487     lp->open_time = jiffies;
1488 
1489     dev->tbusy = 0;
1490     dev->interrupt = 0;
1491     dev->start = 1;
1492     first_time = 0;
1493     return 0;
1494 }
1495 
1496 static int pi_send_packet(struct sk_buff *skb, struct device *dev)
     /*  */
1497 {
1498     struct pi_local *lp = (struct pi_local *) dev->priv;
1499 
1500     /* If some higher layer thinks we've missed an tx-done interrupt
1501            we are passed NULL. Caution: dev_tint() handles the cli()/sti()
1502            itself. */
1503     if (skb == NULL) {
1504         dev_tint(dev);
1505         return 0;
1506     }
1507     hardware_send_packet(lp, skb);
1508     dev->trans_start = jiffies;
1509 
1510     return 0;
1511 }
1512 
1513 /* The typical workload of the driver:
1514    Handle the network interface interrupts. */
1515 static void pi_interrupt(int reg_ptr, struct pt_regs *regs)
     /*  */
1516 {
1517 /*    int irq = -(((struct pt_regs *) reg_ptr)->orig_eax + 2);*/
1518     struct pi_local *lp;
1519     int st;
1520     unsigned long flags;
1521 
1522 /*    dev_b = dev_a->next;       Relies on the order defined in Space.c */
1523 
1524 #if 0
1525     if (dev_a == NULL) {
1526         printk("PI: pi_interrupt(): irq %d for unknown device.\n", irq);
1527         return;
1528     }
1529 #endif    
1530     /* Read interrupt status register (only valid from channel A)
1531      * Process all pending interrupts in while loop
1532      */
1533     lp = (struct pi_local *) pi0a.priv; /* Assume channel A */
1534     while ((st = rdscc(lp->cardbase, pi0a.base_addr | CHANA | CTL, R3)) != 0) {
1535         if (st & CHBTxIP) {
1536             /* Channel B Transmit Int Pending */
1537             lp = (struct pi_local *) pi0b.priv;
1538             b_txint(lp);
1539         } else if (st & CHARxIP) {
1540             /* Channel A Rcv Interrupt Pending */
1541             lp = (struct pi_local *) pi0a.priv;
1542             a_rxint(&pi0a, lp);
1543         } else if (st & CHATxIP) {
1544             /* Channel A Transmit Int Pending */
1545             lp = (struct pi_local *) pi0a.priv;
1546             a_txint(lp);
1547         } else if (st & CHAEXT) {
1548             /* Channel A External Status Int */
1549             lp = (struct pi_local *) pi0a.priv;
1550             a_exint(lp);
1551         } else if (st & CHBRxIP) {
1552             /* Channel B Rcv Interrupt Pending */
1553             lp = (struct pi_local *) pi0b.priv;
1554             b_rxint(&pi0b, lp);
1555         } else if (st & CHBEXT) {
1556             /* Channel B External Status Int */
1557             lp = (struct pi_local *) pi0b.priv;
1558             b_exint(lp);
1559         }
1560         /* Reset highest interrupt under service */
1561         save_flags(flags);
1562         cli();
1563         wrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
1564         restore_flags(flags);
1565     }                           /* End of while loop on int processing */
1566     return;
1567 }
1568 
1569 /* The inverse routine to pi_open(). */
1570 static int pi_close(struct device *dev)
     /*  */
1571 {
1572     unsigned long flags;
1573     struct pi_local *lp;
1574     struct sk_buff *ptr;
1575 
1576     save_flags(flags);
1577     cli();
1578 
1579     lp = (struct pi_local *) dev->priv;
1580     ptr = NULL;
1581 
1582     chipset_init(dev);          /* reset the scc */
1583     disable_dma(lp->dmachan);
1584 
1585     lp->open_time = 0;
1586 
1587     dev->tbusy = 1;
1588     dev->start = 0;
1589 
1590     /* Free any buffers left in the hardware transmit queue */
1591     while ((ptr = skb_dequeue(&lp->sndq)) != NULL)
1592         free_p(ptr);
1593 
1594     restore_flags(flags);
1595     return 0;
1596 }
1597 
1598 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
     /*  */
1599 {
1600     unsigned long flags;
1601     struct pi_req rq;
1602     struct pi_local *lp = (struct pi_local *) dev->priv;
1603 
1604     int ret = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct pi_req));
1605     if (ret)
1606         return ret;
1607         
1608     if(cmd!=SIOCDEVPRIVATE)
1609         return -EINVAL;
1610 
1611     memcpy_fromfs(&rq, ifr->ifr_data, sizeof(struct pi_req));
1612 
1613     switch (rq.cmd) {
1614     case SIOCSPIPARAM:
1615 
1616         if (!suser())
1617             return -EPERM;
1618         save_flags(flags);
1619         cli();
1620         lp->txdelay = rq.txdelay;
1621         lp->persist = rq.persist;
1622         lp->slotime = rq.slotime;
1623         lp->squeldelay = rq.squeldelay;
1624         lp->clockmode = rq.clockmode;
1625         lp->speed = rq.speed;
1626         pi_open(&pi0a); /* both channels get reset %%% */
1627         restore_flags(flags);
1628         ret = 0;
1629         break;
1630 
1631     case SIOCSPIDMA:
1632 
1633         if (!suser())
1634             return -EPERM;
1635         ret = 0;
1636         if (dev->base_addr & 2) {   /* if A channel */
1637            if (rq.dmachan < 1 || rq.dmachan > 3)
1638                 return -EINVAL;
1639            save_flags(flags);
1640            cli();
1641            pi_close(dev);
1642            free_dma(lp->dmachan);
1643            dev->dma = lp->dmachan = rq.dmachan;
1644            if (request_dma(lp->dmachan,"pi2")) 
1645                 ret = -EAGAIN;
1646            pi_open(dev);
1647            restore_flags(flags);
1648         }
1649         break;
1650 
1651     case SIOCSPIIRQ:
1652         ret = -EINVAL;      /* add this later */
1653         break;
1654 
1655     case SIOCGPIPARAM:
1656     case SIOCGPIDMA:
1657     case SIOCGPIIRQ:
1658 
1659         rq.speed = lp->speed;
1660         rq.txdelay = lp->txdelay;
1661         rq.persist = lp->persist;
1662         rq.slotime = lp->slotime;
1663         rq.squeldelay = lp->squeldelay;
1664         rq.clockmode = lp->clockmode;
1665         rq.dmachan = lp->dmachan;
1666         rq.irq = dev->irq;
1667         memcpy_tofs(ifr->ifr_data, &rq, sizeof(struct pi_req));
1668         ret = 0;
1669         break;
1670 
1671     default:
1672         ret = -EINVAL;
1673     }
1674     return ret;
1675 }
1676 
1677 /* Get the current statistics.  This may be called with the card open or
1678    closed. */
1679 static struct netstats *
1680  pi_get_stats(struct device *dev)
     /*  */
1681 {
1682     struct pi_local *lp = (struct pi_local *) dev->priv;
1683 
1684     return &lp->stats;
1685 }
1686 
1687 
1688 /*
1689  * Local variables:
1690  *  compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c skeleton.c"
1691  *  version-control: t
1692  *  kept-new-versions: 5
1693  *  tab-width: 4
1694  * End:
1695  */
/* */
root/drivers/net/pi2.c

DEFINITIONS
