root/drivers/net/de4x5.h

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   1 /*
   2     Copyright 1994 Digital Equipment Corporation.
   3 
   4     This software may be used and distributed according to  the terms of the
   5     GNU Public License, incorporated herein by reference.
   6 
   7     The author may    be  reached as davies@wanton.lkg.dec.com  or   Digital
   8     Equipment Corporation, 550 King Street, Littleton MA 01460.
   9 
  10     =========================================================================
  11 */
  12 
  13 /*
  14 ** DC21040 CSR<1..15> Register Address Map
  15 */
  16 #define DE4X5_BMR    iobase+(0x000 << lp->bus)  /* Bus Mode Register */
  17 #define DE4X5_TPD    iobase+(0x008 << lp->bus)  /* Transmit Poll Demand Reg */
  18 #define DE4X5_RPD    iobase+(0x010 << lp->bus)  /* Receive Poll Demand Reg */
  19 #define DE4X5_RRBA   iobase+(0x018 << lp->bus)  /* RX Ring Base Address Reg */
  20 #define DE4X5_TRBA   iobase+(0x020 << lp->bus)  /* TX Ring Base Address Reg */
  21 #define DE4X5_STS    iobase+(0x028 << lp->bus)  /* Status Register */
  22 #define DE4X5_OMR    iobase+(0x030 << lp->bus)  /* Operation Mode Register */
  23 #define DE4X5_IMR    iobase+(0x038 << lp->bus)  /* Interrupt Mask Register */
  24 #define DE4X5_MFC    iobase+(0x040 << lp->bus)  /* Missed Frame Counter */
  25 #define DE4X5_APROM  iobase+(0x048 << lp->bus)  /* Ethernet Address PROM */
  26 #define DE4X5_BROM   iobase+(0x048 << lp->bus)  /* Boot ROM Register */
  27 #define DE4X5_SROM   iobase+(0x048 << lp->bus)  /* Serial ROM Register */
  28 #define DE4X5_MII    iobase+(0x048 << lp->bus)  /* MII Interface Register */
  29 #define DE4X5_DDR    iobase+(0x050 << lp->bus)  /* Data Diagnostic Register */
  30 #define DE4X5_FDR    iobase+(0x058 << lp->bus)  /* Full Duplex Register */
  31 #define DE4X5_GPT    iobase+(0x058 << lp->bus)  /* General Purpose Timer Reg.*/
  32 #define DE4X5_GEP    iobase+(0x060 << lp->bus)  /* General Purpose Register */
  33 #define DE4X5_SISR   iobase+(0x060 << lp->bus)  /* SIA Status Register */
  34 #define DE4X5_SICR   iobase+(0x068 << lp->bus)  /* SIA Connectivity Register */
  35 #define DE4X5_STRR   iobase+(0x070 << lp->bus)  /* SIA TX/RX Register */
  36 #define DE4X5_SIGR   iobase+(0x078 << lp->bus)  /* SIA General Register */
  37 
  38 /*
  39 ** EISA Register Address Map
  40 */
  41 #define EISA_ID      iobase+0x0c80   /* EISA ID Registers */ 
  42 #define EISA_ID0     iobase+0x0c80   /* EISA ID Register 0 */ 
  43 #define EISA_ID1     iobase+0x0c81   /* EISA ID Register 1 */ 
  44 #define EISA_ID2     iobase+0x0c82   /* EISA ID Register 2 */ 
  45 #define EISA_ID3     iobase+0x0c83   /* EISA ID Register 3 */ 
  46 #define EISA_CR      iobase+0x0c84   /* EISA Control Register */
  47 #define EISA_REG0    iobase+0x0c88   /* EISA Configuration Register 0 */
  48 #define EISA_REG1    iobase+0x0c89   /* EISA Configuration Register 1 */
  49 #define EISA_REG2    iobase+0x0c8a   /* EISA Configuration Register 2 */
  50 #define EISA_REG3    iobase+0x0c8f   /* EISA Configuration Register 3 */
  51 #define EISA_APROM   iobase+0x0c90   /* Ethernet Address PROM */
  52 
  53 /*
  54 ** PCI/EISA Configuration Registers Address Map
  55 */
  56 #define PCI_CFID     iobase+0x0008   /* PCI Configuration ID Register */
  57 #define PCI_CFCS     iobase+0x000c   /* PCI Command/Status Register */
  58 #define PCI_CFRV     iobase+0x0018   /* PCI Revision Register */
  59 #define PCI_CFLT     iobase+0x001c   /* PCI Latency Timer Register */
  60 #define PCI_CBIO     iobase+0x0028   /* PCI Base I/O Register */
  61 #define PCI_CBMA     iobase+0x002c   /* PCI Base Memory Address Register */
  62 #define PCI_CBER     iobase+0x0030   /* PCI Expansion ROM Base Address Reg. */
  63 #define PCI_CFIT     iobase+0x003c   /* PCI Configuration Interrupt Register */
  64 #define PCI_CFDA     iobase+0x0040   /* PCI Driver Area Register */
  65 
  66 /*
  67 ** EISA Configuration Register 0 bit definitions
  68 */
  69 #define ER0_BSW       0x80           /* EISA Bus Slave Width, 1: 32 bits */
  70 #define ER0_BMW       0x40           /* EISA Bus Master Width, 1: 32 bits */
  71 #define ER0_EPT       0x20           /* EISA PREEMPT Time, 0: 23 BCLKs */
  72 #define ER0_ISTS      0x10           /* Interrupt Status (X) */
  73 #define ER0_LI        0x08           /* Latch Interrupts */
  74 #define ER0_INTL      0x06           /* INTerrupt Level */
  75 #define ER0_INTT      0x01           /* INTerrupt Type, 0: Level, 1: Edge */
  76 
  77 /*
  78 ** EISA Configuration Register 1 bit definitions
  79 */
  80 #define ER1_IAM       0xe0           /* ISA Address Mode */
  81 #define ER1_IAE       0x10           /* ISA Addressing Enable */
  82 #define ER1_UPIN      0x0f           /* User Pins */
  83 
  84 /*
  85 ** EISA Configuration Register 2 bit definitions
  86 */
  87 #define ER2_BRS       0xc0           /* Boot ROM Size */
  88 #define ER2_BRA       0x3c           /* Boot ROM Address <16:13> */
  89 
  90 /*
  91 ** EISA Configuration Register 3 bit definitions
  92 */
  93 #define ER3_BWE       0x40           /* Burst Write Enable */
  94 #define ER3_BRE       0x04           /* Burst Read Enable */
  95 #define ER3_LSR       0x02           /* Local Software Reset */
  96 
  97 /*
  98 ** PCI Configuration ID Register (PCI_CFID)
  99 */
 100 #define CFID_DID    0xff00           /* Device ID */
 101 #define CFID_VID    0x00ff           /* Vendor ID */
 102 #define DC21040_DID 0x0002           /* Unique Device ID # */
 103 #define DC21040_VID 0x1011           /* DC21040 Manufacturer */
 104 #define DC21041_DID 0x0014           /* Unique Device ID # */
 105 #define DC21041_VID 0x1011           /* DC21041 Manufacturer */
 106 #define DC21140_DID 0x0009           /* Unique Device ID # */
 107 #define DC21140_VID 0x1011           /* DC21140 Manufacturer */
 108 
 109 /*
 110 ** Chipset defines
 111 */
 112 #define DC21040     DC21040_DID
 113 #define DC21041     DC21041_DID
 114 #define DC21140     DC21140_DID
 115 
 116 #define is_DC21040 ((vendor == DC21040_VID) && (device == DC21040_DID))
 117 #define is_DC21041 ((vendor == DC21041_VID) && (device == DC21041_DID))
 118 #define is_DC21140 ((vendor == DC21140_VID) && (device == DC21140_DID))
 119 
 120 /*
 121 ** PCI Configuration Command/Status Register (PCI_CFCS)
 122 */
 123 #define CFCS_DPE    0x80000000       /* Detected Parity Error (S) */
 124 #define CFCS_SSE    0x40000000       /* Signal System Error   (S) */
 125 #define CFCS_RMA    0x20000000       /* Receive Master Abort  (S) */
 126 #define CFCS_RTA    0x10000000       /* Receive Target Abort  (S) */
 127 #define CFCS_DST    0x06000000       /* DEVSEL Timing         (S) */
 128 #define CFCS_DPR    0x01000000       /* Data Parity Report    (S) */
 129 #define CFCS_FBB    0x00800000       /* Fast Back-To-Back     (S) */
 130 #define CFCS_SLE    0x00000100       /* System Error Enable   (C) */
 131 #define CFCS_PER    0x00000040       /* Parity Error Response (C) */
 132 #define CFCS_MO     0x00000004       /* Master Operation      (C) */
 133 #define CFCS_MSA    0x00000002       /* Memory Space Access   (C) */
 134 #define CFCS_IOSA   0x00000001       /* I/O Space Access      (C) */
 135 
 136 /*
 137 ** PCI Configuration Revision Register (PCI_CFRV)
 138 */
 139 #define CFRV_BC     0xff000000       /* Base Class */
 140 #define CFRV_SC     0x00ff0000       /* Subclass */
 141 #define CFRV_SN     0x000000f0       /* Step Number */
 142 #define CFRV_RN     0x0000000f       /* Revision Number */
 143 #define BASE_CLASS  0x02000000       /* Indicates Network Controller */
 144 #define SUB_CLASS   0x00000000       /* Indicates Ethernet Controller */
 145 #define STEP_NUMBER 0x00000020       /* Increments for future chips */
 146 #define REV_NUMBER  0x00000003       /* 0x00, 0x01, 0x02, 0x03: Rev in Step */
 147 #define CFRV_MASK   0xffff0000       /* Register mask */
 148 
 149 /*
 150 ** PCI Configuration Latency Timer Register (PCI_CFLT)
 151 */
 152 #define CFLT_BC     0x0000ff00       /* Latency Timer bits */
 153 
 154 /*
 155 ** PCI Configuration Base I/O Address Register (PCI_CBIO)
 156 */
 157 #define CBIO_MASK   0xffffff80       /* Base I/O Address Mask */
 158 #define CBIO_IOSI   0x00000001       /* I/O Space Indicator (RO, value is 1) */
 159 
 160 /*
 161 ** PCI Configuration Expansion ROM Base Address Register (PCI_CBER)
 162 */
 163 #define CBER_MASK   0xfffffc00       /* Expansion ROM Base Address Mask */
 164 #define CBER_ROME   0x00000001       /* ROM Enable */
 165 
 166 /*
 167 ** PCI Configuration Driver Area Register (PCI_CFDA)
 168 */
 169 #define CFDA_PSM    0x80000000       /* Power Saving Mode */
 170 
 171 /*
 172 ** DC21040 Bus Mode Register (DE4X5_BMR)
 173 */
 174 #define BMR_DBO    0x00100000       /* Descriptor Byte Ordering (Endian) */
 175 #define BMR_TAP    0x000e0000       /* Transmit Automatic Polling */
 176 #define BMR_DAS    0x00010000       /* Diagnostic Address Space */
 177 #define BMR_CAL    0x0000c000       /* Cache Alignment */
 178 #define BMR_PBL    0x00003f00       /* Programmable Burst Length */
 179 #define BMR_BLE    0x00000080       /* Big/Little Endian */
 180 #define BMR_DSL    0x0000007c       /* Descriptor Skip Length */
 181 #define BMR_BAR    0x00000002       /* Bus ARbitration */
 182 #define BMR_SWR    0x00000001       /* Software Reset */
 183 
 184 #define TAP_NOPOLL 0x00000000       /* No automatic polling */
 185 #define TAP_200US  0x00020000       /* TX automatic polling every 200us */
 186 #define TAP_800US  0x00040000       /* TX automatic polling every 800us */
 187 #define TAP_1_6MS  0x00060000       /* TX automatic polling every 1.6ms */
 188 #define TAP_12_8US 0x00080000       /* TX automatic polling every 12.8us */
 189 #define TAP_25_6US 0x000a0000       /* TX automatic polling every 25.6us */
 190 #define TAP_51_2US 0x000c0000       /* TX automatic polling every 51.2us */
 191 #define TAP_102_4US 0x000e0000      /* TX automatic polling every 102.4us */
 192 
 193 #define CAL_NOUSE  0x00000000       /* Not used */
 194 #define CAL_8LONG  0x00004000       /* 8-longword alignment */
 195 #define CAL_16LONG 0x00008000       /* 16-longword alignment */
 196 #define CAL_32LONG 0x0000c000       /* 32-longword alignment */
 197 
 198 #define PBL_0      0x00000000       /*  DMA burst length = amount in RX FIFO */
 199 #define PBL_1      0x00000100       /*  1 longword  DMA burst length */
 200 #define PBL_2      0x00000200       /*  2 longwords DMA burst length */
 201 #define PBL_4      0x00000400       /*  4 longwords DMA burst length */
 202 #define PBL_8      0x00000800       /*  8 longwords DMA burst length */
 203 #define PBL_16     0x00001000       /* 16 longwords DMA burst length */
 204 #define PBL_32     0x00002000       /* 32 longwords DMA burst length */
 205 
 206 #define DSL_0      0x00000000       /*  0 longword  / descriptor */
 207 #define DSL_1      0x00000004       /*  1 longword  / descriptor */
 208 #define DSL_2      0x00000008       /*  2 longwords / descriptor */
 209 #define DSL_4      0x00000010       /*  4 longwords / descriptor */
 210 #define DSL_8      0x00000020       /*  8 longwords / descriptor */
 211 #define DSL_16     0x00000040       /* 16 longwords / descriptor */
 212 #define DSL_32     0x00000080       /* 32 longwords / descriptor */
 213 
 214 /*
 215 ** DC21040 Transmit Poll Demand Register (DE4X5_TPD)
 216 */
 217 #define TPD        0x00000001       /* Transmit Poll Demand */
 218 
 219 /*
 220 ** DC21040 Receive Poll Demand Register (DE4X5_RPD)
 221 */
 222 #define RPD        0x00000001       /* Receive Poll Demand */
 223 
 224 /*
 225 ** DC21040 Receive Ring Base Address Register (DE4X5_RRBA)
 226 */
 227 #define RRBA       0xfffffffc       /* RX Descriptor List Start Address */
 228 
 229 /*
 230 ** DC21040 Transmit Ring Base Address Register (DE4X5_TRBA)
 231 */
 232 #define TRBA       0xfffffffc       /* TX Descriptor List Start Address */
 233 
 234 /*
 235 ** DC21040 Status Register (DE4X5_STS)
 236 */
 237 #define STS_BE     0x03800000       /* Bus Error Bits */
 238 #define STS_TS     0x00700000       /* Transmit Process State */
 239 #define STS_RS     0x000e0000       /* Receive Process State */
 240 #define STS_NIS    0x00010000       /* Normal Interrupt Summary */
 241 #define STS_AIS    0x00008000       /* Abnormal Interrupt Summary */
 242 #define STS_ER     0x00004000       /* Early Receive */
 243 #define STS_SE     0x00002000       /* System Error */
 244 #define STS_LNF    0x00001000       /* Link Fail */
 245 #define STS_FD     0x00000800       /* Full-Duplex Short Frame Received */
 246 #define STS_TM     0x00000800       /* Timer Expired (DC21041) */
 247 #define STS_AT     0x00000400       /* AUI/TP Pin */
 248 #define STS_RWT    0x00000200       /* Receive Watchdog Time-Out */
 249 #define STS_RPS    0x00000100       /* Receive Process Stopped */
 250 #define STS_RU     0x00000080       /* Receive Buffer Unavailable */
 251 #define STS_RI     0x00000040       /* Receive Interrupt */
 252 #define STS_UNF    0x00000020       /* Transmit Underflow */
 253 #define STS_LNP    0x00000010       /* Link Pass */
 254 #define STS_TJT    0x00000008       /* Transmit Jabber Time-Out */
 255 #define STS_TU     0x00000004       /* Transmit Buffer Unavailable */
 256 #define STS_TPS    0x00000002       /* Transmit Process Stopped */
 257 #define STS_TI     0x00000001       /* Transmit Interrupt */
 258 
 259 #define EB_PAR     0x00000000       /* Parity Error */
 260 #define EB_MA      0x00800000       /* Master Abort */
 261 #define EB_TA      0x01000000       /* Target Abort */
 262 #define EB_RES0    0x01800000       /* Reserved */
 263 #define EB_RES1    0x02000000       /* Reserved */
 264 
 265 #define TS_STOP    0x00000000       /* Stopped */
 266 #define TS_FTD     0x00100000       /* Fetch Transmit Descriptor */
 267 #define TS_WEOT    0x00200000       /* Wait for End Of Transmission */
 268 #define TS_QDAT    0x00300000       /* Queue skb data into TX FIFO */
 269 #define TS_RES     0x00400000       /* Reserved */
 270 #define TS_SPKT    0x00500000       /* Setup Packet */
 271 #define TS_SUSP    0x00600000       /* Suspended */
 272 #define TS_CLTD    0x00700000       /* Close Transmit Descriptor */
 273 
 274 #define RS_STOP    0x00000000       /* Stopped */
 275 #define RS_FRD     0x00020000       /* Fetch Receive Descriptor */
 276 #define RS_CEOR    0x00040000       /* Check for End of Receive Packet */
 277 #define RS_WFRP    0x00060000       /* Wait for Receive Packet */
 278 #define RS_SUSP    0x00080000       /* Suspended */
 279 #define RS_CLRD    0x000a0000       /* Close Receive Descriptor */
 280 #define RS_FLUSH   0x000c0000       /* Flush RX FIFO */
 281 #define RS_QRFS    0x000e0000       /* Queue RX FIFO into RX Skb */
 282 
 283 #define INT_CANCEL 0x0001ffff       /* For zeroing all interrupt sources */
 284 
 285 /*
 286 ** DC21040 Operation Mode Register (DE4X5_OMR)
 287 */
 288 #define OMR_SDP    0x02000000       /* SD Polarity - MUST BE ASSERTED */
 289 #define OMR_SCR    0x01000000       /* Scrambler Mode */
 290 #define OMR_PCS    0x00800000       /* PCS Function */
 291 #define OMR_TTM    0x00400000       /* Transmit Threshold Mode */
 292 #define OMR_SF     0x00200000       /* Store and Forward */
 293 #define OMR_HBD    0x00080000       /* HeartBeat Disable */
 294 #define OMR_PS     0x00040000       /* Port Select */
 295 #define OMR_CA     0x00020000       /* Capture Effect Enable */
 296 #define OMR_BP     0x00010000       /* Back Pressure */
 297 #define OMR_TR     0x0000c000       /* Threshold Control Bits */
 298 #define OMR_ST     0x00002000       /* Start/Stop Transmission Command */
 299 #define OMR_FC     0x00001000       /* Force Collision Mode */
 300 #define OMR_OM     0x00000c00       /* Operating Mode */
 301 #define OMR_FD     0x00000200       /* Full Duplex Mode */
 302 #define OMR_FKD    0x00000100       /* Flaky Oscillator Disable */
 303 #define OMR_PM     0x00000080       /* Pass All Multicast */
 304 #define OMR_PR     0x00000040       /* Promiscuous Mode */
 305 #define OMR_SB     0x00000020       /* Start/Stop Backoff Counter */
 306 #define OMR_IF     0x00000010       /* Inverse Filtering */
 307 #define OMR_PB     0x00000008       /* Pass Bad Frames */
 308 #define OMR_HO     0x00000004       /* Hash Only Filtering Mode */
 309 #define OMR_SR     0x00000002       /* Start/Stop Receive */
 310 #define OMR_HP     0x00000001       /* Hash/Perfect Receive Filtering Mode */
 311 
 312 #define TR_72      0x00000000       /* Threshold set to 72 bytes */
 313 #define TR_96      0x00004000       /* Threshold set to 96 bytes */
 314 #define TR_128     0x00008000       /* Threshold set to 128 bytes */
 315 #define TR_160     0x0000c000       /* Threshold set to 160 bytes */
 316 
 317 /*
 318 ** DC21040 Interrupt Mask Register (DE4X5_IMR)
 319 */
 320 #define IMR_NIM    0x00010000       /* Normal Interrupt Summary Mask */
 321 #define IMR_AIM    0x00008000       /* Abnormal Interrupt Summary Mask */
 322 #define IMR_ERM    0x00004000       /* Early Receive Mask */
 323 #define IMR_SEM    0x00002000       /* System Error Mask */
 324 #define IMR_LFM    0x00001000       /* Link Fail Mask */
 325 #define IMR_FDM    0x00000800       /* Full-Duplex (Short Frame) Mask */
 326 #define IMR_TMM    0x00000800       /* Timer Expired Mask (DC21041) */
 327 #define IMR_ATM    0x00000400       /* AUI/TP Switch Mask */
 328 #define IMR_RWM    0x00000200       /* Receive Watchdog Time-Out Mask */
 329 #define IMR_RSM    0x00000100       /* Receive Stopped Mask */
 330 #define IMR_RUM    0x00000080       /* Receive Buffer Unavailable Mask */
 331 #define IMR_RIM    0x00000040       /* Receive Interrupt Mask */
 332 #define IMR_UNM    0x00000020       /* Underflow Interrupt Mask */
 333 #define IMR_LPM    0x00000010       /* Link Pass */
 334 #define IMR_TJM    0x00000008       /* Transmit Time-Out Jabber Mask */
 335 #define IMR_TUM    0x00000004       /* Transmit Buffer Unavailable Mask */
 336 #define IMR_TSM    0x00000002       /* Transmission Stopped Mask */
 337 #define IMR_TIM    0x00000001       /* Transmit Interrupt Mask */
 338 
 339 /*
 340 ** DC21040 Missed Frame Counter (DE4X5_MFC)
 341 */
 342 #define MFC_OVFL   0x00010000       /* Counter Overflow Bit */
 343 #define MFC_CNTR   0x0000ffff       /* Counter Bits */
 344 
 345 /*
 346 ** DC21040 Ethernet Address PROM (DE4X5_APROM)
 347 */
 348 #define APROM_DN   0x80000000       /* Data Not Valid */
 349 #define APROM_DT   0x000000ff       /* Address Byte */
 350 
 351 /*
 352 ** DC21041 Boot/Ethernet Address ROM (DE4X5_BROM)
 353 */
 354 #define BROM_MODE 0x00008000       /* MODE_1: 0,  MODE_0: 1  (read only) */
 355 #define BROM_RD   0x00004000       /* Read from Boot ROM */
 356 #define BROM_WR   0x00002000       /* Write to Boot ROM */
 357 #define BROM_BR   0x00001000       /* Select Boot ROM when set */
 358 #define BROM_SR   0x00000800       /* Select Serial ROM when set */
 359 #define BROM_REG  0x00000400       /* External Register Select */
 360 #define BROM_DT   0x000000ff       /* Data Byte */
 361 
 362 /*
 363 ** DC21041 Serial/Ethernet Address ROM (DE4X5_SROM, DE4X5_MII)
 364 */
 365 #define MII_MDI   0x00080000       /* MII Management Data In */
 366 #define MII_MDO   0x00060000       /* MII Management Mode/Data Out */
 367 #define MII_MRD   0x00040000       /* MII Management Define Read Mode */
 368 #define MII_MWR   0x00000000       /* MII Management Define Write Mode */
 369 #define MII_MDT   0x00020000       /* MII Management Data Out */
 370 #define MII_MDC   0x00010000       /* MII Management Clock */
 371 #define MII_RD    0x00004000       /* Read from MII */
 372 #define MII_WR    0x00002000       /* Write to MII */
 373 #define MII_SEL   0x00000800       /* Select MII when RESET */
 374 
 375 #define SROM_MODE 0x00008000       /* MODE_1: 0,  MODE_0: 1  (read only) */
 376 #define SROM_RD   0x00004000       /* Read from Boot ROM */
 377 #define SROM_WR   0x00002000       /* Write to Boot ROM */
 378 #define SROM_BR   0x00001000       /* Select Boot ROM when set */
 379 #define SROM_SR   0x00000800       /* Select Serial ROM when set */
 380 #define SROM_REG  0x00000400       /* External Register Select */
 381 #define SROM_DT   0x000000ff       /* Data Byte */
 382 
 383 #define DT_OUT    0x00000008       /* Serial Data Out */
 384 #define DT_IN     0x00000004       /* Serial Data In */
 385 #define DT_CLK    0x00000002       /* Serial ROM Clock */
 386 #define DT_CS     0x00000001       /* Serial ROM Chip Select */
 387 
 388 #define MII_PREAMBLE 0xffffffff    /* MII Management Preamble */
 389 #define MII_TEST     0xaaaaaaaa    /* MII Test Signal */
 390 #define MII_STRD     0x06          /* Start of Frame+Op Code: use low nibble */
 391 #define MII_STWR     0x0a          /* Start of Frame+Op Code: use low nibble */
 392 
 393 #define MII_CR       0x00          /* MII Management Control Register */
 394 #define MII_SR       0x01          /* MII Management Status Register */
 395 #define MII_ID0      0x02          /* PHY Identifier Register 0 */
 396 #define MII_ID1      0x03          /* PHY Identifier Register 1 */
 397 #define MII_ANA      0x04          /* Auto Negotiation Advertisement */
 398 #define MII_ANLPA    0x05          /* Auto Negotiation Link Partner Ability */
 399 #define MII_ANE      0x06          /* Auto Negotiation Expansion */
 400 #define MII_ANP      0x07          /* Auto Negotiation Next Page TX */
 401 
 402 #define DE4X5_MAX_MII 32           /* Maximum address of MII PHY devices */
 403 
 404 /*
 405 ** MII Management Control Register
 406 */
 407 #define MII_CR_RST  0x8000         /* RESET the PHY chip */
 408 #define MII_CR_LPBK 0x4000         /* Loopback enable */
 409 #define MII_CR_SPD  0x2000         /* 0: 10Mb/s; 1: 100Mb/s */
 410 #define MII_CR_10   0x0000         /* Set 10Mb/s */
 411 #define MII_CR_100  0x2000         /* Set 100Mb/s */
 412 #define MII_CR_ASSE 0x1000         /* Auto Speed Select Enable */
 413 #define MII_CR_PD   0x0800         /* Power Down */
 414 #define MII_CR_ISOL 0x0400         /* Isolate Mode */
 415 #define MII_CR_RAN  0x0200         /* Restart Auto Negotiation */
 416 #define MII_CR_FDM  0x0100         /* Full Duplex Mode */
 417 #define MII_CR_CTE  0x0080         /* Collision Test Enable */
 418 
 419 /*
 420 ** MII Management Status Register
 421 */
 422 #define MII_SR_T4C  0x8000         /* 100BASE-T4 capable */
 423 #define MII_SR_TXFD 0x4000         /* 100BASE-TX Full Duplex capable */
 424 #define MII_SR_TXHD 0x2000         /* 100BASE-TX Half Duplex capable */
 425 #define MII_SR_TFD  0x1000         /* 10BASE-T Full Duplex capable */
 426 #define MII_SR_THD  0x0800         /* 10BASE-T Half Duplex capable */
 427 #define MII_SR_ASSC 0x0020         /* Auto Speed Selection Complete*/
 428 #define MII_SR_RFD  0x0010         /* Remote Fault Detected */
 429 #define MII_SR_ANC  0x0008         /* Auto Negotiation capable */
 430 #define MII_SR_LKS  0x0004         /* Link Status */
 431 #define MII_SR_JABD 0x0002         /* Jabber Detect */
 432 #define MII_SR_XC   0x0001         /* Extended Capabilities */
 433 
 434 /*
 435 ** MII Management Auto Negotiation Advertisement Register
 436 */
 437 #define MII_ANA_TAF  0x03e0        /* Technology Ability Field */
 438 #define MII_ANA_T4AM 0x0400        /* T4 Technology Ability Mask */
 439 #define MII_ANA_TXAM 0x0180        /* TX Technology Ability Mask */
 440 #define MII_ANA_FDAM 0x0140        /* Full Duplex Technology Ability Mask */
 441 #define MII_ANA_HDAM 0x02a0        /* Half Duplex Technology Ability Mask */
 442 #define MII_ANA_100M 0x0380        /* 100Mb Technology Ability Mask */
 443 #define MII_ANA_10M  0x0060        /* 10Mb Technology Ability Mask */
 444 #define MII_ANA_CSMA 0x0001        /* CSMA-CD Capable */
 445 
 446 /*
 447 ** MII Management Auto Negotiation Remote End Register
 448 */
 449 #define MII_ANLPA_NP   0x8000      /* Next Page (Enable) */
 450 #define MII_ANLPA_ACK  0x4000      /* Remote Acknowledge */
 451 #define MII_ANLPA_RF   0x2000      /* Remote Fault */
 452 #define MII_ANLPA_TAF  0x03e0      /* Technology Ability Field */
 453 #define MII_ANLPA_T4AM 0x0400      /* T4 Technology Ability Mask */
 454 #define MII_ANLPA_TXAM 0x0180      /* TX Technology Ability Mask */
 455 #define MII_ANLPA_FDAM 0x0140      /* Full Duplex Technology Ability Mask */
 456 #define MII_ANLPA_HDAM 0x02a0      /* Half Duplex Technology Ability Mask */
 457 #define MII_ANLPA_100M 0x0380      /* 100Mb Technology Ability Mask */
 458 #define MII_ANLPA_10M  0x0060      /* 10Mb Technology Ability Mask */
 459 #define MII_ANLPA_CSMA 0x0001      /* CSMA-CD Capable */
 460 
 461 /*
 462 ** SROM Media Definitions (ABG SROM Section)
 463 */
 464 #define MEDIA_NWAY     0x0080      /* Nway (Auto Negotiation) on PHY */
 465 #define MEDIA_MII      0x0040      /* MII Present on the adapter */
 466 #define MEDIA_FIBRE    0x0008      /* Fibre Media present */
 467 #define MEDIA_AUI      0x0004      /* AUI Media present */
 468 #define MEDIA_TP       0x0002      /* TP Media present */
 469 #define MEDIA_BNC      0x0001      /* BNC Media present */
 470 
 471 /*
 472 ** DC21040 Full Duplex Register (DE4X5_FDR)
 473 */
 474 #define FDR_FDACV  0x0000ffff      /* Full Duplex Auto Configuration Value */
 475 
 476 /*
 477 ** DC21041 General Purpose Timer Register (DE4X5_GPT)
 478 */
 479 #define GPT_CON  0x00010000        /* One shot: 0,  Continuous: 1 */
 480 #define GPT_VAL  0x0000ffff        /* Timer Value */
 481 
 482 /*
 483 ** DC21140 General Purpose Register (DE4X5_GEP) (hardware dependent bits)
 484 */
 485 /* Valid ONLY for DE500 hardware */
 486 #define GEP_LNP  0x00000080        /* Link Pass               (input) */
 487 #define GEP_SLNK 0x00000040        /* SYM LINK                (input) */
 488 #define GEP_SDET 0x00000020        /* Signal Detect           (input) */
 489 #define GEP_HRST 0x00000010        /* Hard RESET (to PHY)     (output) */
 490 #define GEP_FDXD 0x00000008        /* Full Duplex Disable     (output) */
 491 #define GEP_PHYL 0x00000004        /* PHY Loopback            (output) */
 492 #define GEP_FLED 0x00000002        /* Force Activity LED on   (output) */
 493 #define GEP_MODE 0x00000001        /* 0: 10Mb/s,  1: 100Mb/s           */
 494 #define GEP_INIT 0x0000011f        /* Setup inputs (0) and outputs (1) */
 495 
 496 
 497 /*
 498 ** DC21040 SIA Status Register (DE4X5_SISR)
 499 */
 500 #define SISR_LPC   0xffff0000      /* Link Partner's Code Word */
 501 #define SISR_LPN   0x00008000      /* Link Partner Negotiable */
 502 #define SISR_ANS   0x00007000      /* Auto Negotiation Arbitration State */
 503 #define SISR_NSN   0x00000800      /* Non Stable NLPs Detected */
 504 #define SISR_ANR_FDS 0x00000400    /* Auto Negotiate Restart/Full Duplex Sel.*/
 505 #define SISR_NRA   0x00000200      /* Non Selected Port Receive Activity */
 506 #define SISR_SRA   0x00000100      /* Selected Port Receive Activity */
 507 #define SISR_DAO   0x00000080      /* PLL All One */
 508 #define SISR_DAZ   0x00000040      /* PLL All Zero */
 509 #define SISR_DSP   0x00000020      /* PLL Self-Test Pass */
 510 #define SISR_DSD   0x00000010      /* PLL Self-Test Done */
 511 #define SISR_APS   0x00000008      /* Auto Polarity State */
 512 #define SISR_LKF   0x00000004      /* Link Fail Status */
 513 #define SISR_NCR   0x00000002      /* Network Connection Error */
 514 #define SISR_PAUI  0x00000001      /* AUI_TP Indication */
 515 #define SIA_RESET  0x00000000      /* SIA Reset */
 516 
 517 #define ANS_NDIS   0x00000000      /* Nway disable */
 518 #define ANS_TDIS   0x00001000      /* Transmit Disable */
 519 #define ANS_ADET   0x00002000      /* Ability Detect */
 520 #define ANS_ACK    0x00003000      /* Acknowledge */
 521 #define ANS_CACK   0x00004000      /* Complete Acknowledge */
 522 #define ANS_NWOK   0x00005000      /* Nway OK - FLP Link Good */
 523 #define ANS_LCHK   0x00006000      /* Link Check */
 524 
 525 /*
 526 ** DC21040 SIA Connectivity Register (DE4X5_SICR)
 527 */
 528 #define SICR_SDM   0xffff0000       /* SIA Diagnostics Mode */
 529 #define SICR_OE57  0x00008000       /* Output Enable 5 6 7 */
 530 #define SICR_OE24  0x00004000       /* Output Enable 2 4 */
 531 #define SICR_OE13  0x00002000       /* Output Enable 1 3 */
 532 #define SICR_IE    0x00001000       /* Input Enable */
 533 #define SICR_EXT   0x00000000       /* SIA MUX Select External SIA Mode */
 534 #define SICR_D_SIA 0x00000400       /* SIA MUX Select Diagnostics - SIA Sigs */
 535 #define SICR_DPLL  0x00000800       /* SIA MUX Select Diagnostics - DPLL Sigs*/
 536 #define SICR_APLL  0x00000a00       /* SIA MUX Select Diagnostics - DPLL Sigs*/
 537 #define SICR_D_RxM 0x00000c00       /* SIA MUX Select Diagnostics - RxM Sigs */
 538 #define SICR_M_RxM 0x00000d00       /* SIA MUX Select Diagnostics - RxM Sigs */
 539 #define SICR_LNKT  0x00000e00       /* SIA MUX Select Diagnostics - Link Test*/
 540 #define SICR_SEL   0x00000f00       /* SIA MUX Select AUI or TP with LEDs */
 541 #define SICR_ASE   0x00000080       /* APLL Start Enable*/
 542 #define SICR_SIM   0x00000040       /* Serial Interface Input Multiplexer */
 543 #define SICR_ENI   0x00000020       /* Encoder Input Multiplexer */
 544 #define SICR_EDP   0x00000010       /* SIA PLL External Input Enable */
 545 #define SICR_AUI   0x00000008       /* 10Base-T or AUI */
 546 #define SICR_CAC   0x00000004       /* CSR Auto Configuration */
 547 #define SICR_PS    0x00000002       /* Pin AUI/TP Selection */
 548 #define SICR_SRL   0x00000001       /* SIA Reset */
 549 #define SICR_RESET 0xffff0000       /* Reset value for SICR */
 550 
 551 /*
 552 ** DC21040 SIA Transmit and Receive Register (DE4X5_STRR)
 553 */
 554 #define STRR_TAS   0x00008000       /* 10Base-T/AUI Autosensing Enable */
 555 #define STRR_SPP   0x00004000       /* Set Polarity Plus */
 556 #define STRR_APE   0x00002000       /* Auto Polarity Enable */
 557 #define STRR_LTE   0x00001000       /* Link Test Enable */
 558 #define STRR_SQE   0x00000800       /* Signal Quality Enable */
 559 #define STRR_CLD   0x00000400       /* Collision Detect Enable */
 560 #define STRR_CSQ   0x00000200       /* Collision Squelch Enable */
 561 #define STRR_RSQ   0x00000100       /* Receive Squelch Enable */
 562 #define STRR_ANE   0x00000080       /* Auto Negotiate Enable */
 563 #define STRR_HDE   0x00000040       /* Half Duplex Enable */
 564 #define STRR_CPEN  0x00000030       /* Compensation Enable */
 565 #define STRR_LSE   0x00000008       /* Link Pulse Send Enable */
 566 #define STRR_DREN  0x00000004       /* Driver Enable */
 567 #define STRR_LBK   0x00000002       /* Loopback Enable */
 568 #define STRR_ECEN  0x00000001       /* Encoder Enable */
 569 #define STRR_RESET 0xffffffff       /* Reset value for STRR */
 570 
 571 /*
 572 ** DC21040 SIA General Register (DE4X5_SIGR)
 573 */
 574 #define SIGR_LV2   0x00008000       /* General Purpose LED2 value */
 575 #define SIGR_LE2   0x00004000       /* General Purpose LED2 enable */
 576 #define SIGR_FRL   0x00002000       /* Force Receiver Low */
 577 #define SIGR_DPST  0x00001000       /* PLL Self Test Start */
 578 #define SIGR_LSD   0x00000800       /* LED Stretch Disable */
 579 #define SIGR_FLF   0x00000400       /* Force Link Fail */
 580 #define SIGR_FUSQ  0x00000200       /* Force Unsquelch */
 581 #define SIGR_TSCK  0x00000100       /* Test Clock */
 582 #define SIGR_LV1   0x00000080       /* General Purpose LED1 value */
 583 #define SIGR_LE1   0x00000040       /* General Purpose LED1 enable */
 584 #define SIGR_RWR   0x00000020       /* Receive Watchdog Release */
 585 #define SIGR_RWD   0x00000010       /* Receive Watchdog Disable */
 586 #define SIGR_ABM   0x00000008       /* BNC: 0,  AUI:1 */
 587 #define SIGR_JCK   0x00000004       /* Jabber Clock */
 588 #define SIGR_HUJ   0x00000002       /* Host Unjab */
 589 #define SIGR_JBD   0x00000001       /* Jabber Disable */
 590 #define SIGR_RESET 0xffff0000       /* Reset value for SIGR */
 591 
 592 /*
 593 ** Receive Descriptor Bit Summary
 594 */
 595 #define R_OWN      0x80000000       /* Own Bit */
 596 #define RD_FL      0x7fff0000       /* Frame Length */
 597 #define RD_ES      0x00008000       /* Error Summary */
 598 #define RD_LE      0x00004000       /* Length Error */
 599 #define RD_DT      0x00003000       /* Data Type */
 600 #define RD_RF      0x00000800       /* Runt Frame */
 601 #define RD_MF      0x00000400       /* Multicast Frame */
 602 #define RD_FS      0x00000200       /* First Descriptor */
 603 #define RD_LS      0x00000100       /* Last Descriptor */
 604 #define RD_TL      0x00000080       /* Frame Too Long */
 605 #define RD_CS      0x00000040       /* Collision Seen */
 606 #define RD_FT      0x00000020       /* Frame Type */
 607 #define RD_RJ      0x00000010       /* Receive Watchdog */
 608 #define RD_DB      0x00000004       /* Dribbling Bit */
 609 #define RD_CE      0x00000002       /* CRC Error */
 610 #define RD_OF      0x00000001       /* Overflow */
 611 
 612 #define RD_RER     0x02000000       /* Receive End Of Ring */
 613 #define RD_RCH     0x01000000       /* Second Address Chained */
 614 #define RD_RBS2    0x003ff800       /* Buffer 2 Size */
 615 #define RD_RBS1    0x000007ff       /* Buffer 1 Size */
 616 
 617 /*
 618 ** Transmit Descriptor Bit Summary
 619 */
 620 #define T_OWN      0x80000000       /* Own Bit */
 621 #define TD_ES      0x00008000       /* Error Summary */
 622 #define TD_TO      0x00004000       /* Transmit Jabber Time-Out */
 623 #define TD_LO      0x00000800       /* Loss Of Carrier */
 624 #define TD_NC      0x00000400       /* No Carrier */
 625 #define TD_LC      0x00000200       /* Late Collision */
 626 #define TD_EC      0x00000100       /* Excessive Collisions */
 627 #define TD_HF      0x00000080       /* Heartbeat Fail */
 628 #define TD_CC      0x00000078       /* Collision Counter */
 629 #define TD_LF      0x00000004       /* Link Fail */
 630 #define TD_UF      0x00000002       /* Underflow Error */
 631 #define TD_DE      0x00000001       /* Deferred */
 632 
 633 #define TD_IC      0x80000000       /* Interrupt On Completion */
 634 #define TD_LS      0x40000000       /* Last Segment */
 635 #define TD_FS      0x20000000       /* First Segment */
 636 #define TD_FT1     0x10000000       /* Filtering Type */
 637 #define TD_SET     0x08000000       /* Setup Packet */
 638 #define TD_AC      0x04000000       /* Add CRC Disable */
 639 #define TD_TER     0x02000000       /* Transmit End Of Ring */
 640 #define TD_TCH     0x01000000       /* Second Address Chained */
 641 #define TD_DPD     0x00800000       /* Disabled Padding */
 642 #define TD_FT0     0x00400000       /* Filtering Type */
 643 #define TD_RBS2    0x003ff800       /* Buffer 2 Size */
 644 #define TD_RBS1    0x000007ff       /* Buffer 1 Size */
 645 
 646 #define PERFECT_F  0x00000000
 647 #define HASH_F     TD_FT0
 648 #define INVERSE_F  TD_FT1
 649 #define HASH_O_F   TD_FT1| TD_F0
 650 
 651 /*
 652 ** Media / mode state machine definitions
 653 */
 654 #define NC              0x0000     /* No Connection */
 655 #define TP              0x0001     /* 10Base-T */
 656 #define TP_NW           0x0002     /* 10Base-T with Nway */
 657 #define BNC             0x0004     /* Thinwire */
 658 #define AUI             0x0008     /* Thickwire */
 659 #define BNC_AUI         0x0010     /* BNC/AUI on DC21040 indistinguishable */
 660 #define ANS             0x0020     /* Intermediate AutoNegotiation State */
 661 #define ANS_1           0x0021     /* Intermediate AutoNegotiation State */
 662 
 663 #define _10Mb           0x0040     /* 10Mb/s Ethernet */
 664 #define _100Mb          0x0080     /* 100Mb/s Ethernet */
 665 #define SPD_DET         0x0100     /* Parallel speed detection */
 666 #define INIT            0x0200     /* Initial state */
 667 #define EXT_SIA         0x0400     /* External SIA for motherboard chip */
 668 #define ANS_SUSPECT     0x0802     /* Suspect the ANS (TP) port is down */
 669 #define TP_SUSPECT      0x0803     /* Suspect the TP port is down */
 670 #define BNC_AUI_SUSPECT 0x0804     /* Suspect the BNC or AUI port is down */
 671 #define EXT_SIA_SUSPECT 0x0805     /* Suspect the EXT SIA port is down */
 672 #define BNC_SUSPECT     0x0806     /* Suspect the BNC port is down */
 673 #define AUI_SUSPECT     0x0807     /* Suspect the AUI port is down */
 674 #define _10Mb_SUSPECT   0x0808     /* Suspect 10Mb/s is down */
 675 #define _100Mb_SUSPECT  0x0809     /* Suspect 100Mb/s is down */
 676 #define LINK_RESET      0x080a     /* Reset the PHY and re-init auto sense */
 677 
 678 #define AUTO            0x4000     /* Auto sense the media or speed */
 679 #define TIMER_CB        0x80000000 /* Timer callback detection */
 680 
 681 /*
 682 ** Miscellaneous
 683 */
 684 #define PCI  0
 685 #define EISA 1
 686 
 687 #define HASH_TABLE_LEN   512       /* Bits */
 688 #define HASH_BITS        0x01ff    /* 9 LS bits */
 689 
 690 #define SETUP_FRAME_LEN  192       /* Bytes */
 691 #define IMPERF_PA_OFFSET 156       /* Bytes */
 692 
 693 #define POLL_DEMAND          1
 694 
 695 #define LOST_MEDIA_THRESHOLD 3
 696 #define LOST_MEDIA           (lp->lostMedia > LOST_MEDIA_THRESHOLD)
 697 
 698 #define MASK_INTERRUPTS      1
 699 #define UNMASK_INTERRUPTS    0
 700 
 701 #define DE4X5_STRLEN         8
 702 
 703 #define DE4X5_INIT           0     /* Initialisation time */
 704 #define DE4X5_RUN            1     /* Run time */
 705 
 706 #define DE4X5_SAVE_STATE     0
 707 #define DE4X5_RESTORE_STATE  1
 708 
 709 /*
 710 ** Address Filtering Modes
 711 */
 712 #define PERFECT              0     /* 16 perfect physical addresses */
 713 #define HASH_PERF            1     /* 1 perfect, 512 multicast addresses */
 714 #define PERFECT_REJ          2     /* Reject 16 perfect physical addresses */
 715 #define ALL_HASH             3     /* Hashes all physical & multicast addrs */
 716 
 717 #define ALL                  0     /* Clear out all the setup frame */
 718 #define PHYS_ADDR_ONLY       1     /* Update the physical address only */
 719 
 720 /*
 721 ** Booleans
 722 */
 723 #define NO                   0
 724 #define FALSE                0
 725 #define CLOSED               0
 726 
 727 #define YES                  ~0
 728 #define TRUE                 ~0
 729 #define OPEN                 ~0
 730 
 731 /*
 732 ** IEEE OUIs for various PHY vendor/chip combos - Reg 2 values only. Since
 733 ** the vendors seem split 50-50 on how to calculate the OUI register values
 734 ** anyway, just reading Reg2 seems reasonable for now [see de4x5_get_oui()].
 735 */
 736 #define NATIONAL_TX 0x2000
 737 #define BROADCOM_T4 0x03e0
 738 #define SEEQ_T4     0x0016
 739 #define CYPRESS_T4  0x0014
 740 
 741 /*
 742 ** Speed Selection stuff
 743 */
 744 #define SET_10Mb {\
 745   if (lp->phy[lp->active].id) {\
 746     mii_wr(MII_CR_10|MII_CR_ASSE,MII_CR,lp->phy[lp->active].addr,DE4X5_MII);\
 747     omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR);\
 748     omr |= (de4x5_full_duplex ? OMR_FD : 0) | OMR_TTM;\
 749     outl(omr, DE4X5_OMR);\
 750     outl(0, DE4X5_GEP);\
 751   } else {\
 752     omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));\
 753     omr |= (de4x5_full_duplex ? OMR_FD : 0);\
 754     outl(omr | OMR_TTM, DE4X5_OMR);\
 755     outl((de4x5_full_duplex ? 0 : GEP_FDXD), DE4X5_GEP);\
 756   }\
 757 }
 758 
 759 #define SET_100Mb {\
 760   if (lp->phy[lp->active].id) {\
 761     mii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
 762     omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR);\
 763     sr = mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);\
 764     if (!(sr & MII_ANA_T4AM) && de4x5_full_duplex) omr |= OMR_FD;\
 765     outl(omr, DE4X5_OMR);\
 766     outl(((!(sr & MII_ANA_T4AM) && de4x5_full_duplex) ? 0:GEP_FDXD)|GEP_MODE,\
 767                                                                   DE4X5_GEP);\
 768   } else {\
 769     omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));\
 770     omr |= (de4x5_full_duplex ? OMR_FD : 0);\
 771     outl(omr | OMR_PS | OMR_HBD | OMR_PCS | OMR_SCR, DE4X5_OMR);\
 772     outl((de4x5_full_duplex ? 0 : GEP_FDXD) | GEP_MODE, DE4X5_GEP);\
 773   }\
 774 }
 775 
 776 /*
 777 ** Include the IOCTL stuff
 778 */
 779 #include <linux/sockios.h>
 780 
 781 #define DE4X5IOCTL      SIOCDEVPRIVATE
 782 
 783 struct de4x5_ioctl {
 784         unsigned short cmd;                /* Command to run */
 785         unsigned short len;                /* Length of the data buffer */
 786         unsigned char  *data;              /* Pointer to the data buffer */
 787 };
 788 
 789 /* 
 790 ** Recognised commands for the driver 
 791 */
 792 #define DE4X5_GET_HWADDR        0x01 /* Get the hardware address */
 793 #define DE4X5_SET_HWADDR        0x02 /* Get the hardware address */
 794 #define DE4X5_SET_PROM          0x03 /* Set Promiscuous Mode */
 795 #define DE4X5_CLR_PROM          0x04 /* Clear Promiscuous Mode */
 796 #define DE4X5_SAY_BOO           0x05 /* Say "Boo!" to the kernel log file */
 797 #define DE4X5_GET_MCA           0x06 /* Get a multicast address */
 798 #define DE4X5_SET_MCA           0x07 /* Set a multicast address */
 799 #define DE4X5_CLR_MCA           0x08 /* Clear a multicast address */
 800 #define DE4X5_MCA_EN            0x09 /* Enable a multicast address group */
 801 #define DE4X5_GET_STATS         0x0a /* Get the driver statistics */
 802 #define DE4X5_CLR_STATS         0x0b /* Zero out the driver statistics */
 803 #define DE4X5_GET_OMR           0x0c /* Get the OMR Register contents */
 804 #define DE4X5_SET_OMR           0x0d /* Set the OMR Register contents */
 805 #define DE4X5_GET_REG           0x0e /* Get the DE4X5 Registers */

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