| tag | line | file | source code |
|---|
| NCR5380_read | 363 | drivers/scsi/NCR5380.c | data = NCR5380_read(CURRENT_SCSI_DATA_REG); |
| NCR5380_read | 364 | drivers/scsi/NCR5380.c | status = NCR5380_read(STATUS_REG); |
| NCR5380_read | 365 | drivers/scsi/NCR5380.c | mr = NCR5380_read(MODE_REG); |
| NCR5380_read | 366 | drivers/scsi/NCR5380.c | icr = NCR5380_read(INITIATOR_COMMAND_REG); |
| NCR5380_read | 367 | drivers/scsi/NCR5380.c | basr = NCR5380_read(BUS_AND_STATUS_REG); |
| NCR5380_read | 410 | drivers/scsi/NCR5380.c | status = NCR5380_read(STATUS_REG); |
| NCR5380_read | 871 | drivers/scsi/NCR5380.c | for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && |
| NCR5380_read | 880 | drivers/scsi/NCR5380.c | while (jiffies < timeout && (NCR5380_read(STATUS_REG) & SR_BSY)); |
| NCR5380_read | 1182 | drivers/scsi/NCR5380.c | basr = NCR5380_read(BUS_AND_STATUS_REG); |
| NCR5380_read | 1188 | drivers/scsi/NCR5380.c | if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == |
| NCR5380_read | 1196 | drivers/scsi/NCR5380.c | (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1201 | drivers/scsi/NCR5380.c | (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1202 | drivers/scsi/NCR5380.c | } else if ((NCR5380_read(STATUS_REG) & SR_RST) == SR_RST) { |
| NCR5380_read | 1206 | drivers/scsi/NCR5380.c | (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1220 | drivers/scsi/NCR5380.c | if ((NCR5380_read(MODE_REG) & MR_DMA) && ((basr & |
| NCR5380_read | 1234 | drivers/scsi/NCR5380.c | (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1239 | drivers/scsi/NCR5380.c | while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK |
| NCR5380_read | 1247 | drivers/scsi/NCR5380.c | while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK); |
| NCR5380_read | 1255 | drivers/scsi/NCR5380.c | printk("scsi : unknown interrupt, BASR 0x%X, MR 0x%X, SR 0x%x\n", basr, NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG)); |
| NCR5380_read | 1257 | drivers/scsi/NCR5380.c | (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 1365 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_PROGRESS) |
| NCR5380_read | 1377 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_PROGRESS)); |
| NCR5380_read | 1396 | drivers/scsi/NCR5380.c | if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) || |
| NCR5380_read | 1397 | drivers/scsi/NCR5380.c | (NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_higher_mask) || |
| NCR5380_read | 1398 | drivers/scsi/NCR5380.c | (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST)) { |
| NCR5380_read | 1411 | drivers/scsi/NCR5380.c | if (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) { |
| NCR5380_read | 1502 | drivers/scsi/NCR5380.c | while ((jiffies < timeout) && !(NCR5380_read(STATUS_REG) & |
| NCR5380_read | 1505 | drivers/scsi/NCR5380.c | if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == |
| NCR5380_read | 1525 | drivers/scsi/NCR5380.c | if (!(NCR5380_read(STATUS_REG) & SR_BSY)) { |
| NCR5380_read | 1573 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(STATUS_REG) & SR_REQ) && jiffies < timeout); |
| NCR5380_read | 1582 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(STATUS_REG) & SR_REQ)); |
| NCR5380_read | 1686 | drivers/scsi/NCR5380.c | while (!((tmp = NCR5380_read(STATUS_REG)) & SR_REQ)); |
| NCR5380_read | 1705 | drivers/scsi/NCR5380.c | *d = NCR5380_read(CURRENT_SCSI_DATA_REG); |
| NCR5380_read | 1741 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 1772 | drivers/scsi/NCR5380.c | tmp = NCR5380_read(STATUS_REG); |
| NCR5380_read | 1790 | drivers/scsi/NCR5380.c | PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); |
| NCR5380_read | 1826 | drivers/scsi/NCR5380.c | while (!(tmp = NCR5380_read(STATUS_REG)) & SR_REQ); |
| NCR5380_read | 1833 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 1890 | drivers/scsi/NCR5380.c | if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) { |
| NCR5380_read | 1936 | drivers/scsi/NCR5380.c | printk("scsi%d : mode reg = 0x%X\n", instance->host_no, NCR5380_read(MODE_REG)); |
| NCR5380_read | 1969 | drivers/scsi/NCR5380.c | tmp = NCR5380_read(BUS_AND_STATUS_REG); |
| NCR5380_read | 2012 | drivers/scsi/NCR5380.c | if (((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH|BASR_ACK)) == |
| NCR5380_read | 2014 | drivers/scsi/NCR5380.c | saved_data = NCR5380_read(INPUT_DATA_REGISTER); |
| NCR5380_read | 2020 | drivers/scsi/NCR5380.c | while (((tmp = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_ACK) || |
| NCR5380_read | 2021 | drivers/scsi/NCR5380.c | (NCR5380_read(STATUS_REG) & SR_REQ)) { |
| NCR5380_read | 2030 | drivers/scsi/NCR5380.c | instance->host_no, tmp, NCR5380_read(STATUS_REG)); |
| NCR5380_read | 2040 | drivers/scsi/NCR5380.c | *phase = NCR5380_read(STATUS_REG) & PHASE_MASK; |
| NCR5380_read | 2103 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)); |
| NCR5380_read | 2105 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 2106 | drivers/scsi/NCR5380.c | d[c - 1] = NCR5380_read(INPUT_DATA_REG); |
| NCR5380_read | 2123 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(BUS_AND_STATUS_REG) & |
| NCR5380_read | 2124 | drivers/scsi/NCR5380.c | BASR_DRQ) && (NCR5380_read(BUS_AND_STATUS_REG) & |
| NCR5380_read | 2127 | drivers/scsi/NCR5380.c | if (NCR5380_read(STATUS_REG) & SR_REQ) { |
| NCR5380_read | 2129 | drivers/scsi/NCR5380.c | !(NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK); |
| NCR5380_read | 2131 | drivers/scsi/NCR5380.c | for (; timeout && (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 2146 | drivers/scsi/NCR5380.c | if (NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT) { |
| NCR5380_read | 2158 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)); |
| NCR5380_read | 2176 | drivers/scsi/NCR5380.c | if (NCR5380_read(BUS_AND_STATUS_REG) & BASR_IRQ) { |
| NCR5380_read | 2180 | drivers/scsi/NCR5380.c | NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 2188 | drivers/scsi/NCR5380.c | *phase = NCR5380_read(STATUS_REG) & PHASE_MASK; |
| NCR5380_read | 2233 | drivers/scsi/NCR5380.c | tmp = NCR5380_read(STATUS_REG); |
| NCR5380_read | 2249 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_REQ); |
| NCR5380_read | 2477 | drivers/scsi/NCR5380.c | while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected) |
| NCR5380_read | 2518 | drivers/scsi/NCR5380.c | while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected) |
| NCR5380_read | 2733 | drivers/scsi/NCR5380.c | target_mask = NCR5380_read(CURRENT_SCSI_DATA_REG) & ~(hostdata->id_mask); |
| NCR5380_read | 2750 | drivers/scsi/NCR5380.c | while (NCR5380_read(STATUS_REG) & SR_SEL); |
| NCR5380_read | 2757 | drivers/scsi/NCR5380.c | while (!(NCR5380_read(STATUS_REG) & SR_REQ)); |
| NCR5380_read | 2865 | drivers/scsi/NCR5380.c | while (NCR5380_read(BUS_AND_STATUS_REG) & BASR_ACK); |
| NCR5380_read | 2927 | drivers/scsi/NCR5380.c | NCR5380_read(BUS_AND_STATUS_REG), NCR5380_read(STATUS_REG)); |
| NCR5380_read | 313 | drivers/scsi/g_NCR5380.c | if ((bl=NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { |
| NCR5380_read | 324 | drivers/scsi/g_NCR5380.c | if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { |
| NCR5380_read | 334 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) |
| NCR5380_read | 342 | drivers/scsi/g_NCR5380.c | dst[start+i] = NCR5380_read(C400_HOST_BUFFER); |
| NCR5380_read | 354 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) |
| NCR5380_read | 362 | drivers/scsi/g_NCR5380.c | dst[start+i] = NCR5380_read(C400_HOST_BUFFER); |
| NCR5380_read | 374 | drivers/scsi/g_NCR5380.c | if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) |
| NCR5380_read | 387 | drivers/scsi/g_NCR5380.c | if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) |
| NCR5380_read | 395 | drivers/scsi/g_NCR5380.c | NCR5380_read(RESET_PARITY_INTERRUPT_REG); |
| NCR5380_read | 416 | drivers/scsi/g_NCR5380.c | if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { |
| NCR5380_read | 421 | drivers/scsi/g_NCR5380.c | if ((bl=NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { |
| NCR5380_read | 436 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) |
| NCR5380_read | 456 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) |
| NCR5380_read | 484 | drivers/scsi/g_NCR5380.c | while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) |
| NCR5380_read | 493 | drivers/scsi/g_NCR5380.c | while (!(i = NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) |
| NCR5380_read | 504 | drivers/scsi/g_NCR5380.c | if (!((i=NCR5380_read(BUS_AND_STATUS_REG)) & BASR_END_DMA_TRANSFER)) |
| NCR5380_read | 515 | drivers/scsi/g_NCR5380.c | if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) { |
| NCR5380_read | 523 | drivers/scsi/g_NCR5380.c | while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) |
| NCR5380_read | 659 | drivers/scsi/g_NCR5380.c | status = NCR5380_read(STATUS_REG); |
| NCR5380_read | 225 | drivers/scsi/pas16.c | NCR5380_read( RESET_PARITY_INTERRUPT_REG ); |
| NCR5380_read | 301 | drivers/scsi/pas16.c | if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */ |
| NCR5380_read | 304 | drivers/scsi/pas16.c | if( NCR5380_read( MODE_REG ) != 0x00 ) |