drivers/net/pt.h

/* */
   1 /*
   2  * pt.h: Linux device driver for the Gracilis PackeTwin
   3  * Copyright (C) 1995 Craig Small VK2XLZ (vk2xlz@vk2xlz.ampr.org.)
   4  *
   5  * Please read the notice appearing at the top of the file pt.c
   6  */
   7 #define DMA_BUFF_SIZE 2200
   8 
   9 /* Network statistics, with the same names as 'struct enet_statistics'. */
  10 #define netstats enet_statistics
  11 
  12 #define ON 1
  13 #define OFF 0
  14 
  15 
  16 /* Register offset info, specific to the PT
  17  * E.g., to read the data port on channel A, use
  18  *  inportb(pichan[dev].base + CHANA + DATA)
  19  */
  20 #define CHANB   0   /* Base of channel B regs */
  21 #define CHANA   2   /* Base of channel A regs */
  22 
  23 /* 8530 ports on each channel */
  24 #define CTL 0
  25 #define DATA    1
  26 
  27 #define DMAEN   0x8 /* Offset off DMA Enable register */
  28 
  29 /* Timer chip offsets */
  30 #define TMR0    0x4 /* Offset of timer 0 register */
  31 #define TMR1    0x5 /* Offset of timer 1 register */
  32 #define TMR2    0x6 /* Offset of timer 2 register */
  33 #define TMRCMD  0x7 /* Offset of timer command register */
  34 #define INT_REG 0x8
  35 #define TMR1CLR 0x9
  36 #define TMR2CLR 0xa
  37 
  38 /* Interrupt register equates */
  39 #define PT_SCC_MSK      0x1
  40 #define PT_TMR1_MSK     0x2
  41 #define PT_TMR2_MSK     0x4
  42 
  43 /* Serial/interrupt register equates */
  44 #define PT_DTRA_ON      0x1
  45 #define PT_DTRB_ON      0x2
  46 #define PT_EXTCLKA      0x4
  47 #define PT_EXTCLKB      0x8
  48 #define PT_LOOPA_ON     0x10
  49 #define PT_LOOPB_ON     0x20
  50 #define PT_EI           0x80
  51 
  52 /* Timer chip equates */
  53 #define SC0 0x00 /* Select counter 0 */
  54 #define SC1 0x40 /* Select counter 1 */
  55 #define SC2 0x80 /* Select counter 2 */
  56 #define CLATCH  0x00 /* Counter latching operation */
  57 #define MSB 0x20 /* Read/load MSB only */
  58 #define LSB 0x10 /* Read/load LSB only */
  59 #define LSB_MSB 0x30 /* Read/load LSB, then MSB */
  60 #define MODE0   0x00 /* Interrupt on terminal count */
  61 #define MODE1   0x02 /* Programmable one shot */
  62 #define MODE2   0x04 /* Rate generator */
  63 #define MODE3   0x06 /* Square wave rate generator */
  64 #define MODE4   0x08 /* Software triggered strobe */
  65 #define MODE5   0x0a /* Hardware triggered strobe */
  66 #define BCD 0x01 /* BCD counter */
  67 
  68 /* DMA controller registers */
  69 #define DMA_STAT    8   /* DMA controller status register */
  70 #define DMA_CMD     8   /* DMA controller command register */
  71 #define DMA_MASK        10  /* DMA controller mask register */
  72 #define DMA_MODE        11  /* DMA controller mode register */
  73 #define DMA_RESETFF 12  /* DMA controller first/last flip flop  */
  74 /* DMA data */
  75 #define DMA_DISABLE (0x04)  /* Disable channel n */
  76 #define DMA_ENABLE  (0x00)  /* Enable channel n */
  77 /* Single transfers, incr. address, auto init, writes, ch. n */
  78 #define DMA_RX_MODE (0x54)
  79 /* Single transfers, incr. address, no auto init, reads, ch. n */
  80 #define DMA_TX_MODE (0x48)
  81 
  82 /* Write registers */
  83 #define DMA_CFG         0x08
  84 #define SERIAL_CFG      0x09
  85 #define INT_CFG         0x09    /* shares with serial config */
  86 #define DMA_CLR_FF      0x0a
  87 
  88 #define SINGLE 3686400
  89 #define DOUBLE 7372800
  90 #define XTAL   ((long) 6144000L)
  91 
  92 #define SIOCGPIPARAM            0x5000  /* get PI parameters */
  93 #define SIOCSPIPARAM            0x5001  /* set */
  94 #define SIOCGPIBAUD             0x5002  /* get only baud rate */
  95 #define SIOCSPIBAUD             0x5003  
  96 #define SIOCGPIDMA              0x5004  /* get only DMA */
  97 #define SIOCSPIDMA              0x5005  
  98 #define SIOCGPIIRQ              0x5006  /* get only IRQ */
  99 #define SIOCSPIIRQ              0x5007  
 100 
 101 struct pt_req  {
 102     int cmd;
 103     int speed;
 104     int clockmode;
 105     int txdelay;
 106     unsigned char persist;
 107     int slotime; 
 108     int squeldelay;
 109     int dmachan;    
 110     int irq;    
 111 };
 112 
 113 /* SCC Interrupt vectors, if we have set 'status low' */
 114 #define CHBTxIV         0x00
 115 #define CHBEXTIV        0x02
 116 #define CHBRxIV         0x04
 117 #define CHBSRCIV        0x06
 118 #define CHATxIV         0x08
 119 #define CHAEXTIV        0x0a
 120 #define CHARxIV         0x0c
 121 #define CHASRCIV        0x0e
 122 
 123 
 124 #ifdef __KERNEL__
 125 
 126 /* Information that needs to be kept for each channel. */
 127 struct pt_local {
 128     struct netstats stats; /* %%%dp*/
 129     long open_time;             /* Useless example local info. */
 130     unsigned long xtal; 
 131 
 132     struct mbuf *rcvbuf;/* Buffer for current rx packet */
 133     struct mbuf *rxdmabuf1; /* DMA rx buffer */
 134     struct mbuf *rxdmabuf2; /* DMA rx buffer */
 135 
 136     int bufsiz;         /* Size of rcvbuf */
 137     char *rcp;          /* Pointer into rcvbuf */
 138 
 139     struct sk_buff_head sndq;  /* Packets awaiting transmission */
 140     int sndcnt;         /* Number of packets on sndq */
 141     struct sk_buff *sndbuf;/* Current buffer being transmitted */
 142     char *txdmabuf;     /* Transmit DMA buffer */
 143         char *txptr;            /* Used by B port tx */
 144         int txcnt;                      
 145     char tstate;        /* Transmitter state */
 146 #define IDLE    0       /* Transmitter off, no data pending */
 147 #define ACTIVE  1       /* Transmitter on, sending data */
 148 #define UNDERRUN 2      /* Transmitter on, flushing CRC */
 149 #define FLAGOUT 3       /* CRC sent - attempt to start next frame */
 150 #define DEFER 4         /* Receive Active - DEFER Transmit */
 151 #define ST_TXDELAY 5    /* Sending leading flags */
 152 #define CRCOUT 6
 153     char rstate;        /* Set when !DCD goes to 0 (TRUE) */
 154 /* Normal state is ACTIVE if Receive enabled */
 155 #define RXERROR 2       /* Error -- Aborting current Frame */
 156 #define RXABORT 3       /* ABORT sequence detected */
 157 #define TOOBIG 4        /* too large a frame to store */
 158         
 159     int dev;            /* Device number */
 160     int base;       /* Base of I/O registers */
 161     int cardbase;     /* Base address of card */
 162     int stata;        /* address of Channel A status regs */
 163     int statb;        /* address of Channel B status regs */
 164     int speed;        /* Line speed, bps */
 165     int clockmode;    /* tapr 9600 modem clocking option */
 166     int txdelay;      /* Transmit Delay 10 ms/cnt */
 167     unsigned char persist;       /* Persistence (0-255) as a % */
 168     int slotime;      /* Delay to wait on persistence hit */
 169     int squeldelay;   /* Delay after XMTR OFF for squelch tail */
 170     struct iface *iface;    /* Associated interface */
 171     int dmachan;           /* DMA channel for this port */
 172     char saved_RR0;     /* The saved version of RR) that we compare with */
 173     int nrzi;                   /* Do we use NRZI (or NRZ) */
 174 };
 175 
 176 #endif
/* */
root/drivers/net/pt.h

INCLUDED FROM
