1 /*+M************************************************************************* 2 * Adaptec 274x/284x/294x device driver for Linux. 3 * 4 * Copyright (c) 1994 John Aycock 5 * The University of Calgary Department of Computer Science. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of Calgary 19 * Department of Computer Science and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * Sources include the Adaptec 1740 driver (aha1740.c), the Ultrastor 24F 37 * driver (ultrastor.c), various Linux kernel source, the Adaptec EISA 38 * config file (!adp7771.cfg), the Adaptec AHA-2740A Series User's Guide, 39 * the Linux Kernel Hacker's Guide, Writing a SCSI Device Driver for Linux, 40 * the Adaptec 1542 driver (aha1542.c), the Adaptec EISA overlay file 41 * (adp7770.ovl), the Adaptec AHA-2740 Series Technical Reference Manual, 42 * the Adaptec AIC-7770 Data Book, the ANSI SCSI specification, the 43 * ANSI SCSI-2 specification (draft 10c), ... 44 * 45 * ---------------------------------------------------------------- 46 * Modified to include support for wide and twin bus adapters, 47 * DMAing of SCBs, tagged queueing, IRQ sharing, bug fixes, 48 * and other rework of the code. 49 * 50 * Parts of this driver are based on the FreeBSD driver by Justin 51 * T. Gibbs. 52 * 53 * A Boot time option was also added for not resetting the scsi bus. 54 * 55 * Form: aic7xxx=extended,no_reset 56 * 57 * -- Daniel M. Eischen, deischen@iworks.InterWorks.org, 04/03/95 58 * 59 * $Id: aic7xxx.c,v 1.49 1995/06/28 05:41:09 deang Exp $ 60 *-M*************************************************************************/ 61
62 #ifdefMODULE 63 #include <linux/module.h>
64 #endif 65
66 #include <stdarg.h>
67 #include <asm/io.h>
68 #include <linux/string.h>
69 #include <linux/kernel.h>
70 #include <linux/ioport.h>
71 #include <linux/bios32.h>
72 #include <linux/delay.h>
73 #include <linux/sched.h>
74 #include <linux/pci.h>
75 #include <linux/proc_fs.h>
76 #include "../block/blk.h"
77 #include "sd.h"
78 #include "scsi.h"
79 #include "hosts.h"
80 #include "aic7xxx.h"
81
82 #defineAIC7XXX_C_VERSION "$Revision: 1.49 $"
83
84 #defineNUMBER(arr) (sizeof(arr) / sizeof(arr[0]))
85 #defineMIN(a,b) ((a < b) ? a : b)
86
87 /* 88 * Defines for PCI bus support, testing twin bus support, DMAing of 89 * SCBs, and tagged queueing. 90 * 91 * o PCI bus support - this has been implemented and working since 92 * the December 1, 1994 release of this driver. If you don't have 93 * a PCI bus and do not wish to configure your kernel with PCI 94 * support, then make sure this define is set to the cprrect 95 * define for PCI support (CONFIG_PCI) and configure your kernel 96 * without PCI support (make config). 97 * 98 * o Twin bus support - this has been tested and does work. 99 * 100 * o DMAing of SCBs - thanks to Kai Makisara, this now works 101 * 102 * o Tagged queueing - this driver is capable of tagged queueing 103 * but I am unsure as to how well the higher level driver implements 104 * tagged queueing. Therefore, the maximum commands per lun is 105 * set to 2. If you want to implement tagged queueing, ensure 106 * this define is not commented out. 107 * 108 * o Sharing IRQs - allowed for sharing of IRQs. This will allow 109 * for multiple aic7xxx host adapters sharing the same IRQ, but 110 * not for sharing IRQs with other devices. The higher level 111 * PCI code and interrupt handling needs to be modified to 112 * support this. 113 * 114 * Daniel M. Eischen, deischen@iworks.InterWorks.org, 03/11/95 115 */ 116
117 /* Uncomment this for testing twin bus support. */ 118 #defineAIC7XXX_TWIN_SUPPORT 119
120 /* Uncomment this for DMAing of SCBs. */ 121 #defineAIC7XXX_USE_DMA 122
123 /* Uncomment this for tagged queueing. */ 124 /* #define AIC7XXX_TAGGED_QUEUEING */ 125
126 /* Uncomment this for allowing sharing of IRQs. */ 127 #defineAIC7XXX_SHARE_IRQS 128
129 /* Set this to the delay in seconds after SCSI bus reset. */ 130 #defineAIC7XXX_RESET_DELAY 15
131
132 /* 133 * Uncomment this to always use scatter/gather lists. 134 * *NOTE: The sequencer must be changed also! 135 */ 136 #defineAIC7XXX_USE_SG 137
138 /* 139 * Controller type and options 140 */ 141 typedefenum{ 142 AIC_NONE,
143 AIC_274x, /* EISA aic7770 */ 144 AIC_284x, /* VLB aic7770 */ 145 AIC_7870, /* PCI aic7870 */ 146 AIC_7850, /* PCI aic7850 */ 147 AIC_7872/* PCI aic7870 on 394x */ 148 }aha_type;
149
150 typedefenum{ 151 AIC_SINGLE, /* Single Channel */ 152 AIC_TWIN, /* Twin Channel */ 153 AIC_WIDE/* Wide Channel */ 154 }aha_bus_type;
155
156 typedefenum{ 157 AIC_UNKNOWN,
158 AIC_ENABLED,
159 AIC_DISABLED 160 }aha_status_type;
161
162 /* 163 * There should be a specific return value for this in scsi.h, but 164 * it seems that most drivers ignore it. 165 */ 166 #define DID_UNDERFLOW DID_ERROR 167
168 /* 169 * What we want to do is have the higher level scsi driver requeue 170 * the command to us. There is no specific driver status for this 171 * condition, but the higher level scsi driver will requeue the 172 * command on a DID_BUS_BUSY error. 173 */ 174 #defineDID_RETRY_COMMANDDID_BUS_BUSY 175
176 /* 177 * EISA/VL-bus stuff 178 */ 179 #defineMINSLOT 1
180 #defineMAXSLOT 15
181 #defineSLOTBASE(x) ((x) << 12)
182 #defineMAXIRQ 15
183
184 /* 185 * Standard EISA Host ID regs (Offset from slot base) 186 */ 187 #defineHID0(x) ((x) + 0xC80) /* 0,1: msb of ID2, 2-7: ID1 */ 188 #defineHID1(x) ((x) + 0xC81) /* 0-4: ID3, 5-7: LSB ID2 */ 189 #defineHID2(x) ((x) + 0xC82) /* product */ 190 #define HID3(x) ((x) + 0xC83) /* firmware revision */ 191
192 /* 193 * AIC-7770 I/O range to reserve for a card 194 */ 195 #defineMINREG(x) ((x) + 0xC00ul)
196 #defineMAXREG(x) ((x) + 0xCBFul)
197
198 /* -------------------- AIC-7770 offset definitions ----------------------- */ 199
200 /* 201 * SCSI Sequence Control (p. 3-11). 202 * Each bit, when set starts a specific SCSI sequence on the bus 203 */ 204 #defineSCSISEQ(x) ((x) + 0xC00ul)
205 #defineTEMODEO 0x80
206 #defineENSELO 0x40
207 #defineENSELI 0x20
208 #defineENRSELI 0x10
209 #defineENAUTOATNO 0x08
210 #defineENAUTOATNI 0x04
211 #defineENAUTOATNP 0x02
212 #defineSCSIRSTO 0x01
213
214 /* 215 * SCSI Transfer Control 1 Register (pp. 3-14,15). 216 * Controls the SCSI module data path. 217 */ 218 #defineSXFRCTL1(x) ((x) + 0xC02ul)
219 #define BITBUCKET 0x80
220 #define SWRAPEN 0x40
221 #defineENSPCHK 0x20
222 #defineSTIMESEL 0x18
223 #defineENSTIMER 0x04
224 #defineACTNEGEN 0x02
225 #defineSTPWEN 0x01 /* Powered Termination */ 226
227 /* 228 * SCSI Control Signal Read Register (p. 3-15). 229 * Reads the actual state of the SCSI bus pins 230 */ 231 #defineSCSISIGI(x) ((x) + 0xC03ul)
232 #defineCDI 0x80
233 #defineIOI 0x40
234 #defineMSGI 0x20
235 #defineATNI 0x10
236 #defineSELI 0x08
237 #defineBSYI 0x04
238 #defineREQI 0x02
239 #defineACKI 0x01
240
241 /* 242 * SCSI Contol Signal Write Register (p. 3-16). 243 * Writing to this register modifies the control signals on the bus. Only 244 * those signals that are allowed in the current mode (Initiator/Target) are 245 * asserted. 246 */ 247 #defineSCSISIGO(x) ((x) + 0xC03ul)
248 #defineCDO 0x80
249 #define IOO 0x40
250 #defineMSGO 0x20
251 #defineATNO 0x10
252 #define SELO 0x08
253 #define BSYO 0x04
254 #define REQO 0x02
255 #define ACKO 0x01
256
257 /* 258 * SCSI Rate 259 */ 260 #defineSCSIRATE(x) ((x) + 0xC04ul)
261
262 /* 263 * SCSI ID (p. 3-18). 264 * Contains the ID of the board and the current target on the 265 * selected channel 266 */ 267 #defineSCSIID(x) ((x) + 0xC05ul)
268 #define TID 0xF0 /* Target ID mask */ 269 #define OID 0x0F /* Our ID mask */ 270
271 /* 272 * SCSI Status 0 (p. 3-21) 273 * Contains one set of SCSI Interrupt codes 274 * These are most likely of interest to the sequencer 275 */ 276 #defineSSTAT0(x) ((x) + 0xC0Bul)
277 #defineTARGET 0x80 /* Board is a target */ 278 #defineSELDO 0x40 /* Selection Done */ 279 #defineSELDI 0x20 /* Board has been selected */ 280 #defineSELINGO 0x10 /* Selection In Progress */ 281 #defineSWRAP 0x08 /* 24bit counter wrap */ 282 #defineSDONE 0x04 /* STCNT = 0x000000 */ 283 #defineSPIORDY 0x02 /* SCSI PIO Ready */ 284 #defineDMADONE 0x01 /* DMA transfer completed */ 285
286 /* 287 * Clear SCSI Interrupt 1 (p. 3-23) 288 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 289 */ 290 #defineCLRSINT1(x) ((x) + 0xC0Cul)
291 #defineCLRSELTIMEO 0x80
292 #defineCLRATNO 0x40
293 #define CLRSCSIRSTI 0x20
294 /* UNUSED 0x10 */ 295 #defineCLRBUSFREE 0x08
296 #defineCLRSCSIPERR 0x04
297 #defineCLRPHASECHG 0x02
298 #define CLRREQINIT 0x01
299
300 /* 301 * SCSI Status 1 (p. 3-24) 302 * These interrupt bits are of interest to the kernel driver 303 */ 304 #defineSSTAT1(x) ((x) + 0xC0Cul)
305 #defineSELTO 0x80
306 #defineATNTARG 0x40
307 #defineSCSIRSTI 0x20
308 #definePHASEMIS 0x10
309 #defineBUSFREE 0x08
310 #defineSCSIPERR 0x04
311 #definePHASECHG 0x02
312 #defineREQINIT 0x01
313
314 /* 315 * SCSI Interrrupt Mode 1 (pp. 3-28,29). 316 * Set bits in this register enable the corresponding 317 * interrupt source. 318 */ 319 #defineSIMODE1(x) ((x) + 0xC11ul)
320 #defineENSELTIMO 0x80
321 #defineENATNTARG 0x40
322 #define ENSCSIRST 0x20
323 #defineENPHASEMIS 0x10
324 #defineENBUSFREE 0x08
325 #defineENSCSIPERR 0x04
326 #defineENPHASECHG 0x02
327 #defineENREQINIT 0x01
328
329 /* 330 * Selection/Reselection ID (p. 3-31) 331 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 332 * device did not set its own ID. 333 */ 334 #defineSELID(x) ((x) + 0xC19ul)
335 #define SELID_MASK 0xF0
336 #define ONEBIT 0x08
337 /* UNUSED 0x07 */ 338
339 /* 340 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 341 * Controls the reading and writing of an external serial 1-bit 342 * EEPROM Device. In order to access the serial EEPROM, you must 343 * first set the SEEMS bit that generates a request to the memory 344 * port for access to the serial EEPROM device. When the memory 345 * port is not busy servicing another request, it reconfigures 346 * to allow access to the serial EEPROM. When this happens, SEERDY 347 * gets set high to verify that the memory port access has been 348 * granted. See aic7xxx_read_eprom for detailed information on 349 * the protocol necessary to read the serial EEPROM. 350 */ 351 #defineSEECTL(x) ((x) + 0xC1Eul)
352 #define EXTARBACK 0x80
353 #define EXTARBREQ 0x40
354 #defineSEEMS 0x20
355 #defineSEERDY 0x10
356 #defineSEECS 0x08
357 #defineSEECK 0x04
358 #define SEEDO 0x02
359 #defineSEEDI 0x01
360
361 /* 362 * SCSI Block Control (p. 3-32) 363 * Controls Bus type and channel selection. In a twin channel configuration 364 * addresses 0x00-0x1E are gated to the appropriate channel based on this 365 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 366 * on a wide bus. 367 */ 368 #defineSBLKCTL(x) ((x) + 0xC1Ful)
369 /* UNUSED 0xC0 */ 370 #defineAUTOFLUSHDIS 0x20 /* used for Rev C check */ 371 /* UNUSED 0x10 */ 372 #define SELBUSB 0x08
373 /* UNUSED 0x04 */ 374 #define SELWIDE 0x02
375 /* UNUSED 0x01 */ 376 #define SELSINGLE 0x00
377
378 /* 379 * Sequencer Control (p. 3-33) 380 * Error detection mode and speed configuration 381 */ 382 #defineSEQCTL(x) ((x) + 0xC60ul)
383 #definePERRORDIS 0x80
384 #define PAUSEDIS 0x40
385 #define FAILDIS 0x20
386 #defineFASTMODE 0x10
387 #define BRKADRINTEN 0x08
388 #define STEP 0x04
389 #defineSEQRESET 0x02
390 #defineLOADRAM 0x01
391
392 /* 393 * Sequencer RAM Data (p. 3-34) 394 * Single byte window into the Scratch Ram area starting at the address 395 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 396 * four bytes in sucessesion. The SEQADDRs will increment after the most 397 * significant byte is written 398 */ 399 #defineSEQRAM(x) ((x) + 0xC61ul)
400
401 /* 402 * Sequencer Address Registers (p. 3-35) 403 * Only the first bit of SEQADDR1 holds addressing information 404 */ 405 #defineSEQADDR0(x) ((x) + 0xC62ul)
406 #defineSEQADDR1(x) ((x) + 0xC63ul)
407
408 #defineACCUM(x) ((x) + 0xC64ul) /* accumulator */ 409
410 /* 411 * Board Control (p. 3-43) 412 */ 413 #defineBCTL(x) ((x) + 0xC84ul)
414 /* RSVD 0xF0 */ 415 #define ACE 0x08 /* Support for external processors */ 416 /* RSVD 0x06 */ 417 #defineENABLE 0x01
418
419 #define BUSSPD(x) ((x) + 0xC86ul) /* FIFO threshold bits ? */ 420
421 /* 422 * Host Control (p. 3-47) R/W 423 * Overal host control of the device. 424 */ 425 #defineHCNTRL(x) ((x) + 0xC87ul)
426 /* UNUSED 0x80 */ 427 #define POWRDN 0x40
428 /* UNUSED 0x20 */ 429 #defineSWINT 0x10
430 #defineIRQMS 0x08
431 #definePAUSE 0x04
432 #defineINTEN 0x02
433 #defineCHIPRST 0x01
434 #defineREQ_PAUSEIRQMS | PAUSE | INTEN 435 #define UNPAUSE_274X IRQMS | INTEN 436 #defineUNPAUSE_284XINTEN 437 #defineUNPAUSE_294XIRQMS | INTEN 438
439 /* 440 * SCB Pointer (p. 3-49) 441 * Gate one of the four SCBs into the SCBARRAY window. 442 */ 443 #defineSCBPTR(x) ((x) + 0xC90ul)
444
445 /* 446 * Interrupt Status (p. 3-50) 447 * Status for system interrupts 448 */ 449 #defineINTSTAT(x) ((x) + 0xC91ul)
450 #defineSEQINT_MASK 0xF0 /* SEQINT Status Codes */ 451 #defineBAD_PHASE 0x00
452 #defineSEND_REJECT 0x10
453 #defineNO_IDENT 0x20
454 #defineNO_MATCH 0x30
455 #defineMSG_SDTR 0x40
456 #defineMSG_WDTR 0x50
457 #defineMSG_REJECT 0x60
458 #defineBAD_STATUS 0x70
459 #defineRESIDUAL 0x80
460 #defineABORT_TAG 0x90
461 #defineAWAITING_MSG 0xa0
462 #defineBRKADRINT 0x08
463 #defineSCSIINT 0x04
464 #defineCMDCMPLT 0x02
465 #defineSEQINT 0x01
466 #defineINT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
467
468 /* 469 * Hard Error (p. 3-53) 470 * Reporting of catastrophic errors. You usually cannot recover from 471 * these without a full board reset. 472 */ 473 #defineERROR(x) ((x) + 0xC92ul)
474 /* UNUSED 0xF0 */ 475 #definePARERR 0x08
476 #defineILLOPCODE 0x04
477 #defineILLSADDR 0x02
478 #defineILLHADDR 0x01
479
480 /* 481 * Clear Interrupt Status (p. 3-52) 482 */ 483 #defineCLRINT(x) ((x) + 0xC92ul)
484 #define CLRBRKADRINT 0x08
485 #defineCLRSCSIINT 0x04
486 #defineCLRCMDINT 0x02
487 #defineCLRSEQINT 0x01
488
489 /* 490 * SCB Auto Increment (p. 3-59) 491 * Byte offset into the SCB Array and an optional bit to allow auto 492 * incrementing of the address during download and upload operations 493 */ 494 #defineSCBCNT(x) ((x) + 0xC9Aul)
495 #defineSCBAUTO 0x80
496 #define SCBCNT_MASK 0x1F
497
498 /* 499 * Queue In FIFO (p. 3-60) 500 * Input queue for queued SCBs (commands that the seqencer has yet to start) 501 */ 502 #defineQINFIFO(x) ((x) + 0xC9Bul)
503
504 /* 505 * Queue In Count (p. 3-60) 506 * Number of queued SCBs 507 */ 508 #defineQINCNT(x) ((x) + 0xC9Cul)
509
510 /* 511 * Queue Out FIFO (p. 3-61) 512 * Queue of SCBs that have completed and await the host 513 */ 514 #defineQOUTFIFO(x) ((x) + 0xC9Dul)
515
516 /* 517 * Queue Out Count (p. 3-61) 518 * Number of queued SCBs in the Out FIFO 519 */ 520 #defineQOUTCNT(x) ((x) + 0xC9Eul)
521
522 #defineSCBARRAY(x) ((x) + 0xCA0ul)
523
524 /* ---------------- END AIC-7770 Register Definitions ----------------- */ 525
526 /* --------------------- AIC-7870-only definitions -------------------- */ 527
528 #defineDSPCISTATUS(x) ((x) + 0xC86ul)
529 #defineDFTHRESH 0xC0
530
531 /* Scratch RAM offset definitions */ 532
533 /* ---------------------- Scratch RAM Offsets ------------------------- */ 534 /* These offsets are either to values that are initialized by the board's 535 * BIOS or are specified by the Linux sequencer code. If I can figure out 536 * how to read the EISA configuration info at probe time, the cards could 537 * be run without BIOS support installed 538 */ 539
540 /* 541 * 1 byte per target starting at this address for configuration values 542 */ 543 #defineHA_TARG_SCRATCH(x) ((x) + 0xC20ul)
544
545 /* 546 * The sequencer will stick the first byte of any rejected message here so 547 * we can see what is getting thrown away. 548 */ 549 #defineHA_REJBYTE(x) ((x) + 0xC31ul)
550
551 /* 552 * Bit vector of targets that have disconnection disabled. 553 */ 554 #define HA_DISC_DSB ((x) + 0xc32ul)
555
556 /* 557 * Length of pending message 558 */ 559 #defineHA_MSG_LEN(x) ((x) + 0xC34ul)
560
561 /* 562 * Outgoing Message Body 563 */ 564 #defineHA_MSG_START(x) ((x) + 0xC35ul)
565
566 /* 567 * These are offsets into the card's scratch ram. Some of the values are 568 * specified in the AHA2742 technical reference manual and are initialized 569 * by the BIOS at boot time. 570 */ 571 #defineHA_ARG_1(x) ((x) + 0xC4Aul) /* sdtr <-> rate parameters */ 572 #defineHA_RETURN_1(x) ((x) + 0xC4Aul)
573 #defineSEND_SENSE 0x80
574 #defineSEND_SDTR 0x80
575 #defineSEND_WDTR 0x80
576 #defineSEND_REJ 0x40
577
578 #defineHA_SIGSTATE(x) ((x) + 0xC4Bul) /* value in SCSISIGO */ 579 #defineHA_SCBCOUNT(x) ((x) + 0xC52ul) /* number of hardware SCBs */ 580
581 #defineHA_FLAGS(x) ((x) + 0xC53ul) /* TWIN and WIDE bus flags */ 582 #define SINGLE_BUS 0x00
583 #defineTWIN_BUS 0x01
584 #defineWIDE_BUS 0x02
585 #defineACTIVE_MSG 0x20
586 #define IDENTIFY_SEEN 0x40
587 #define RESELECTING 0x80
588
589 #defineHA_ACTIVE0(x) ((x) + 0xC54ul) /* Active bits; targets 0-7 */ 590 #defineHA_ACTIVE1(x) ((x) + 0xC55ul) /* Active bits; targets 8-15 */ 591 #define SAVED_TCL(x) ((x) + 0xC56ul) /* Saved target, channel, LUN */ 592 #defineWAITING_SCBH(x) ((x) + 0xC57ul) /* Head of disconnected targets list. */ 593 #defineWAITING_SCBT(x) ((x) + 0xC58ul) /* Tail of disconnected targets list. */ 594
595 #defineHA_SCSICONF(x) ((x) + 0xC5Aul) /* SCSI config register */ 596 #defineHA_INTDEF(x) ((x) + 0xC5Cul) /* interrupt def'n register */ 597 #defineHA_HOSTCONF(x) ((x) + 0xC5Dul) /* host config def'n register */ 598
599 #define MSG_ABORT 0x06
600 #defineMSG_BUS_DEVICE_RESET 0x0c
601 #defineBUS_8_BIT 0x00
602 #defineBUS_16_BIT 0x01
603 #defineBUS_32_BIT 0x02
604
605
606 /* 607 * 608 * Define the format of the SEEPROM registers (16 bits). 609 * 610 */ 611 structseeprom_config{ 612
613 /* 614 * SCSI ID Configuration Flags 615 */ 616 #defineCFXFER 0x0007 /* synchronous transfer rate */ 617 #defineCFSYNCH 0x0008 /* enable synchronous transfer */ 618 #define CFDISC 0x0010 /* enable disconnection */ 619 #defineCFWIDEB 0x0020 /* wide bus device */ 620 /* UNUSED 0x00C0 */ 621 #define CFSTART 0x0100 /* send start unit SCSI command */ 622 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 623 #define CFRNFOUND 0x0400 /* report even if not found */ 624 /* UNUSED 0xF800 */ 625 unsignedshortdevice_flags[16]; /* words 0-15 */ 626
627 /* 628 * BIOS Control Bits 629 */ 630 #define CFSUPREM 0x0001 /* support all removeable drives */ 631 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 632 #define CFBIOSEN 0x0004 /* BIOS enabled */ 633 /* UNUSED 0x0008 */ 634 #define CFSM2DRV 0x0010 /* support more than two drives */ 635 /* UNUSED 0x0060 */ 636 #defineCFEXTEND 0x0080 /* extended translation enabled */ 637 /* UNUSED 0xFF00 */ 638 unsignedshortbios_control; /* word 16 */ 639
640 /* 641 * Host Adapter Control Bits 642 */ 643 /* UNUSED 0x0003 */ 644 #defineCFWSTERM 0x0008 /* SCSI high byte termination (wide card) */ 645 #defineCFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */ 646 #defineCFSPARITY 0x0010 /* SCSI parity */ 647 /* UNUSED 0x0020 */ 648 #define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */ 649 /* UNUSED 0xFF80 */ 650 unsignedshortadapter_control; /* word 17 */ 651
652 /* 653 * Bus Release, Host Adapter ID 654 */ 655 #defineCFSCSIID 0x000F /* host adapter SCSI ID */ 656 /* UNUSED 0x00F0 */ 657 #defineCFBRTIME 0xFF00 /* bus release time */ 658 unsignedshortbrtime_id; /* word 18 */ 659
660 /* 661 * Maximum targets 662 */ 663 #define CFMAXTARG 0x00FF /* maximum targets */ 664 /* UNUSED 0xFF00 */ 665 unsignedshortmax_targets; /* word 19 */ 666
667 unsignedshort res_1[11]; /* words 20-30 */ 668 unsignedshortchecksum; /* word 31 */ 669
670 };
671
672
673 #defineAIC7XXX_DEBUG 674
675 /* 676 * Pause the sequencer and wait for it to actually stop - this 677 * is important since the sequencer can disable pausing for critical 678 * sections. 679 */ 680 #definePAUSE_SEQUENCER(p) \
681 outb(p->pause, HCNTRL(p->base)); \
682 while ((inb(HCNTRL(p->base)) & PAUSE) == 0) \
683 ; \
684
685 /* 686 * Unpause the sequencer. Unremarkable, yet done often enough to 687 * warrant an easy way to do it. 688 */ 689 #defineUNPAUSE_SEQUENCER(p) \
690 outb(p->unpause, HCNTRL(p->base))
691
692 /* 693 * Restart the sequencer program from address zero 694 */ 695 #defineRESTART_SEQUENCER(p) \
696 do{ \
697 outb(SEQRESET | FASTMODE, SEQCTL(p->base)); \
698 }while (inb(SEQADDR0(p->base)) != 0 && \
699 inb(SEQADDR1(p->base)) != 0); \
700 UNPAUSE_SEQUENCER(p);
701
702 /* 703 * If an error occurs during a data transfer phase, run the comand 704 * to completion - it's easier that way - making a note of the error 705 * condition in this location. This then will modify a DID_OK status 706 * into an appropriate error for the higher-level SCSI code. 707 */ 708 #defineaic7xxx_error(cmd) ((cmd)->SCp.Status)
709
710 /* 711 * Keep track of the targets returned status. 712 */ 713 #defineaic7xxx_status(cmd) ((cmd)->SCp.sent_command)
714
715 /* 716 * The position of the SCSI commands scb within the scb array. 717 */ 718 #defineaic7xxx_position(cmd) ((cmd)->SCp.have_data_in)
719
720 /* 721 * Since the sequencer code DMAs the scatter-gather structures 722 * directly from memory, we use this macro to assert that the 723 * kernel structure hasn't changed. 724 */ 725 #defineSG_STRUCT_CHECK(sg) \
726 ((char *)&(sg).address - (char *)&(sg) != 0 || \
727 (char *)&(sg).length - (char *)&(sg) != 8 || \
728 sizeof((sg).address) != 4 || \
729 sizeof((sg).length) != 4 || \
730 sizeof(sg) != 12)
731
732 /* 733 * "Static" structures. Note that these are NOT initialized 734 * to zero inside the kernel - we have to initialize them all 735 * explicitly. 736 * 737 * We support a maximum of one adapter card per IRQ level (see the 738 * rationale for this above). On an interrupt, use the IRQ as an 739 * index into aic7xxx_boards[] to locate the card information. 740 */ 741 staticstructScsi_Host *aic7xxx_boards[MAXIRQ + 1];
742
743 /* 744 * The driver keeps up to four scb structures per card in memory. Only the 745 * first 26 bytes of the structure are valid for the hardware, the rest used 746 * for driver level bookeeping. The driver is further optimized 747 * so that we only have to download the first 19 bytes since as long 748 * as we always use S/G, the last fields should be zero anyway. 749 */ 750 #ifdefAIC7XXX_USE_SG 751 #defineSCB_DOWNLOAD_SIZE 19 /* amount to actually download */ 752 #else 753 #defineSCB_DOWNLOAD_SIZE 26
754 #endif 755
756 #defineSCB_UPLOAD_SIZE 19 /* amount to actually upload */ 757
758 structaic7xxx_scb{ 759 /* ------------ Begin hardware supported fields ---------------- */ 760 /*1 */unsignedcharcontrol;
761 #defineSCB_NEEDWDTR 0x80 /* Initiate Wide Negotiation */ 762 #defineSCB_NEEDSDTR 0x40 /* Initiate Sync Negotiation */ 763 #defineSCB_NEEDDMA 0x08 /* SCB needs to be DMA'd from 764 * from host memory 765 */ 766 #define SCB_REJ_MDP 0x80 /* Reject MDP message */ 767 #define SCB_DISEN 0x40 /* SCB Disconnect enable */ 768 #defineSCB_TE 0x20 /* Tag enable */ 769 /* RESERVED 0x10 */ 770 #define SCB_WAITING 0x08 /* Waiting */ 771 #defineSCB_DIS 0x04 /* Disconnected */ 772 #define SCB_TAG_TYPE 0x03
773 #define SIMPLE_QUEUE 0x00 /* Simple Queue */ 774 #define HEAD_QUEUE 0x01 /* Head of Queue */ 775 #define ORD_QUEUE 0x02 /* Ordered Queue */ 776 /* ILLEGAL 0x03 */ 777 /*2 */unsignedchartarget_channel_lun; /* 4/1/3 bits */ 778 /*3 */unsignedcharSG_segment_count;
779 /*7 */unsignedcharSG_list_pointer[4] __attribute__ ((packed));
780 /*11*/unsignedcharSCSI_cmd_pointer[4] __attribute__ ((packed));
781 /*12*/unsignedcharSCSI_cmd_length;
782 /*14*/unsignedcharRESERVED[2]; /* must be zero */ 783 /*15*/unsignedchartarget_status;
784 /*18*/unsignedchar residual_data_count[3];
785 /*19*/unsignedcharresidual_SG_segment_count;
786 /*23*/unsignedchardata_pointer[4] __attribute__ ((packed));
787 /*26*/unsignedchardata_count[3];
788 /*30*/unsignedcharhost_scb[4] __attribute__ ((packed));
789 /*31*/u_charnext_waiting; /* Used to thread SCBs awaiting selection. */ 790 #defineSCB_LIST_NULL 0x10 /* SCB list equivelent to NULL */ 791 #if 0
792 /* 793 * No real point in transferring this to the 794 * SCB registers. 795 */ 796 unsignedcharRESERVED[1];
797 #endif 798
799 /*-----------------end of hardware supported fields----------------*/ 800 structaic7xxx_scb *next; /* next ptr when in free list */ 801 Scsi_Cmnd *cmd; /* Scsi_Cmnd for this scb */ 802 intstate; /* current state of scb */ 803 #defineSCB_FREE 0x00
804 #defineSCB_ACTIVE 0x01
805 #define SCB_ABORTED 0x02
806 #defineSCB_DEVICE_RESET 0x04
807 #define SCB_IMMED 0x08
808 #define SCB_SENSE 0x10
809 unsignedintposition; /* Position in scb array */ 810 #ifdefAIC7XXX_USE_SG 811 structscatterlistsg;
812 structscatterlistsense_sg;
813 #endif 814 unsignedcharsense_cmd[6]; /* Allocate 6 characters for sense command */ 815 };
816
817 staticstruct{ 818 unsignedcharerrno;
819 char *errmesg;
820 }hard_error[] = { 821 {ILLHADDR, "Illegal Host Access" },
822 {ILLSADDR, "Illegal Sequencer Address referrenced" },
823 {ILLOPCODE, "Illegal Opcode in sequencer program" },
824 {PARERR, "Sequencer Ram Parity Error" } 825 };
826
827 staticunsignedchar 828 generic_sense[] = {REQUEST_SENSE, 0, 0, 0, 255, 0 };
829
830 /* 831 * The maximum number of SCBs we could have for ANY type 832 * of card. DON'T FORGET TO CHANGE THE SCB MASK IN THE 833 * SEQUENCER CODE IF THIS IS MODIFIED! 834 */ 835 #defineAIC7XXX_MAXSCB 16
836
837 /* 838 * Define a structure used for each host adapter, only one per IRQ. 839 */ 840 structaic7xxx_host{ 841 intbase; /* card base address */ 842 intmaxscb; /* hardware SCBs */ 843 intnumscb; /* current number of scbs */ 844 intextended; /* extended xlate? */ 845 aha_typetype; /* card type */ 846 aha_bus_typebus_type; /* normal/twin/wide bus */ 847 unsignedchara_scanned; /* 0 not scanned, 1 scanned */ 848 unsignedcharb_scanned; /* 0 not scanned, 1 scanned */ 849 unsignedintisr_count; /* Interrupt count */ 850 volatileunsignedcharunpause; /* unpause value for HCNTRL */ 851 volatileunsignedcharpause; /* pause value for HCNTRL */ 852 volatileunsignedshortneedsdtr_copy; /* default config */ 853 volatileunsignedshortneedsdtr;
854 volatileunsignedshortsdtr_pending;
855 volatileunsignedshortneedwdtr_copy; /* default config */ 856 volatileunsignedshortneedwdtr;
857 volatileunsignedshortwdtr_pending;
858 structseeprom_configseeprom;
859 inthave_seeprom;
860 structScsi_Host *next; /* allow for multiple IRQs */ 861 structaic7xxx_scbscb_array[AIC7XXX_MAXSCB]; /* active commands */ 862 structaic7xxx_scb *free_scb; /* list of free SCBs */ 863 };
864
865 structaic7xxx_host_config{ 866 intirq; /* IRQ number */ 867 intbase; /* I/O base */ 868 intmaxscb; /* hardware SCBs */ 869 intunpause; /* unpause value for HCNTRL */ 870 intpause; /* pause value for HCNTRL */ 871 intscsi_id; /* host SCSI ID */ 872 intscsi_id_b; /* host SCSI ID B channel for twin cards */ 873 intextended; /* extended xlate? */ 874 intbusrtime; /* bus release time */ 875 aha_typetype; /* card type */ 876 aha_bus_typebus_type; /* normal/twin/wide bus */ 877 aha_status_typeparity; /* bus parity enabled/disabled */ 878 aha_status_typelow_term; /* bus termination low byte */ 879 aha_status_typehigh_term; /* bus termination high byte (wide cards only) */ 880 };
881
882 /* 883 * Valid SCSIRATE values. (p. 3-17) 884 * Provides a mapping of tranfer periods in ns to the proper value to 885 * stick in the scsiscfr reg to use that transfer rate. 886 */ 887 staticstruct{ 888 shortperiod;
889 shortrate;
890 char *english;
891 }aic7xxx_syncrates[] = { 892 { 100, 0, "10.0" },
893 { 125, 1, "8.0" },
894 { 150, 2, "6.67" },
895 { 175, 3, "5.7" },
896 { 200, 4, "5.0" },
897 { 225, 5, "4.4" },
898 { 250, 6, "4.0" },
899 { 275, 7, "3.6" } 900 };
901
902 staticintnum_aic7xxx_syncrates =
903 sizeof(aic7xxx_syncrates) / sizeof(aic7xxx_syncrates[0]);
904
905 #ifdefAIC7XXX_DEBUG 906 externintvsprintf(char *, constchar *, va_list);
907
908 staticvoid 909 debug(constchar *fmt, ...)
/* */ 910 { 911 va_listap;
912 charbuf[256];
913
914 va_start(ap, fmt);
915 vsprintf(buf, fmt, ap);
916 printk(buf);
917 va_end(ap);
918 } 919
920 staticvoid 921 debug_config(structaic7xxx_host_config *p)
/* */ 922 { 923 inthost_conf, scsi_conf;
924 unsignedcharbrelease;
925 unsignedchardfthresh;
926
927 staticintDFT[] = { 0, 50, 75, 100 };
928 staticintSST[] = { 256, 128, 64, 32 };
929 staticchar *BUSW[] = { "", "-TWIN", "-WIDE" };
930
931 host_conf = inb(HA_HOSTCONF(p->base));
932 scsi_conf = inb(HA_SCSICONF(p->base));
933
934 /* 935 * The 7870 gets the bus release time and data FIFO threshold 936 * from the serial EEPROM (stored in the config structure) and 937 * scsi_conf register respectively. The 7770 gets the bus 938 * release time and data FIFO threshold from the scsi_conf and 939 * host_conf registers respectively. 940 */ 941 if ((p->type == AIC_274x) || (p->type == AIC_284x))
942 { 943 brelease = scsi_conf & 0x3F;
944 dfthresh = host_conf >> 6;
945 } 946 else 947 { 948 brelease = p->busrtime;
949 dfthresh = scsi_conf >> 6;
950 } 951 if (brelease == 0)
952 { 953 brelease = 2;
954 } 955
956 switch (p->type)
957 { 958 caseAIC_274x:
959 printk("AIC7770%s AT EISA SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
960 break;
961
962 caseAIC_284x:
963 printk("AIC7770%s AT VLB SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
964 break;
965
966 caseAIC_7870:
967 printk("AIC7870%s (PCI-bus):\n", BUSW[p->bus_type]);
968 break;
969
970 caseAIC_7850:
971 printk("AIC7850%s (PCI-bus):\n", BUSW[p->bus_type]);
972 break;
973
974 caseAIC_7872:
975 printk("AIC7872%s (PCI-bus):\n", BUSW[p->bus_type]);
976 break;
977
978 default:
979 panic("aic7xxx debug_config: internal error\n");
980 } 981
982 printk(" irq %d\n"
983 " bus release time %d bclks\n"
984 " data fifo threshold %d%%\n",
985 p->irq,
986 brelease,
987 DFT[dfthresh]);
988
989 printk(" SCSI CHANNEL A:\n"
990 " scsi id %d\n"
991 " scsi selection timeout %d ms\n"
992 " scsi bus reset at power-on %sabled\n",
993 scsi_conf & 0x07,
994 SST[(scsi_conf >> 3) & 0x03],
995 (scsi_conf & 0x40) ? "en" : "dis");
996
997 if (((p->type == AIC_274x) || (p->type == AIC_284x)) && p->parity == AIC_UNKNOWN)
998 {/* Set the parity for 7770 based cards. */ 999 p->parity = (scsi_conf & 0x20) ? AIC_ENABLED : AIC_DISABLED;
1000 }1001 if (p->parity != AIC_UNKNOWN)
1002 {1003 printk(" scsi bus parity %sabled\n",
1004 (p->parity == AIC_ENABLED) ? "en" : "dis");
1005 }1006
1007 if (p->type == AIC_274x)
1008 {1009 p->low_term = (scsi_conf & 0x80) ? AIC_ENABLED : AIC_DISABLED;
1010 }1011 if (p->low_term != AIC_UNKNOWN)
1012 {1013 printk(" scsi bus termination (low byte) %sabled\n",
1014 (p->low_term == AIC_ENABLED) ? "en" : "dis");
1015 }1016 if ((p->bus_type == AIC_WIDE) && (p->high_term != AIC_UNKNOWN))
1017 {1018 printk(" scsi bus termination (high byte) %sabled\n",
1019 (p->high_term == AIC_ENABLED) ? "en" : "dis");
1020 }1021 }1022 #else1023 # definedebug(fmt, args...)
1024 # definedebug_config(x)
1025 #endifAIC7XXX_DEBUG1026
1027 /*1028 * XXX - these options apply unilaterally to _all_ 274x/284x/294x1029 * cards in the system. This should be fixed, but then,1030 * does anyone really have more than one in a machine?1031 */1032 staticintaic7xxx_extended = 0; /* extended translation on? */1033 staticintaic7xxx_no_reset = 0; /* no resetting of SCSI bus */1034
1035 /*+F*************************************************************************1036 * Function:1037 * aic7xxx_setup1038 *1039 * Description:1040 * Handle Linux boot parameters.1041 *-F*************************************************************************/1042 void1043 aic7xxx_setup(char *s, int *dummy)
/* */1044 {1045 inti;
1046 char *p;
1047
1048 staticstruct{1049 char *name;
1050 int *flag;
1051 }options[] = {1052 { "extended", &aic7xxx_extended},
1053 { "no_reset", &aic7xxx_no_reset},
1054 {NULL, NULL}1055 };
1056
1057 for (p = strtok(s, ","); p; p = strtok(NULL, ","))
1058 {1059 for (i = 0; options[i].name; i++)
1060 {1061 if (!strcmp(options[i].name, p))
1062 {1063 *(options[i].flag) = !0;
1064 }1065 }1066 }1067 }1068
1069 /*+F*************************************************************************1070 * Function:1071 * aic7xxx_loadseq1072 *1073 * Description:1074 * Load the sequencer code into the controller memory.1075 *-F*************************************************************************/1076 staticvoid1077 aic7xxx_loadseq(intbase)
/* */1078 {1079 staticunsignedcharseqprog[] = {1080 /*1081 * Each sequencer instruction is 29 bits1082 * long (fill in the excess with zeroes)1083 * and has to be loaded from least -> most1084 * significant byte, so this table has the1085 * byte ordering reversed.1086 */1087 # include "aic7xxx_seq.h"
1088 };
1089
1090 /*1091 * When the AIC-7770 is paused (as on chip reset), the1092 * sequencer address can be altered and a sequencer1093 * program can be loaded by writing it, byte by byte, to1094 * the sequencer RAM port - the Adaptec documentation1095 * recommends using REP OUTSB to do this, hence the inline1096 * assembly. Since the address autoincrements as we load1097 * the program, reset it back to zero afterward. Disable1098 * sequencer RAM parity error detection while loading, and1099 * make sure the LOADRAM bit is enabled for loading.1100 */1101 outb(PERRORDIS | SEQRESET | LOADRAM, SEQCTL(base));
1102
1103 asmvolatile("cld\n\t"
1104 "rep\n\t"
1105 "outsb"
1106 : /* no output */1107 :"S" (seqprog), "c" (sizeof(seqprog)), "d" (SEQRAM(base))
1108 :"si", "cx", "dx");
1109
1110 /*1111 * WARNING! This is a magic sequence! After extensive1112 * experimentation, it seems that you MUST turn off the1113 * LOADRAM bit before you play with SEQADDR again, else1114 * you will end up with parity errors being flagged on1115 * your sequencer program. (You would also think that1116 * turning off LOADRAM and setting SEQRESET to reset the1117 * address to zero would work, but you need to do it twice1118 * for it to take effect on the address. Timing problem?)1119 */1120 do{1121 /*1122 * Actually, reset it until1123 * the address shows up as1124 * zero just to be safe..1125 */1126 outb(SEQRESET | FASTMODE, SEQCTL(base));
1127 }while ((inb(SEQADDR0(base)) != 0) && (inb(SEQADDR1(base)) != 0));
1128 }1129
1130 /*+F*************************************************************************1131 * Function:1132 * aic7xxx_delay1133 *1134 * Description:1135 * Delay for specified amount of time.1136 *-F*************************************************************************/1137 staticvoid1138 aic7xxx_delay(intseconds)
/* */1139 {1140 unsignedlongi;
1141
1142 i = jiffies + (seconds * 100); /* compute time to stop */1143
1144 while (jiffies < i)
1145 {1146 ; /* Do nothing! */1147 }1148 }1149
1150 /*+F*************************************************************************1151 * Function:1152 * rcs_version1153 *1154 * Description:1155 * Return a string containing just the RCS version number from either1156 * an Id or Revison RCS clause.1157 *-F*************************************************************************/1158 constchar *
1159 rcs_version(constchar *version_info)
/* */1160 {1161 staticcharbuf[10];
1162 char *bp, *ep;
1163
1164 bp = NULL;
1165 strcpy(buf, "????");
1166 if (!strncmp(version_info, "$Id: ", 5))
1167 {1168 if ((bp = strchr(version_info, ' ')) != NULL)
1169 {1170 bp++;
1171 if ((bp = strchr(bp, ' ')) != NULL)
1172 {1173 bp++;
1174 }1175 }1176 }1177 else1178 {1179 if (!strncmp(version_info, "$Revision: ", 11))
1180 {1181 if ((bp = strchr(version_info, ' ')) != NULL)
1182 {1183 bp++;
1184 }1185 }1186 }1187
1188 if (bp != NULL)
1189 {1190 if ((ep = strchr(bp, ' ')) != NULL)
1191 {1192 registerintlen = ep - bp;
1193
1194 strncpy(buf, bp, len);
1195 buf[len] = '\0';
1196 }1197 }1198
1199 returnbuf;
1200 }1201
1202 /*+F*************************************************************************1203 * Function:1204 * aic7xxx_info1205 *1206 * Description:1207 * Return a string describing the driver.1208 *-F*************************************************************************/1209 constchar *
1210 aic7xxx_info(structScsi_Host *notused)
/* */1211 {1212 staticcharbuffer[128];
1213
1214 strcpy(buffer, "Adaptec AHA274x/284x/294x (EISA/VLB/PCI-Fast SCSI) ");
1215 strcat(buffer, rcs_version(AIC7XXX_C_VERSION));
1216 strcat(buffer, "/");
1217 strcat(buffer, rcs_version(AIC7XXX_H_VERSION));
1218 strcat(buffer, "/");
1219 strcat(buffer, rcs_version(AIC7XXX_SEQ_VER));
1220
1221 returnbuffer;
1222 }1223
1224 /*+F*************************************************************************1225 * Function:1226 * aic7xxx_putscb1227 *1228 * Description:1229 * Transfer a SCB to the controller.1230 *-F*************************************************************************/1231 staticvoid1232 aic7xxx_putscb(intbase, structaic7xxx_scb *scb)
/* */1233 {1234 #ifdefAIC7XXX_USE_DMA1235 /*1236 * All we need to do, is to output the position1237 * of the SCB in the SCBARRAY to the QINFIFO1238 * of the host adapter.1239 */1240 outb(scb->position, QINFIFO(base));
1241 #else1242 /*1243 * By turning on the SCB auto increment, any reference1244 * to the SCB I/O space postincrements the SCB address1245 * we're looking at. So turn this on and dump the relevant1246 * portion of the SCB to the card.1247 */1248 outb(SCBAUTO, SCBCNT(base));
1249
1250 asmvolatile("cld\n\t"
1251 "rep\n\t"
1252 "outsb"
1253 : /* no output */1254 :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1255 :"si", "cx", "dx");
1256
1257 outb(0, SCBCNT(base));
1258 #endif1259 }1260
1261 /*+F*************************************************************************1262 * Function:1263 * aic7xxx_putdmascb1264 *1265 * Description:1266 * DMA a SCB to the controller.1267 *-F*************************************************************************/1268 staticvoid1269 aic7xxx_putdmascb(intbase, structaic7xxx_scb *scb)
/* */1270 {1271 /*1272 * By turning on the SCB auto increment, any reference1273 * to the SCB I/O space postincrements the SCB address1274 * we're looking at. So turn this on and dump the relevant1275 * portion of the SCB to the card.1276 */1277 outb(SCBAUTO, SCBCNT(base));
1278
1279 asmvolatile("cld\n\t"
1280 "rep\n\t"
1281 "outsb"
1282 : /* no output */1283 :"S" (scb), "c" (31), "d" (SCBARRAY(base))
1284 :"si", "cx", "dx");
1285
1286 outb(0, SCBCNT(base));
1287 }1288
1289 /*+F*************************************************************************1290 * Function:1291 * aic7xxx_getscb1292 *1293 * Description:1294 * Get a SCB from the controller.1295 *-F*************************************************************************/1296 staticvoid1297 aic7xxx_getscb(intbase, structaic7xxx_scb *scb)
/* */1298 {1299 /*1300 * This is almost identical to aic7xxx_putscb().1301 */1302 outb(SCBAUTO, SCBCNT(base));
1303
1304 asmvolatile("cld\n\t"
1305 "rep\n\t"
1306 "insb"
1307 : /* no output */1308 :"D" (scb), "c" (SCB_UPLOAD_SIZE), "d" (SCBARRAY(base))
1309 :"di", "cx", "dx");
1310
1311 outb(0, SCBCNT(base));
1312 }1313
1314 /*+F*************************************************************************1315 * Function:1316 * aic7xxx_length1317 *1318 * Description:1319 * How much data should be transferred for this SCSI command? Stop1320 * at segment sg_last if it's a scatter-gather command so we can1321 * compute underflow easily.1322 *-F*************************************************************************/1323 staticunsigned1324 aic7xxx_length(Scsi_Cmnd *cmd, intsg_last)
/* */1325 {1326 inti, segments;
1327 unsignedlength;
1328 structscatterlist *sg;
1329
1330 segments = cmd->use_sg - sg_last;
1331 sg = (structscatterlist *) cmd->buffer;
1332
1333 if (cmd->use_sg)
1334 {1335 for (i = length = 0; i < cmd->use_sg && i < segments; i++)
1336 {1337 length += sg[i].length;
1338 }1339 }1340 else1341 {1342 length = cmd->request_bufflen;
1343 }1344
1345 return(length);
1346 }1347
1348 /*+F*************************************************************************1349 * Function:1350 * aic7xxx_scsirate1351 *1352 * Description:1353 * Look up the valid period to SCSIRATE conversion in our table1354 *-F*************************************************************************/1355 staticvoid1356 aic7xxx_scsirate(unsignedchar *scsirate, unsignedcharperiod,
/* */1357 unsignedcharoffset, inttarget)
1358 {1359 inti;
1360
1361 for (i = 0; i < num_aic7xxx_syncrates; i++)
1362 {1363 if ((aic7xxx_syncrates[i].period - period) >= 0)
1364 {1365 *scsirate = (aic7xxx_syncrates[i].rate << 4) | (offset & 0x0F);
1366 printk("aic7xxx: target %d now synchronous at %sMb/s, offset = 0x%x\n",
1367 target, aic7xxx_syncrates[i].english, offset);
1368 return;
1369 }1370 }1371
1372 /*1373 * Default to asyncronous transfer1374 */1375 *scsirate = 0;
1376 printk("aic7xxx: target %d using asynchronous transfers\n", target);
1377 }1378
1379 /*+F*************************************************************************1380 * Function:1381 * aic7xxx_isr1382 *1383 * Description:1384 * SCSI controller interrupt handler.1385 *1386 * NOTE: Since we declared this using SA_INTERRUPT, interrupts should1387 * be disabled all through this function unless we say otherwise.1388 *-F*************************************************************************/1389 staticvoid1390 aic7xxx_isr(intirq, structpt_regs * regs)
/* */1391 {1392 intbase, intstat;
1393 structaic7xxx_host *p;
1394 structaic7xxx_scb *scb;
1395 unsignedcharactive, ha_flags, transfer;
1396 unsignedcharscsi_id, bus_width;
1397 unsignedcharoffset, rate, scratch;
1398 unsignedcharmax_offset;
1399 unsignedcharhead, tail;
1400 unsignedshorttarget_mask;
1401 longflags;
1402 void *addr;
1403 intactual;
1404 inttarget, tcl;
1405 intscbptr;
1406 Scsi_Cmnd *cmd;
1407 #if 0
1408 staticint_count = 0;
1409 #endif1410
1411 p = (structaic7xxx_host *) aic7xxx_boards[irq]->hostdata;
1412 #ifdefAIC7XXX_SHARE_IRQS1413 /*1414 * Search for the host with a pending interrupt.1415 */1416 while ((p != NULL) && !(inb(INTSTAT(p->base)) & INT_PEND))
1417 {1418 p = (structaic7xxx_host *) p->next->hostdata;
1419 }1420 if (p == NULL)
1421 {1422 printk("aic7xxx_isr: Encountered spurious interrupt.\n");
1423 return;
1424 }1425 #endif1426 base = p->base;
1427 if (p->isr_count == 0xffffffff)
1428 {1429 p->isr_count = 0;
1430 }1431 else1432 {1433 p->isr_count = p->isr_count + 1;
1434 }1435 if ((p->a_scanned == 0) && (p->isr_count == 1))
1436 {1437 /* Allow for one interrupt when the card is enabled. */1438 return;
1439 }1440
1441 /*1442 * Handle all the interrupt sources - especially for SCSI1443 * interrupts, we won't get a second chance at them.1444 */1445 intstat = inb(INTSTAT(base));
1446
1447 if (intstat & BRKADRINT)
1448 {1449 inti;
1450 unsignedcharerrno = inb(ERROR(base));
1451
1452 printk("aic7xxx_isr: brkadrint (0x%x):\n", errno);
1453 for (i = 0; i < NUMBER(hard_error); i++)
1454 {1455 if (errno & hard_error[i].errno)
1456 {1457 printk(" %s\n", hard_error[i].errmesg);
1458 }1459 }1460
1461 panic("aic7xxx_isr: brkadrint, error = 0x%x, seqaddr = 0x%x\n",
1462 inb(ERROR(base)),
1463 inb(SEQADDR1(base)) << 8 | inb(SEQADDR0(base)));
1464 }1465
1466 if (intstat & SEQINT)
1467 {1468 /*1469 * Although the sequencer is paused immediately on1470 * a SEQINT, an interrupt for a SCSIINT or a CMDCMPLT1471 * condition will have unpaused the sequencer before1472 * this point.1473 */1474 PAUSE_SEQUENCER(p);
1475
1476 switch (intstat & SEQINT_MASK)
1477 {1478 caseBAD_PHASE:
1479 panic("aic7xxx_isr: unknown scsi bus phase\n");
1480
1481 caseSEND_REJECT:
1482 debug("aic7xxx_isr warning: issuing message reject, 1st byte 0x%x\n",
1483 inb(HA_REJBYTE(base)));
1484 break;
1485
1486 caseNO_IDENT:
1487 panic("aic7xxx_isr: reconnecting target %d at seqaddr 0x%x "
1488 "didn't issue IDENTIFY message\n",
1489 (inb(SELID(base)) >> 4) & 0x0F,
1490 (inb(SEQADDR1(base)) << 8) | inb(SEQADDR0(base)));
1491 break;
1492
1493 caseNO_MATCH:
1494 tcl = inb(SCBARRAY(base) + 1);
1495 target = (tcl >> 4) & 0x0F;
1496 /* Purposefully mask off the top bit of targets 8-15. */1497 target_mask = 0x01 << (target & 0x07);
1498
1499 debug("aic7xxx_isr: sequencer couldn't find match "
1500 "for reconnecting target %d, channel %d, lun %d - "
1501 "issuing ABORT\n", target, (tcl & 0x08) >> 3, tcl & 0x07);
1502 if (tcl & 0x88)
1503 {1504 /* Second channel stores its info in byte1505 * two of HA_ACTIVE1506 */1507 active = inb(HA_ACTIVE1(base));
1508 active = active & ~(target_mask);
1509 outb(active, HA_ACTIVE1(base));
1510 }1511 else1512 {1513 active = inb(HA_ACTIVE0(base));
1514 active = active & ~(target_mask);
1515 outb(active, HA_ACTIVE0(base));
1516 }1517 #ifdefAIC7XXX_USE_DMA1518 outb(SCB_NEEDDMA, SCBARRAY(base));
1519 #endif1520
1521 /*1522 * Check out why this use to be outb(0x80, CLRINT(base))1523 * clear the timeout1524 */1525 outb(CLRSELTIMEO, CLRSINT1(base));
1526 RESTART_SEQUENCER(p);
1527 break;
1528
1529 caseMSG_SDTR:
1530 /*1531 * Help the sequencer to translate the negotiated1532 * transfer rate. Transfer is 1/4 the period1533 * in ns as is returned by the sync negotiation1534 * message. So, we must multiply by four.1535 */1536 transfer = (inb(HA_ARG_1(base)) << 2);
1537 offset = inb(ACCUM(base));
1538 scsi_id = inb(SCSIID(base)) >> 0x04;
1539 if (inb(SBLKCTL(base)) & 0x08)
1540 {1541 scsi_id = scsi_id + 8; /* B channel */1542 }1543 target_mask = (0x01 << scsi_id);
1544 scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1545 /*1546 * The maximum offset for a wide device is 0x08; for a1547 * 8-bit bus device the maximum offset is 0x0f.1548 */1549 if (scratch & 0x80)
1550 {1551 max_offset = 0x08;
1552 }1553 else1554 {1555 max_offset = 0x0f;
1556 }1557 aic7xxx_scsirate(&rate, transfer, MIN(offset, max_offset), scsi_id);
1558 /*1559 * Preserve the wide transfer flag.1560 */1561 rate = rate | (scratch & 0x80);
1562 outb(rate, HA_TARG_SCRATCH(base) + scsi_id);
1563 outb(rate, SCSIRATE(base));
1564 if ((rate & 0xf) == 0)
1565 {/*1566 * The requested rate was so low that asynchronous transfers1567 * are faster (not to mention the controller won't support1568 * them), so we issue a reject to ensure we go to asynchronous1569 * transfers.1570 */1571 outb(SEND_REJ, HA_RETURN_1(base));
1572 }1573 else1574 {1575 /*1576 * See if we initiated Sync Negotiation1577 */1578 if (p->sdtr_pending & target_mask)
1579 {1580 /*1581 * Don't send an SDTR back to the target.1582 */1583 outb(0, HA_RETURN_1(base));
1584 }1585 else1586 {1587 /*1588 * Send our own SDTR in reply.1589 */1590 printk("Sending SDTR!!\n");
1591 outb(SEND_SDTR, HA_RETURN_1(base));
1592 }1593 }1594 /*1595 * Clear the flags.1596 */1597 p->needsdtr = p->needsdtr & ~target_mask;
1598 p->sdtr_pending = p->sdtr_pending & ~target_mask;
1599 break;
1600
1601 caseMSG_WDTR:
1602 {1603 bus_width = inb(ACCUM(base));
1604 scsi_id = inb(SCSIID(base)) >> 0x04;
1605 if (inb(SBLKCTL(base)) & 0x08)
1606 {1607 scsi_id = scsi_id + 8; /* B channel */1608 }1609 printk("Received MSG_WDTR, scsi_id = %d, "
1610 "needwdtr = 0x%x\n", scsi_id, p->needwdtr);
1611 scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1612
1613 target_mask = (0x01 << scsi_id);
1614 if (p->wdtr_pending & target_mask)
1615 {1616 /*1617 * Don't send an WDTR back to the target, since we asked first.1618 */1619 outb(0, HA_RETURN_1(base));
1620 switch (bus_width)
1621 {1622 caseBUS_8_BIT:
1623 scratch = scratch & 0x7F;
1624 break;
1625
1626 caseBUS_16_BIT:
1627 printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1628 scsi_id);
1629 scratch = scratch | 0x80;
1630 break;
1631 }1632 }1633 else1634 {1635 /*1636 * Send our own WDTR in reply.1637 */1638 printk("Will send WDTR!!\n");
1639 switch (bus_width)
1640 {1641 caseBUS_8_BIT:
1642 scratch = scratch & 0x7F;
1643 break;
1644
1645 caseBUS_32_BIT:
1646 /* Negotiate 16 bits. */1647 bus_width = BUS_16_BIT;
1648 /* Yes, we mean to fall thru here */1649
1650 caseBUS_16_BIT:
1651 printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1652 scsi_id);
1653 scratch = scratch | 0x80;
1654 break;
1655 }1656 outb(bus_width | SEND_WDTR, HA_RETURN_1(base));
1657 }1658 p->needwdtr = p->needwdtr & ~target_mask;
1659 p->wdtr_pending = p->wdtr_pending & ~target_mask;
1660 outb(scratch, HA_TARG_SCRATCH(base) + scsi_id);
1661 outb(scratch, SCSIRATE(base));
1662 break;
1663 }1664
1665 caseMSG_REJECT:
1666 {1667 /*1668 * What we care about here is if we had an1669 * outstanding SDTR or WDTR message for this1670 * target. If we did, this is a signal that1671 * the target is refusing negotiation.1672 */1673
1674 unsignedchartarg_scratch, scsi_id;
1675 unsignedshortmask;
1676
1677 scsi_id = inb(SCSIID(base)) >> 0x04;
1678 if (inb(SBLKCTL(base)) & 0x08)
1679 {1680 scsi_id = scsi_id + 8;
1681 }1682
1683 mask = (0x01 << scsi_id);
1684
1685 targ_scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1686
1687 if (p->wdtr_pending & mask)
1688 {1689 /*1690 * note 8bit xfers and clear flag1691 */1692 targ_scratch = targ_scratch & 0x7F;
1693 p->needwdtr = p->needwdtr & ~mask;
1694 p->wdtr_pending = p->wdtr_pending & ~mask;
1695 outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1696 printk("aic7xxx: target %d refusing WIDE negotiation. Using "
1697 "8 bit transfers\n", scsi_id);
1698 }1699 else1700 {1701 if (p->sdtr_pending & mask)
1702 {1703 /*1704 * note asynch xfers and clear flag1705 */1706 targ_scratch = targ_scratch & 0xF0;
1707 p->needsdtr = p->needsdtr & ~mask;
1708 p->sdtr_pending = p->sdtr_pending & ~mask;
1709 outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1710 printk("aic7xxx: target %d refusing syncronous negotiation. Using "
1711 "asyncronous transfers\n", scsi_id);
1712 }1713 /*1714 * Otherwise, we ignore it.1715 */1716 }1717 outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1718 outb(targ_scratch, SCSIRATE(base));
1719 break;
1720 }1721
1722 caseBAD_STATUS:
1723 scsi_id = inb(SCSIID(base)) >> 0x04;
1724 scbptr = inb(SCBPTR(base));
1725 scb = &(p->scb_array[scbptr]);
1726 outb(0, HA_RETURN_1(base)); /* CHECK_CONDITION may change this */1727 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1728 {1729 printk("aic7xxx_isr: referenced scb not valid "
1730 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1731 intstat, scbptr, scb->state, (unsignedint) scb->cmd);
1732 }1733 else1734 {1735 cmd = scb->cmd;
1736 aic7xxx_getscb(base, scb);
1737 aic7xxx_status(cmd) = scb->target_status;
1738
1739 cmd->result = cmd->result | scb->target_status;
1740
1741 /*1742 * This test is just here for debugging purposes.1743 * It will go away when the timeout problem is resolved.1744 */1745 switch (status_byte(scb->target_status))
1746 {1747 caseGOOD:
1748 break;
1749
1750 caseCHECK_CONDITION:
1751 if ((aic7xxx_error(cmd) == 0) && !(cmd->flags & WAS_SENSE))
1752 {1753 void *req_buf;
1754 #ifndefAIC7XXX_USE_SG1755 unsignedintreq_buflen;
1756 #endif1757
1758 /* Update the timeout for the SCSI command. */1759 /* update_timeout(cmd, SENSE_TIMEOUT); */1760
1761 /* Send a sense command to the requesting target. */1762 cmd->flags = cmd->flags | WAS_SENSE;
1763 memcpy((void *) scb->sense_cmd, (void *) generic_sense,
1764 sizeof(generic_sense));
1765
1766 scb->sense_cmd[1] = cmd->lun << 5;
1767 scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
1768
1769 #ifdefAIC7XXX_USE_SG1770 scb->sense_sg.address = (char *) &cmd->sense_buffer;
1771 scb->sense_sg.length = sizeof(cmd->sense_buffer);
1772 req_buf = &scb->sense_sg;
1773 #else1774 req_buf = &cmd->sense_buffer;
1775 req_buflen = sizeof(cmd->sense_buffer);
1776 #endif1777 cmd->cmd_len = COMMAND_SIZE(cmd->cmnd[0]);
1778 memset(scb, 0, SCB_DOWNLOAD_SIZE);
1779 scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
1780 ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
1781 addr = scb->sense_cmd;
1782 scb->SCSI_cmd_length = COMMAND_SIZE(scb->sense_cmd[0]);
1783 memcpy(scb->SCSI_cmd_pointer, &addr,
1784 sizeof(scb->SCSI_cmd_pointer));
1785 #ifdefAIC7XXX_USE_SG1786 scb->SG_segment_count = 1;
1787 memcpy (scb->SG_list_pointer, &req_buf,
1788 sizeof(scb->SG_list_pointer));
1789 #else1790 scb->SG_segment_count = 0;
1791 memcpy (scb->data_pointer, &req_buf,
1792 sizeof(scb->data_pointer));
1793 memcpy (scb->data_count, &req_buflen, 3);
1794 #endif1795
1796 outb(SCBAUTO, SCBCNT(base));
1797 asmvolatile("cld\n\t"
1798 "rep\n\t"
1799 "outsb"
1800 : /* no output */1801 :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1802 :"si", "cx", "dx");
1803 outb(0, SCBCNT(base));
1804 outb(SCB_LIST_NULL, (SCBARRAY(base) + 30));
1805
1806 /*1807 * Add this SCB to the "waiting for selection" list.1808 */1809 head = inb(WAITING_SCBH(base));
1810 tail = inb(WAITING_SCBT(base));
1811 if (head & SCB_LIST_NULL)
1812 {/* list is empty */1813 head = scb->position;
1814 tail = SCB_LIST_NULL;
1815 }1816 else1817 {1818 if (tail & SCB_LIST_NULL)
1819 {/* list has one element */1820 tail = scb->position;
1821 outb(head, SCBPTR(base));
1822 outb(tail, (SCBARRAY(base) + 30));
1823 }1824 else1825 {/* list has more than one element */1826 outb(tail, SCBPTR(base));
1827 tail = scb->position;
1828 outb(tail, (SCBARRAY(base) + 30));
1829 }1830 }1831 outb(head, WAITING_SCBH(base));
1832 outb(tail, WAITING_SCBT(base));
1833 outb(SEND_SENSE, HA_RETURN_1(base));
1834 }/* first time sense, no errors */1835 else1836 {1837 /*1838 * Indicate that we asked for sense, have the sequencer do1839 * a normal command complete, and have the scsi driver handle1840 * this condition.1841 */1842 cmd->flags = cmd->flags | ASKED_FOR_SENSE;
1843 }1844 break;
1845
1846 caseBUSY:
1847 printk("aic7xxx_isr: Target busy\n");
1848 if (!aic7xxx_error(cmd))
1849 {1850 aic7xxx_error(cmd) = DID_BUS_BUSY;
1851 }1852 break;
1853
1854 caseQUEUE_FULL:
1855 printk("aic7xxx_isr: Queue full\n");
1856 if (!aic7xxx_error(cmd))
1857 {1858 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1859 }1860 break;
1861
1862 default:
1863 printk("aic7xxx_isr: Unexpected target status 0x%x\n",
1864 scb->target_status);
1865 if (!aic7xxx_error(cmd))
1866 {1867 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1868 }1869 break;
1870 }/* end switch */1871 }/* end else of */1872 break;
1873
1874 caseRESIDUAL:
1875 scbptr = inb(SCBPTR(base));
1876 scb = &(p->scb_array[scbptr]);
1877 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1878 {1879 printk("aic7xxx_isr: referenced scb not valid "
1880 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1881 intstat, scbptr, scb->state, (unsignedint) scb->cmd);
1882 }1883 else1884 {1885 cmd = scb->cmd;
1886 /*1887 * Don't destroy valid residual information with1888 * residual coming from a check sense operation.1889 */1890 if (!(cmd->flags & WAS_SENSE))
1891 {1892 /*1893 * We had an underflow. At this time, there's only1894 * one other driver that bothers to check for this,1895 * and cmd->underflow seems to be set rather half-1896 * heartedly in the higher-level SCSI code.1897 */1898 actual = aic7xxx_length(cmd, scb->residual_SG_segment_count);
1899
1900 actual -= ((inb(SCBARRAY(base + 17)) << 16) |
1901 (inb(SCBARRAY(base + 16)) << 8) |
1902 inb(SCBARRAY(base + 15)));
1903
1904 if (actual < cmd->underflow)
1905 {1906 printk("aic7xxx: target %d underflow - "
1907 "wanted (at least) %u, got %u\n",
1908 cmd->target, cmd->underflow, actual);
1909
1910 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1911 aic7xxx_status(cmd) = scb->target_status;
1912 }1913 }1914 }1915 break;
1916
1917 caseABORT_TAG:
1918 scbptr = inb(SCBPTR(base));
1919 scb = &(p->scb_array[scbptr]);
1920 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1921 {1922 printk("aic7xxx_isr: referenced scb not valid "
1923 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1924 intstat, scbptr, scb->state, (unsignedint) scb->cmd);
1925 }1926 else1927 {1928 cmd = scb->cmd;
1929 /*1930 * We didn't recieve a valid tag back from the target1931 * on a reconnect.1932 */1933 printk("aic7xxx_isr: invalid tag recieved on channel %c "
1934 "target %d, lun %d -- sending ABORT_TAG\n",
1935 (cmd->channel & 0x01) ? 'B':'A',
1936 cmd->target, cmd->lun & 0x07);
1937 /*1938 * This is a critical section, since we don't want the1939 * queue routine mucking with the host data.1940 */1941 save_flags(flags);
1942 cli();
1943
1944 /*1945 * Process the command after marking the scb as free1946 * and adding it to the free list.1947 */1948 scb->state = SCB_FREE;
1949 scb->cmd = NULL;
1950 scb->next = p->free_scb; /* preserve next pointer */1951 p->free_scb = scb; /* add at head of list */1952
1953 restore_flags (flags);
1954 cmd->result = (DID_RETRY_COMMAND << 16);
1955 cmd->scsi_done(cmd);
1956 }1957 break;
1958
1959 caseAWAITING_MSG:
1960 scbptr = inb(SCBPTR(base));
1961 scb = &(p->scb_array[scbptr]);
1962 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1963 {1964 printk("aic7xxx_isr: referenced scb not valid "
1965 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1966 intstat, scbptr, scb->state, (unsignedint) scb->cmd);
1967 }1968 else1969 {1970 /*1971 * This SCB had a zero length command, informing the sequencer1972 * that we wanted to send a special message to this target.1973 * We only do this for BUS_DEVICE_RESET messages currently.1974 */1975 if (scb->state & SCB_DEVICE_RESET)
1976 {1977 outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
1978 outb(1, HA_MSG_LEN(base));
1979 }1980 else1981 {1982 panic ("aic7xxx_isr: AWAITING_SCB for an SCB that does "
1983 "not have a waiting message");
1984 }1985 }1986 break;
1987
1988 default: /* unknown */1989 debug("aic7xxx_isr: seqint, intstat = 0x%x, scsisigi = 0x%x\n",
1990 intstat, inb(SCSISIGI(base)));
1991 break;
1992 }1993 outb(CLRSEQINT, CLRINT(base));
1994 UNPAUSE_SEQUENCER(p);
1995 }1996
1997 if (intstat & SCSIINT)
1998 {1999 intstatus = inb(SSTAT1(base));
2000
2001 scbptr = inb(SCBPTR(base));
2002 scb = &p->scb_array[scbptr];
2003 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2004 {2005 printk("aic7xxx_isr: no command for scb (scsiint)\n");
2006 /*2007 * Turn off the interrupt and set status2008 * to zero, so that it falls through the2009 * reset of the SCSIINT code.2010 */2011 outb(status, CLRSINT1(base));
2012 UNPAUSE_SEQUENCER(p);
2013 outb(CLRSCSIINT, CLRINT(base));
2014 status = 0;
2015 scb = NULL;
2016 }2017 else2018 {2019 cmd = scb->cmd;
2020
2021 /*2022 * Only the SCSI Status 1 register has information2023 * about exceptional conditions that we'd have a2024 * SCSIINT about; anything in SSTAT0 will be handled2025 * by the sequencer. Note that there can be multiple2026 * bits set.2027 */2028 if (status & SELTO)
2029 {2030 unsignedchartarget_mask = (1 << (cmd->target & 0x07));
2031 unsignedcharwaiting;
2032
2033 /*2034 * Hardware selection timer has expired. Turn2035 * off SCSI selection sequence.2036 */2037 outb(ENRSELI, SCSISEQ(base));
2038 cmd->result = (DID_TIME_OUT << 16);
2039 /*2040 * Clear an pending messages for the timed out2041 * target and mark the target as free.2042 */2043 ha_flags = inb(HA_FLAGS(base));
2044 outb(ha_flags & ~ACTIVE_MSG, HA_FLAGS(base));
2045
2046 if (scb->target_channel_lun & 0x88)
2047 {2048 active = inb(HA_ACTIVE1(base));
2049 active = active & ~(target_mask);
2050 outb(active, HA_ACTIVE1(base));
2051 }2052 else2053 {2054 active = inb(HA_ACTIVE0(base));
2055 active = active & ~(target_mask);
2056 outb(active, HA_ACTIVE0(base));
2057 }2058
2059 #ifdefAIC7XXX_USE_DMA2060 outb(SCB_NEEDDMA, SCBARRAY(base));
2061 #endif2062
2063 /*2064 * Shut off the offending interrupt sources, reset2065 * the sequencer address to zero and unpause it,2066 * then call the high-level SCSI completion routine.2067 *2068 * WARNING! This is a magic sequence! After many2069 * hours of guesswork, turning off the SCSI interrupts2070 * in CLRSINT? does NOT clear the SCSIINT bit in2071 * INTSTAT. By writing to the (undocumented, unused2072 * according to the AIC-7770 manual) third bit of2073 * CLRINT, you can clear INTSTAT. But, if you do it2074 * while the sequencer is paused, you get a BRKADRINT2075 * with an Illegal Host Address status, so the2076 * sequencer has to be restarted first.2077 */2078 outb(CLRSELTIMEO, CLRSINT1(base));
2079
2080 outb(CLRSCSIINT, CLRINT(base));
2081
2082 /* Shift the waiting for selection queue forward */2083 waiting = inb(WAITING_SCBH(base));
2084 outb(waiting, SCBPTR(base));
2085 waiting = inb(SCBARRAY(base) + 30);
2086 outb(waiting, WAITING_SCBH(base));
2087
2088 RESTART_SEQUENCER(p);
2089 /*2090 * This is a critical section, since we don't want the2091 * queue routine mucking with the host data.2092 */2093 save_flags(flags);
2094 cli();
2095
2096 /*2097 * Process the command after marking the scb as free2098 * and adding it to the free list.2099 */2100 scb->state = SCB_FREE;
2101 scb->cmd = NULL;
2102 scb->next = p->free_scb; /* preserve next pointer */2103 p->free_scb = scb; /* add at head of list */2104
2105 restore_flags(flags);
2106
2107 cmd->scsi_done(cmd);
2108 #if 0
2109 printk("aic7xxx_isr: SELTO scb(%d) state(%x), cmd(%x)\n",
2110 scb->position, scb->state, (unsignedint) scb->cmd);
2111 #endif2112 }2113 else2114 {2115 if (status & SCSIPERR)
2116 {2117 /*2118 * A parity error has occurred during a data2119 * transfer phase. Flag it and continue.2120 */2121 printk("aic7xxx: parity error on target %d, "
2122 "channel %d, lun %d\n",
2123 cmd->target,
2124 cmd->channel & 0x01,
2125 cmd->lun & 0x07);
2126 aic7xxx_error(cmd) = DID_PARITY;
2127
2128 /*2129 * Clear interrupt and resume as above.2130 */2131 outb(CLRSCSIPERR, CLRSINT1(base));
2132 UNPAUSE_SEQUENCER(p);
2133
2134 outb(CLRSCSIINT, CLRINT(base));
2135 scb = NULL;
2136 }2137 else2138 {2139 if (! (status & BUSFREE))
2140 {2141 /*2142 * We don't know what's going on. Turn off the2143 * interrupt source and try to continue.2144 */2145 printk("aic7xxx_isr: sstat1 = 0x%x\n", status);
2146 outb(status, CLRSINT1(base));
2147 UNPAUSE_SEQUENCER(p);
2148 outb(CLRSCSIINT, CLRINT(base));
2149 scb = NULL;
2150 }2151 }2152 }2153 }/* else */2154 }2155
2156 if (intstat & CMDCMPLT)
2157 {2158 intcomplete;
2159
2160 /*2161 * The sequencer will continue running when it2162 * issues this interrupt. There may be >1 commands2163 * finished, so loop until we've processed them all.2164 */2165 do{2166 complete = inb(QOUTFIFO(base));
2167
2168 scb = &(p->scb_array[complete]);
2169 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2170 {2171 printk("aic7xxx warning: "
2172 "no command for scb %d (cmdcmplt)\n"
2173 "QOUTCNT = %d, SCB state = 0x%x, CMD = 0x%x\n",
2174 complete, inb(QOUTFIFO(base)),
2175 scb->state, (unsignedint) scb->cmd);
2176 outb(CLRCMDINT, CLRINT(base));
2177 continue;
2178 }2179 cmd = scb->cmd;
2180
2181 cmd->result = (aic7xxx_error(cmd) << 16) | aic7xxx_status(cmd);
2182 if ((cmd->flags & WAS_SENSE) && !(cmd->flags & ASKED_FOR_SENSE))
2183 {/* Got sense information. */2184 cmd->flags = cmd->flags & ASKED_FOR_SENSE;
2185 }2186 #if 0
2187 printk("aic7xxx_intr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2188 scb->state, (unsignedint) scb->cmd, (unsignedint) p->free_scb);
2189 #endif2190 /*2191 * This is a critical section, since we don't want the2192 * queue routine mucking with the host data.2193 */2194 save_flags(flags);
2195 cli();
2196
2197 scb->state = SCB_FREE;
2198 scb->next = p->free_scb;
2199 scb->cmd = NULL;
2200 p->free_scb = &(p->scb_array[scb->position]);
2201
2202 restore_flags(flags);
2203 #if 0
2204 if (scb != &p->scb_array[scb->position])
2205 {2206 printk("aic7xxx_isr: (complete) address mismatch, pos %d\n", scb->position);
2207 }2208 printk("aic7xxx_isr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2209 scb->state, (unsignedint) scb->cmd, (unsignedint) p->free_scb);
2210 #endif2211
2212 cmd->scsi_done(cmd);
2213
2214 /*2215 * Clear interrupt status before checking2216 * the output queue again. This eliminates2217 * a race condition whereby a command could2218 * complete between the queue poll and the2219 * interrupt clearing, so notification of the2220 * command being complete never made it back2221 * up to the kernel.2222 */2223 outb(CLRCMDINT, CLRINT(base));
2224 }while (inb(QOUTCNT(base)));
2225 }2226 }2227
2228 /*+F*************************************************************************2229 * Function:2230 * aic7xxx_probe2231 *2232 * Description:2233 * Probing for EISA boards: it looks like the first two bytes2234 * are a manufacturer code - three characters, five bits each:2235 *2236 * BYTE 0 BYTE 1 BYTE 2 BYTE 32237 * ?1111122 22233333 PPPPPPPP RRRRRRRR2238 *2239 * The characters are baselined off ASCII '@', so add that value2240 * to each to get the real ASCII code for it. The next two bytes2241 * appear to be a product and revision number, probably vendor-2242 * specific. This is what is being searched for at each port,2243 * and what should probably correspond to the ID= field in the2244 * ECU's .cfg file for the card - if your card is not detected,2245 * make sure your signature is listed in the array.2246 *2247 * The fourth byte's lowest bit seems to be an enabled/disabled2248 * flag (rest of the bits are reserved?).2249 *-F*************************************************************************/2250 staticaha_type2251 aic7xxx_probe(intslot, intbase)
/* */2252 {2253 inti;
2254 unsignedcharbuf[4];
2255
2256 staticstruct{2257 intn;
2258 unsignedcharsignature[sizeof(buf)];
2259 aha_typetype;
2260 }AIC7xxx[] = {2261 { 4, { 0x04, 0x90, 0x77, 0x71 }, AIC_274x}, /* host adapter 274x */2262 { 4, { 0x04, 0x90, 0x77, 0x70 }, AIC_274x}, /* motherboard 274x */2263 { 4, { 0x04, 0x90, 0x77, 0x56 }, AIC_284x}, /* 284x, BIOS enabled */2264 { 4, { 0x04, 0x90, 0x77, 0x57 }, AIC_284x}/* 284x, BIOS disabled */2265 };
2266
2267 /*2268 * The VL-bus cards need to be primed by2269 * writing before a signature check.2270 */2271 for (i = 0; i < sizeof(buf); i++)
2272 {2273 outb(0x80 + i, base);
2274 buf[i] = inb(base + i);
2275 }2276
2277 for (i = 0; i < NUMBER(AIC7xxx); i++)
2278 {2279 /*2280 * Signature match on enabled card?2281 */2282 if (!memcmp(buf, AIC7xxx[i].signature, AIC7xxx[i].n))
2283 {2284 if (inb(base + 4) & 1)
2285 {2286 return(AIC7xxx[i].type);
2287 }2288
2289 printk("aic7xxx disabled at slot %d, ignored\n", slot);
2290 }2291 }2292
2293 return(AIC_NONE);
2294 }2295
2296 /*+F*************************************************************************2297 * Function:2298 * read_seeprom2299 *2300 * Description:2301 * Reads the serial EEPROM and returns 1 if successful and 0 if2302 * not successful.2303 *2304 * The instruction set of the 93C46 chip is as follows:2305 *2306 * Start OP2307 * Function Bit Code Address Data Description2308 * -------------------------------------------------------------------2309 * READ 1 10 A5 - A0 Reads data stored in memory,2310 * starting at specified address2311 * EWEN 1 00 11XXXX Write enable must preceed2312 * all programming modes2313 * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A02314 * WRITE 1 01 A5 - A0 D15 - D0 Writes register2315 * ERAL 1 00 10XXXX Erase all registers2316 * WRAL 1 00 01XXXX D15 - D0 Writes to all registers2317 * EWDS 1 00 00XXXX Disables all programming2318 * instructions2319 * *Note: A value of X for address is a don't care condition.2320 *2321 * The 93C46 has a four wire interface: clock, chip select, data in, and2322 * data out. In order to perform one of the above functions, you need2323 * to enable the chip select for a clock period (typically a minimum of2324 * 1 usec, with the clock high and low a minimum of 750 and 250 nsec2325 * respectively. While the chip select remains high, you can clock in2326 * the instructions (above) starting with the start bit, followed by the2327 * OP code, Address, and Data (if needed). For the READ instruction, the2328 * requested 16-bit register contents is read from the data out line but2329 * is preceded by an initial zero (leading 0, followed by 16-bits, MSB2330 * first). The clock cycling from low to high initiates the next data2331 * bit to be sent from the chip.2332 *2333 * The 7870 interface to the 93C46 serial EEPROM is through the SEECTL2334 * register. After successful arbitration for the memory port, the2335 * SEECS bit of the SEECTL register is connected to the chip select.2336 * The SEECK, SEEDO, and SEEDI are connected to the clock, data out,2337 * and data in lines respectively. The SEERDY bit of SEECTL is useful2338 * in that it gives us an 800 nsec timer. After a write to the SEECTL2339 * register, the SEERDY goes high 800 nsec later. The one exception2340 * to this is when we first request access to the memory port. The2341 * SEERDY goes high to signify that access has been granted and, for2342 * this case, has no implied timing.2343 *2344 *-F*************************************************************************/2345 staticint2346 read_seeprom(intbase, structseeprom_config *sc)
/* */2347 {2348 inti = 0, k = 0;
2349 unsignedlongtimeout;
2350 unsignedchartemp;
2351 unsignedshortchecksum = 0;
2352 unsignedshort *seeprom = (unsignedshort *) sc;
2353 structseeprom_cmd{2354 unsignedcharlen;
2355 unsignedcharbits[3];
2356 };
2357 structseeprom_cmdseeprom_read = {3, {1, 1, 0}};
2358
2359 #defineCLOCK_PULSE(p) \
2360 while ((inb(SEECTL(base)) & SEERDY) == 0) \
2361 { \
2362 ; /* Do nothing */ \
2363 }2364
2365 /*2366 * Request access of the memory port. When access is2367 * granted, SEERDY will go high. We use a 1 second2368 * timeout which should be near 1 second more than2369 * is needed. Reason: after the 7870 chip reset, there2370 * should be no contention.2371 */2372 outb(SEEMS, SEECTL(base));
2373 timeout = jiffies + 100; /* 1 second timeout */2374 while ((jiffies < timeout) && ((inb(SEECTL(base)) & SEERDY) == 0))
2375 {2376 ; /* Do nothing! Wait for access to be granted. */2377 }2378 if ((inb(SEECTL(base)) & SEERDY) == 0)
2379 {2380 outb (0, SEECTL(base));
2381 return (0);
2382 }2383
2384 /*2385 * Read the first 32 registers of the seeprom. For the 7870,2386 * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers2387 * but only the first 32 are used by Adaptec BIOS. The loop2388 * will range from 0 to 31.2389 */2390 for (k = 0; k < (sizeof(*sc) / 2); k = k + 1)
2391 {2392 /* Send chip select for one clock cycle. */2393 outb(SEEMS | SEECK | SEECS, SEECTL(base));
2394 CLOCK_PULSE(base);
2395
2396 /*2397 * Now we're ready to send the read command followed by the2398 * address of the 16-bit register we want to read.2399 */2400 for (i = 0; i < seeprom_read.len; i = i + 1)
2401 {2402 temp = SEEMS | SEECS | (seeprom_read.bits[i] << 1);
2403 outb(temp, SEECTL(base));
2404 CLOCK_PULSE(base);
2405 temp = temp ^ SEECK;
2406 outb(temp, SEECTL(base));
2407 CLOCK_PULSE(base);
2408 }2409 /* Send the 6 bit address (MSB first, LSB last). */2410 for (i = 5; i >= 0; i = i - 1)
2411 {2412 temp = k;
2413 temp = (temp >> i) & 1; /* Mask out all but lower bit. */2414 temp = SEEMS | SEECS | (temp << 1);
2415 outb(temp, SEECTL(base));
2416 CLOCK_PULSE(base);
2417 temp = temp ^ SEECK;
2418 outb(temp, SEECTL(base));
2419 CLOCK_PULSE(base);
2420 }2421
2422 /*2423 * Now read the 16 bit register. An initial 0 precedes the2424 * register contents which begins with bit 15 (MSB) and ends2425 * with bit 0 (LSB). The initial 0 will be shifted off the2426 * top of our word as we let the loop run from 0 to 16.2427 */2428 for (i = 0; i <= 16; i = i + 1)
2429 {2430 temp = SEEMS | SEECS;
2431 outb(temp, SEECTL(base));
2432 CLOCK_PULSE(base);
2433 temp = temp ^ SEECK;
2434 seeprom[k] = (seeprom[k] << 1) | (inb(SEECTL(base)) & SEEDI);
2435 outb(temp, SEECTL(base));
2436 CLOCK_PULSE(base);
2437 }2438
2439 /*2440 * The serial EEPROM has a checksum in the last word. Keep a2441 * running checksum for all words read except for the last2442 * word. We'll verify the checksum after all words have been2443 * read.2444 */2445 if (k < (sizeof(*sc) / 2) - 1)
2446 {2447 checksum = checksum + seeprom[k];
2448 }2449
2450 /* Reset the chip select for the next command cycle. */2451 outb(SEEMS, SEECTL(base));
2452 CLOCK_PULSE(base);
2453 outb(SEEMS | SEECK, SEECTL(base));
2454 CLOCK_PULSE(base);
2455 outb(SEEMS, SEECTL(base));
2456 CLOCK_PULSE(base);
2457 }2458
2459 if (checksum != sc->checksum)
2460 {2461 printk ("aic7xxx : SEEPROM checksum error, ignoring SEEPROM settings.\n");
2462 return (0);
2463 }2464
2465 #if 0
2466 printk ("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
2467 printk ("Serial EEPROM:");
2468 for (k = 0; k < (sizeof(*sc) / 2); k = k + 1)
2469 {2470 if (((k % 8) == 0) && (k != 0))
2471 {2472 printk ("\n ");
2473 }2474 printk (" 0x%x", seeprom[k]);
2475 }2476 printk ("\n");
2477 #endif2478
2479 /* Release access to the memory port and the serial EEPROM. */2480 outb(0, SEECTL(base));
2481 return (1);
2482 }2483
2484 /*+F*************************************************************************2485 * Function:2486 * detect_maxscb2487 *2488 * Description:2489 * Return the maximum number of SCB's allowed for a given controller.2490 *-F*************************************************************************/2491 staticint2492 detect_maxscb(aha_typetype, intbase)
/* */2493 {2494 unsignedcharsblkctl_reg;
2495 intmaxscb = 0;
2496
2497 switch (type)
2498 {2499 caseAIC_274x:
2500 caseAIC_284x:
2501 /*2502 * Check for Rev C or E boards. Rev E boards can supposedly have2503 * more than 4 SCBs, while the Rev C boards are limited to 4 SCBs.2504 * Until we know how to access more than 4 SCBs for the Rev E chips,2505 * we limit them, along with the Rev C chips, to 4 SCBs.2506 *2507 * The Rev E boards have a read/write autoflush bit in the2508 * SBLKCTL registor, while in the Rev C boards it is read only.2509 */2510 sblkctl_reg = inb(SBLKCTL(base)) ^ AUTOFLUSHDIS;
2511 outb(sblkctl_reg, SBLKCTL(base));
2512 if (inb(SBLKCTL(base)) == sblkctl_reg)
2513 {/* We detected a Rev E board. */2514 printk("aic7770: Rev E and subsequent; using 4 SCB's\n");
2515 outb(sblkctl_reg ^ AUTOFLUSHDIS, SBLKCTL(base));
2516 maxscb = 4;
2517 }2518 else2519 {2520 printk("aic7770: Rev C and previous; using 4 SCB's\n");
2521 maxscb = 4;
2522 }2523 break;
2524
2525 caseAIC_7850:
2526 maxscb = 3;
2527 break;
2528
2529 caseAIC_7870:
2530 maxscb = 16;
2531 break;
2532
2533 caseAIC_7872:
2534 /*2535 * Really has 255, but we'll wait to verify that we access2536 * them the same way and do not have to set the card to2537 * use the memory port to access external SCB RAM.2538 */2539 maxscb = 16;
2540 break;
2541
2542 caseAIC_NONE:
2543 /*2544 * This should never happen... But just in case.2545 */2546 break;
2547 }2548
2549 return(maxscb);
2550 }2551
2552 /*+F*************************************************************************2553 * Function:2554 * aic7xxx_register2555 *2556 * Description:2557 * Register a Adaptec aic7xxx chip SCSI controller with the kernel.2558 *-F*************************************************************************/2559 staticint2560 aic7xxx_register(Scsi_Host_Template *template, aha_typetype,
/* */2561 intbase, unsignedcharirq)
2562 {2563 staticchar * board_name[] = {"", "274x", "284x", "7870", "7850", "7872"};
2564 inti;
2565 unsignedcharsblkctl;
2566 intmax_targets;
2567 intfound = 1;
2568 unsignedchartarget_settings;
2569 unsignedcharscsi_conf;
2570 inthave_seeprom = 0;
2571 structScsi_Host *host;
2572 structaic7xxx_host *p;
2573 structaic7xxx_host_configconfig;
2574 structseeprom_configsc;
2575
2576 config.type = type;
2577 config.base = base;
2578 config.irq = irq;
2579 config.parity = AIC_UNKNOWN;
2580 config.low_term = AIC_UNKNOWN;
2581 config.high_term = AIC_UNKNOWN;
2582 config.busrtime = 0;
2583
2584 /*2585 * Lock out other contenders for our i/o space.2586 */2587 request_region(MINREG(base), MAXREG(base) - MINREG(base), "aic7xxx");
2588
2589 switch (type)
2590 {2591 caseAIC_274x:
2592 #if 1
2593 printk("aha274x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2594 #endif2595 /*2596 * For some 274x boards, we must clear the CHIPRST bit2597 * and pause the sequencer. For some reason, this makes2598 * the driver work. For 284x boards, we give it a2599 * CHIPRST just like the 294x boards.2600 *2601 * Use the BIOS settings to determine the interrupt2602 * trigger type (level or edge) and use this value2603 * for pausing and unpausing the sequencer.2604 */2605 config.unpause = (inb(HCNTRL(config.base)) & IRQMS) | INTEN;
2606 config.pause = config.unpause | PAUSE;
2607 config.extended = aic7xxx_extended;
2608
2609 /*2610 * I don't think we need to kick the reset again, the initial probe2611 * does a reset, it seems that this is kicking a dead horse here.2612 * So... I will try to just verify that the chip has come out of the2613 * reset state and continue the same as the 284x.2614 * In the Calgary version of the driver:2615 * 1) Chip Reset2616 * 2) Set unpause to IRQMS | INTEN2617 * 3) If an interrupt occured without any commands queued, the2618 * unpause was set to just INTEN2619 * I changed the initial reset code to just mask in the CHIPRST bit2620 * and try to leave the other settings alone.2621 *2622 * I don't think we need the warning about chip reset not being clear.2623 * On both my test machines (2842 & 2940), they work just fine with a2624 * HCNTRL() of 0x5 (PAUSE | CHIPRST). Notice though, the 274x also2625 * adds the INTEN flag, where neither the 284x or 294x do.2626 */2627 outb(config.pause | CHIPRST, HCNTRL(config.base));
2628 aic7xxx_delay(1);
2629 if (inb(HCNTRL(config.base)) & CHIPRST)
2630 {2631 printk("aic7xxx_register: Chip reset not cleared; clearing manually.\n");
2632 }2633 outb(config.pause, HCNTRL(config.base));
2634
2635 /*2636 * Just to be on the safe side with the 274x, we will re-read the irq2637 * since there was some issue about reseting the board.2638 */2639 config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2640 config.busrtime = inb(HA_SCSICONF(config.base)) & 0x3C;
2641
2642 /*2643 * A reminder until this can be detected automatically.2644 */2645 printk("aha274x: extended translation %sabled\n",
2646 config.extended ? "en" : "dis");
2647 break;
2648
2649 caseAIC_284x:
2650 #if 1
2651 printk("aha284x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2652 #endif2653 outb(CHIPRST, HCNTRL(config.base));
2654 config.unpause = UNPAUSE_284X;
2655 config.pause = REQ_PAUSE; /* DWG would like to be like the rest */2656 config.extended = aic7xxx_extended;
2657 config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2658
2659 /*2660 * A reminder until this can be detected automatically.2661 */2662 printk("aha284x: extended translation %sabled\n",
2663 config.extended ? "en" : "dis");
2664 break;
2665
2666 caseAIC_7850:
2667 caseAIC_7870:
2668 caseAIC_7872:
2669 #if 1
2670 printk("aic%s hcntrl=0x%x\n", board_name[type], inb(HCNTRL(config.base)));
2671 #endif2672
2673 outb(CHIPRST, HCNTRL(config.base));
2674 config.unpause = UNPAUSE_294X;
2675 config.pause = config.unpause | PAUSE;
2676 config.extended = aic7xxx_extended;
2677 config.scsi_id = 7;
2678
2679 printk ("aic78xx: Reading SEEPROM... ");
2680 have_seeprom = read_seeprom(base, &sc);
2681 if (! have_seeprom)
2682 {2683 printk ("Unable to read SEEPROM\n");
2684 }2685 else2686 {2687 printk ("done\n");
2688 config.extended = (sc.bios_control & CFEXTEND) >> 7;
2689 config.scsi_id = (sc.brtime_id & CFSCSIID);
2690 config.parity = (sc.adapter_control & CFSPARITY) ?
2691 AIC_ENABLED : AIC_DISABLED;
2692 config.low_term = (sc.adapter_control & CFSTERM) ?
2693 AIC_ENABLED : AIC_DISABLED;
2694 config.high_term = (sc.adapter_control & CFWSTERM) ?
2695 AIC_ENABLED : AIC_DISABLED;
2696 config.busrtime = (sc.brtime_id & CFBRTIME) >> 8;
2697 }2698
2699 /*2700 * XXX - force data fifo threshold to 100%. Why does this2701 * need to be done?2702 */2703 outb(inb(DSPCISTATUS(config.base)) | DFTHRESH, DSPCISTATUS(config.base));
2704 outb(config.scsi_id | DFTHRESH, HA_SCSICONF(config.base));
2705
2706 /*2707 * In case we are a wide card, place scsi ID in second conf byte.2708 */2709 outb(config.scsi_id, (HA_SCSICONF(config.base) + 1));
2710
2711 /*2712 * A reminder until this can be detected automatically.2713 */2714 printk("aic%s: extended translation %sabled\n", board_name[type],
2715 config.extended ? "en" : "dis");
2716 break;
2717
2718 default:
2719 panic("aic7xxx_register: internal error\n");
2720 }2721
2722 config.maxscb = detect_maxscb(type, base);
2723
2724 if ((config.type == AIC_274x) || (config.type == AIC_284x))
2725 {2726 if (config.pause & IRQMS)
2727 {2728 printk("aic7xxx: Using Level Sensitive Interrupts\n");
2729 }2730 else2731 {2732 printk("aic7xxx: Using Edge Triggered Interrupts\n");
2733 }2734 }2735
2736 /*2737 * Read the bus type from the SBLKCTL register. Set the FLAGS2738 * register in the sequencer for twin and wide bus cards.2739 */2740 sblkctl = inb(SBLKCTL(base)) & 0x0F; /* mask out upper two bits */2741 switch (sblkctl)
2742 {2743 case 0: /* narrow/normal bus */2744 config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2745 config.bus_type = AIC_SINGLE;
2746 outb(0, HA_FLAGS(base));
2747 break;
2748
2749 case 2: /* Wide bus */2750 config.scsi_id = inb(HA_SCSICONF(base) + 1) & 0x0F;
2751 config.bus_type = AIC_WIDE;
2752 printk("aic7xxx : Enabling wide channel of %s-Wide\n",
2753 board_name[config.type]);
2754 outb(WIDE_BUS, HA_FLAGS(base));
2755 break;
2756
2757 case 8: /* Twin bus */2758 config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2759 #ifdefAIC7XXX_TWIN_SUPPORT2760 config.scsi_id_b = inb(HA_SCSICONF(base) + 1) & 0x07;
2761 config.bus_type = AIC_TWIN;
2762 printk("aic7xxx : Enabled channel B of %s-Twin\n",
2763 board_name[config.type]);
2764 outb(TWIN_BUS, HA_FLAGS(base));
2765 #else2766 config.bus_type = AIC_SINGLE;
2767 printk("aic7xxx : Channel B of %s-Twin will be ignored\n",
2768 board_name[config.type]);
2769 outb(0, HA_FLAGS(base));
2770 #endif2771 break;
2772
2773 default:
2774 printk("aic7xxx is an unsupported type 0x%x, please "
2775 "mail deang@ims.com\n", inb(SBLKCTL(base)));
2776 outb(0, HA_FLAGS(base));
2777 return(0);
2778 }2779
2780 /*2781 * Clear the upper two bits. For the 294x cards, clearing the2782 * upper two bits, will take the card out of diagnostic mode2783 * and make the host adatper LED follow bus activity (will not2784 * always be on).2785 */2786 outb(sblkctl, SBLKCTL(base));
2787
2788 /*2789 * The IRQ level in i/o port 4 maps directly onto the real2790 * IRQ number. If it's ok, register it with the kernel.2791 *2792 * NB. the Adaptec documentation says the IRQ number is only2793 * in the lower four bits; the ECU information shows the2794 * high bit being used as well. Which is correct?2795 *2796 * The 294x cards (PCI) get their interrupt from PCI BIOS.2797 */2798 if (((config.type == AIC_274x) || (config.type == AIC_284x))
2799 && (config.irq < 9 || config.irq > 15))
2800 {2801 printk("aic7xxx uses unsupported IRQ level, ignoring\n");
2802 return(0);
2803 }2804
2805 /*2806 * Check the IRQ to see if it is shared by another aic7xxx2807 * controller. If it is and sharing of IRQs is not defined,2808 * then return 0 hosts found. If sharing of IRQs is allowed2809 * or the IRQ is not shared by another host adapter, then2810 * proceed.2811 */2812 #ifndefAIC7XXX_SHARE_IRQS2813 if (aic7xxx_boards[config.irq] != NULL)
2814 {2815 printk("aic7xxx_register: Sharing of IRQs is not configured.\n");
2816 return(0);
2817 }2818 #endif2819
2820 /*2821 * Print out debugging information before re-enabling2822 * the card - a lot of registers on it can't be read2823 * when the sequencer is active.2824 */2825 debug_config(&config);
2826
2827 /*2828 * Before registry, make sure that the offsets of the2829 * struct scatterlist are what the sequencer will expect,2830 * otherwise disable scatter-gather altogether until someone2831 * can fix it. This is important since the sequencer will2832 * DMA elements of the SG array in while executing commands.2833 */2834 if (template->sg_tablesize != SG_NONE)
2835 {2836 structscatterlistsg;
2837
2838 if (SG_STRUCT_CHECK(sg))
2839 {2840 printk("aic7xxx warning: kernel scatter-gather "
2841 "structures changed, disabling it\n");
2842 template->sg_tablesize = SG_NONE;
2843 }2844 }2845
2846 /*2847 * Register each "host" and fill in the returned Scsi_Host2848 * structure as best we can. Some of the parameters aren't2849 * really relevant for bus types beyond ISA, and none of the2850 * high-level SCSI code looks at it anyway. Why are the fields2851 * there? Also save the pointer so that we can find the2852 * information when an IRQ is triggered.2853 */2854 host = scsi_register(template, sizeof(structaic7xxx_host));
2855 host->can_queue = config.maxscb;
2856 #ifdefAIC7XXX_TAGGED_QUEUEING2857 host->cmd_per_lun = 2;
2858 #else2859 host->cmd_per_lun = 1;
2860 #endif2861 host->this_id = config.scsi_id;
2862 host->irq = config.irq;
2863 if (config.bus_type == AIC_WIDE)
2864 {2865 host->max_id = 16;
2866 }2867 if (config.bus_type == AIC_TWIN)
2868 {2869 host->max_channel = 1;
2870 }2871
2872 p = (structaic7xxx_host *) host->hostdata;
2873
2874 /* Initialize the scb array by setting the state to free. */2875 for (i = 0; i < AIC7XXX_MAXSCB; i = i + 1)
2876 {2877 p->scb_array[i].state = SCB_FREE;
2878 p->scb_array[i].next = NULL;
2879 p->scb_array[i].cmd = NULL;
2880 }2881
2882 p->isr_count = 0;
2883 p->a_scanned = 0;
2884 p->b_scanned = 0;
2885 p->base = config.base;
2886 p->maxscb = config.maxscb;
2887 p->numscb = 0;
2888 p->extended = config.extended;
2889 p->type = config.type;
2890 p->bus_type = config.bus_type;
2891 p->have_seeprom = have_seeprom;
2892 p->seeprom = sc;
2893 p->free_scb = NULL;
2894 p->next = NULL;
2895
2896 p->unpause = config.unpause;
2897 p->pause = config.pause;
2898
2899 if (aic7xxx_boards[config.irq] == NULL)
2900 {2901 /*2902 * Register IRQ with the kernel.2903 */2904 if (request_irq(config.irq, aic7xxx_isr, SA_INTERRUPT, "aic7xxx"))
2905 {2906 printk("aic7xxx couldn't register irq %d, ignoring\n", config.irq);
2907 return(0);
2908 }2909 aic7xxx_boards[config.irq] = host;
2910 }2911 else2912 {2913 /*2914 * We have found a host adapter sharing an IRQ of a previously2915 * registered host adapter. Add this host adapter's Scsi_Host2916 * to the beginning of the linked list of hosts at the same IRQ.2917 */2918 p->next = aic7xxx_boards[config.irq];
2919 aic7xxx_boards[config.irq] = host;
2920 }2921
2922 /*2923 * Load the sequencer program, then re-enable the board -2924 * resetting the AIC-7770 disables it, leaving the lights2925 * on with nobody home. On the PCI bus you *may* be home,2926 * but then your mailing address is dynamically assigned2927 * so no one can find you anyway :-)2928 */2929 printk("aic7xxx: Downloading sequencer code..");
2930 aic7xxx_loadseq(base);
2931
2932 /* Set Fast Mode and Enable the board */2933 outb(FASTMODE, SEQCTL(base));
2934
2935 if ((p->type == AIC_274x || p->type == AIC_284x))
2936 {2937 outb(ENABLE, BCTL(base));
2938 }2939
2940 printk("done.\n");
2941
2942 /*2943 * Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels2944 */2945 if (p->bus_type == AIC_TWIN)
2946 {2947 /*2948 * The device is gated to channel B after a chip reset,2949 * so set those values first.2950 */2951 outb(config.scsi_id_b, SCSIID(base));
2952 scsi_conf = inb(HA_SCSICONF(base) + 1) & (ENSPCHK | STIMESEL);
2953 scsi_conf = scsi_conf | ENSTIMER | ACTNEGEN | STPWEN;
2954 outb(scsi_conf, SXFRCTL1(base));
2955 outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
2956 /* Select Channel A */2957 outb(0, SBLKCTL(base));
2958 }2959 outb(config.scsi_id, SCSIID(base));
2960 scsi_conf = inb(HA_SCSICONF(base)) & (ENSPCHK | STIMESEL);
2961 outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
2962 outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
2963
2964 /* Look at the information that board initialization or the board2965 * BIOS has left us. In the lower four bits of each target's2966 * scratch space any value other than 0 indicates that we should2967 * initiate synchronous transfers. If it's zero, the user or the2968 * BIOS has decided to disable synchronous negotiation to that2969 * target so we don't activate the needsdtr flag.2970 */2971 p->needsdtr_copy = 0;
2972 p->sdtr_pending = 0;
2973 p->needwdtr_copy = 0;
2974 p->wdtr_pending = 0;
2975 if (p->bus_type == AIC_SINGLE)
2976 {2977 max_targets = 8;
2978 }2979 else2980 {2981 max_targets = 16;
2982 }2983
2984 for (i = 0; i < max_targets; i = i + 1)
2985 {2986 if (have_seeprom)
2987 {2988 target_settings = (sc.device_flags[i] & CFXFER) << 4;
2989 if (sc.device_flags[i] & CFSYNCH)
2990 {2991 p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
2992 }2993 if ((sc.device_flags[i] & CFWIDEB) && (p->bus_type == AIC_WIDE))
2994 {2995 p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
2996 }2997 }2998 else2999 {3000 target_settings = inb(HA_TARG_SCRATCH(base) + i);
3001 if (target_settings & 0x0F)
3002 {3003 p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
3004 /*3005 * Default to asynchronous transfers (0 offset)3006 */3007 target_settings = target_settings & 0xF0;
3008 }3009 /*3010 * If we are not wide, forget WDTR. This makes the driver3011 * work on some cards that don't leave these fields cleared3012 * when BIOS is not installed.3013 */3014 if ((target_settings & 0x80) && (p->bus_type == AIC_WIDE))
3015 {3016 p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
3017 target_settings = target_settings & 0x7F;
3018 }3019 }3020 outb(target_settings, (HA_TARG_SCRATCH(base) + i));
3021 }3022
3023 p->needsdtr = p->needsdtr_copy;
3024 p->needwdtr = p->needwdtr_copy;
3025 printk("NeedSdtr = 0x%x, 0x%x\n", p->needsdtr_copy, p->needsdtr);
3026 printk("NeedWdtr = 0x%x, 0x%x\n", p->needwdtr_copy, p->needwdtr);
3027
3028 /* 3029 * Clear the control byte for every SCB so that the sequencer3030 * doesn't get confused and think that one of them is valid3031 */3032 for (i = 0; i < config.maxscb; i = i + 1)
3033 {3034 outb(i, SCBPTR(base));
3035 outb(0, SCBARRAY(base));
3036 }3037
3038 /*3039 * For reconnecting targets, the sequencer code needs to3040 * know how many SCBs it has to search through.3041 */3042 outb(config.maxscb, HA_SCBCOUNT(base));
3043
3044 /*3045 * Clear the active flags - no targets are busy.3046 */3047 outb(0, HA_ACTIVE0(base));
3048 outb(0, HA_ACTIVE1(base));
3049
3050 /* We don't have any waiting selections */3051 outb (SCB_LIST_NULL, WAITING_SCBH(base));
3052 outb (SCB_LIST_NULL, WAITING_SCBT(base));
3053
3054 /*3055 * Reset the SCSI bus. Is this necessary?3056 * There may be problems for a warm boot without resetting3057 * the SCSI bus. Either BIOS settings in scratch RAM3058 * will not get reinitialized, or devices may stay at3059 * previous negotiated settings (SDTR and WDTR) while3060 * the driver will think that no negotiations have been3061 * performed.3062 *3063 * Some devices need a long time to "settle" after a SCSI3064 * bus reset.3065 */3066
3067 if (!aic7xxx_no_reset)
3068 {3069 printk("Resetting the SCSI bus...\n");
3070 outb(SCSIRSTO, SCSISEQ(base));
3071 udelay(1000);
3072 outb(0, SCSISEQ(base));
3073 aic7xxx_delay(AIC7XXX_RESET_DELAY);
3074 }3075
3076 /*3077 * Unpause the sequencer before returning and enable3078 * interrupts - we shouldn't get any until the first3079 * command is sent to us by the high-level SCSI code.3080 */3081 UNPAUSE_SEQUENCER(p);
3082 return(found);
3083 }3084
3085 /*+F*************************************************************************3086 * Function:3087 * aic7xxx_detect3088 *3089 * Description:3090 * Try to detect and register an Adaptec 7770 or 7870 SCSI controller.3091 *-F*************************************************************************/3092 int3093 aic7xxx_detect(Scsi_Host_Template *template)
/* */3094 {3095 aha_typetype = AIC_NONE;
3096 intfound = 0, slot, base;
3097 unsignedcharirq = 0;
3098 inti;
3099
3100 /*3101 * Since we may allow sharing of IRQs, it is imperative3102 * that we "null-out" the aic7xxx_boards array. It is3103 * not guaranteed to be initialized to 0 (NULL). We use3104 * a NULL entry to indicate that no prior hosts have3105 * been found/registered for that IRQ.3106 */3107 for (i = 0; i <= MAXIRQ; i++)
3108 {3109 aic7xxx_boards[i] = NULL;
3110 }3111
3112 /*3113 * EISA/VL-bus card signature probe.3114 */3115 for (slot = MINSLOT; slot <= MAXSLOT; slot++)
3116 {3117 base = SLOTBASE(slot);
3118
3119 if (check_region(MINREG(base), MAXREG(base) - MINREG(base)))
3120 {3121 /*3122 * Some other driver has staked a3123 * claim to this i/o region already.3124 */3125 continue;
3126 }3127
3128 type = aic7xxx_probe(slot, HID0(base));
3129 if (type != AIC_NONE)
3130 {3131 printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3132 #if 0
3133 outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3134 irq = inb(HA_INTDEF(base)) & 0x0F;
3135 #endif3136
3137 /*3138 * We "find" a AIC-7770 if we locate the card3139 * signature and we can set it up and register3140 * it with the kernel without incident.3141 */3142 found += aic7xxx_register(template, type, base, irq);
3143 }3144 }3145
3146 #ifdefCONFIG_PCI3147
3148 #defineDEVREVID 0x08
3149 #defineDEVCONFIG 0x40
3150 #defineDEVSTATUS 0x41
3151 #defineRAMPSM 0x02
3152
3153 /* This should be defined in pci.h */3154 #definePCI_DEVICE_ID_ADAPTEC_7850 0x5078
3155 #definePCI_DEVICE_ID_ADAPTEC_7872 0x7278
3156
3157 /*3158 * PCI-bus probe.3159 */3160 if (pcibios_present())
3161 {3162 interror;
3163 intdone = 0;
3164 unsignedintio_port;
3165 unsignedshortindex = 0;
3166 unsignedcharpci_bus, pci_device_fn;
3167 unsignedchardevrevid, devconfig, devstatus;
3168 charrev_id[] = {'B', 'C', 'D'};
3169
3170 while (!done)
3171 {3172 if ((!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3173 PCI_DEVICE_ID_ADAPTEC_294x,
3174 index, &pci_bus, &pci_device_fn)) ||
3175 (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3176 PCI_DEVICE_ID_ADAPTEC_2940,
3177 index, &pci_bus, &pci_device_fn)))
3178 {3179 type = AIC_7870;
3180 }3181 else3182 {3183 if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3184 PCI_DEVICE_ID_ADAPTEC_7850,
3185 index, &pci_bus, &pci_device_fn))
3186 {3187 type = AIC_7850;
3188 }3189 else3190 {3191 if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3192 PCI_DEVICE_ID_ADAPTEC_7872,
3193 index, &pci_bus, &pci_device_fn))
3194 {3195 type = AIC_7872;
3196 }3197 else3198 {3199 type = AIC_NONE;
3200 done = 1;
3201 }3202 }3203 }3204
3205 if (!done)
3206 {3207 /*3208 * Read esundry information from PCI BIOS.3209 */3210 error = pcibios_read_config_dword(pci_bus, pci_device_fn,
3211 PCI_BASE_ADDRESS_0, &io_port);
3212
3213 if (error)
3214 {3215 panic("aic7xxx_detect: error 0x%x reading i/o port.\n", error);
3216 }3217
3218 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3219 PCI_INTERRUPT_LINE, &irq);
3220 if (error)
3221 {3222 panic("aic7xxx_detect: error %d reading irq.\n", error);
3223 }3224
3225 /*3226 * Make the base I/O register look like EISA and VL-bus.3227 */3228 base = io_port - 0xC01;
3229
3230 printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3231 outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3232
3233 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3234 DEVREVID, &devrevid);
3235 if (devrevid < 3)
3236 {3237 printk ("aic7xxx_detect: AIC-7870 Rev %c\n", rev_id[devrevid]);
3238 }3239 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3240 DEVCONFIG, &devconfig);
3241 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3242 DEVSTATUS, &devstatus);
3243 printk ("aic7xxx_detect: devconfig 0x%x, devstatus 0x%x\n",
3244 devconfig, devstatus);
3245 if (devstatus & RAMPSM)
3246 {3247 printk ("aic7xxx_detect: detected external SCB RAM, "
3248 "mail deang@ims.com for test patch");
3249 }3250
3251 found += aic7xxx_register(template, type, base, irq);
3252 index += 1;
3253 }3254 }3255 }3256 #endifCONFIG_PCI3257
3258 template->name = (char *) aic7xxx_info(NULL);
3259 return(found);
3260 }3261
3262
3263 /*+F*************************************************************************3264 * Function:3265 * aic7xxx_buildscb3266 *3267 * Description:3268 * Build a SCB.3269 *-F*************************************************************************/3270 staticvoid3271 aic7xxx_buildscb(structaic7xxx_host *p,
/* */3272 Scsi_Cmnd *cmd,
3273 structaic7xxx_scb *scb)
3274 {3275 void *addr;
3276 unsignedlength;
3277 unsignedshortmask;
3278
3279 /*3280 * Setup the control byte if we need negotiation and have not3281 * already requested it.3282 */3283 #ifdefAIC7XXX_TAGGED_QUEUEING3284 if (cmd->device->tagged_supported)
3285 {3286 if (cmd->device->tagged_queue == 0)
3287 {3288 printk ("aic7xxx_buildscb: Enabling tagged queuing for target %d, "
3289 "channel %d\n", cmd->target, cmd->channel);
3290 cmd->device->tagged_queue = 1;
3291 cmd->device->current_tag = 1; /* enable tagging */3292 }3293 cmd->tag = cmd->device->current_tag;
3294 cmd->device->current_tag = cmd->device->current_tag + 1;
3295 scb->control = scb->control | SCB_TE;
3296 }3297 #endif3298 mask = (0x01 << cmd->target);
3299 if ((p->needwdtr & mask) && !(p->wdtr_pending & mask))
3300 {3301 p->wdtr_pending = p->wdtr_pending | mask;
3302 scb->control = scb->control | SCB_NEEDWDTR;
3303 #if 0
3304 printk("Sending WDTR request to target %d.\n", cmd->target);
3305 #endif3306 }3307 else3308 {3309 if ((p->needsdtr & mask) && !(p->sdtr_pending & mask))
3310 {3311 p->sdtr_pending = p->sdtr_pending | mask;
3312 scb->control = scb->control | SCB_NEEDSDTR;
3313 #if 0
3314 printk("Sending SDTR request to target %d.\n", cmd->target);
3315 #endif3316 }3317 }3318
3319 #if 0
3320 printk("aic7xxx_queue: target %d, cmd 0x%x (size %u), wdtr 0x%x, mask 0x%x\n",
3321 cmd->target, cmd->cmnd[0], cmd->cmd_len, p->needwdtr, mask);
3322 #endif3323 scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
3324 ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
3325
3326 /*3327 * The interpretation of request_buffer and request_bufflen3328 * changes depending on whether or not use_sg is zero; a3329 * non-zero use_sg indicates the number of elements in the3330 * scatter-gather array.3331 *3332 * The AIC-7770 can't support transfers of any sort larger3333 * than 2^24 (three-byte count) without backflips. For what3334 * the kernel is doing, this shouldn't occur. I hope.3335 */3336 length = aic7xxx_length(cmd, 0);
3337
3338 if (length > 0xFFFFFF)
3339 {3340 panic("aic7xxx_buildscb: can't transfer > 2^24 - 1 bytes\n");
3341 }3342
3343 /*3344 * XXX - this relies on the host data being stored in a3345 * little-endian format.3346 */3347 addr = cmd->cmnd;
3348 scb->SCSI_cmd_length = cmd->cmd_len;
3349 memcpy(scb->SCSI_cmd_pointer, &addr, sizeof(scb->SCSI_cmd_pointer));
3350
3351 if (cmd->use_sg)
3352 {3353 #if 0
3354 debug("aic7xxx_buildscb: SG used, %d segments, length %u\n",
3355 cmd->use_sg, length);
3356 #endif3357 scb->SG_segment_count = cmd->use_sg;
3358 memcpy(scb->SG_list_pointer, &cmd->request_buffer,
3359 sizeof(scb->SG_list_pointer));
3360 }3361 else3362 {3363 #if 0
3364 debug ("aic7xxx_buildscb: Creating scatterlist, addr=0x%lx, length=%d.\n",
3365 (unsignedlong) cmd->request_buffer, cmd->request_bufflen);
3366 #endif3367 #ifdefAIC7XXX_USE_SG3368 scb->SG_segment_count = 1;
3369 scb->sg.address = (char *) cmd->request_buffer;
3370 scb->sg.length = cmd->request_bufflen;
3371 addr = &scb->sg;
3372 memcpy(scb->SG_list_pointer, &addr, sizeof(scb->SG_list_pointer));
3373 #else3374 scb->SG_segment_count = 0;
3375 memcpy(scb->data_pointer, &cmd->request_buffer, sizeof(scb->data_pointer));
3376 memcpy(scb->data_count, &cmd->request_bufflen, 3);
3377 #endif3378 }3379 }3380
3381 /*+F*************************************************************************3382 * Function:3383 * aic7xxx_queue3384 *3385 * Description:3386 * Queue a SCB to the controller.3387 *-F*************************************************************************/3388 int3389 aic7xxx_queue(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *))
/* */3390 {3391 longflags;
3392 #ifndefAIC7XXX_USE_DMA3393 intold_scbptr;
3394 #endif3395 structaic7xxx_host *p;
3396 structaic7xxx_scb *scb;
3397 unsignedcharcurscb;
3398
3399 p = (structaic7xxx_host *) cmd->host->hostdata;
3400
3401 /* Check to see if channel was scanned. */3402 if (!p->a_scanned && (cmd->channel == 0))
3403 {3404 printk("aic7xxx: Scanning channel A for devices.\n");
3405 p->a_scanned = 1;
3406 }3407 else3408 {3409 if (!p->b_scanned && (cmd->channel == 1))
3410 {3411 printk("aic7xxx: Scanning channel B for devices.\n");
3412 p->b_scanned = 1;
3413 }3414 }3415
3416 #if 0
3417 debug("aic7xxx_queue: cmd 0x%x (size %u), target %d, channel %d, lun %d\n",
3418 cmd->cmnd[0], cmd->cmd_len, cmd->target, cmd->channel,
3419 cmd->lun & 0x07);
3420 #endif3421
3422 /*3423 * This is a critical section, since we don't want the3424 * interrupt routine mucking with the host data or the3425 * card. Since the kernel documentation is vague on3426 * whether or not we are in a cli/sti pair already, save3427 * the flags to be on the safe side.3428 */3429 save_flags(flags);
3430 cli();
3431
3432 /*3433 * Find a free slot in the SCB array to load this command3434 * into. Since can_queue is set to the maximum number of3435 * SCBs for the card, we should always find one.3436 *3437 * First try to find an scb in the free list. If there are3438 * none in the free list, then check the current number of3439 * of scbs and take an unused one from the scb array.3440 */3441 scb = p->free_scb;
3442 if (scb != NULL)
3443 {/* found one in the free list */3444 p->free_scb = scb->next; /* remove and update head of list */3445 /*3446 * Warning! For some unknown reason, the scb at the head3447 * of the free list is not the same address that it should3448 * be. That's why we set the scb pointer taken by the3449 * position in the array. The scb at the head of the list3450 * should match this address, but it doesn't.3451 */3452 scb = &(p->scb_array[scb->position]);
3453 scb->control = 0;
3454 scb->state = SCB_ACTIVE;
3455 }3456 else3457 {3458 if (p->numscb >= p->maxscb)
3459 {3460 panic("aic7xxx_queue: couldn't find a free scb\n");
3461 }3462 else3463 {3464 /*3465 * Initialize the scb within the scb array. The3466 * position within the array is the position on3467 * the board that it will be loaded.3468 */3469 scb = &(p->scb_array[p->numscb]);
3470 memset(scb, 0, sizeof(*scb));
3471
3472 scb->position = p->numscb;
3473 p->numscb = p->numscb + 1;
3474 scb->state = SCB_ACTIVE;
3475 scb->next_waiting = SCB_LIST_NULL;
3476 memcpy(scb->host_scb, &scb, sizeof(scb));
3477 #ifdefAIC7XXX_USE_DMA3478 scb->control = SCB_NEEDDMA;
3479 #endif3480 PAUSE_SEQUENCER(p);
3481 curscb = inb(SCBPTR(p->base));
3482 outb(scb->position, SCBPTR(p->base));
3483 aic7xxx_putdmascb(p->base, scb);
3484 outb(curscb, SCBPTR(p->base));
3485 UNPAUSE_SEQUENCER(p);
3486 scb->control = 0;
3487 }3488 }3489
3490 scb->cmd = cmd;
3491 aic7xxx_position(cmd) = scb->position;
3492
3493 /*3494 * Construct the SCB beforehand, so the sequencer is3495 * paused a minimal amount of time.3496 */3497 aic7xxx_buildscb(p, cmd, scb);
3498
3499 #if 0
3500 if (scb != &p->scb_array[scb->position])
3501 {3502 printk("aic7xxx_queue: address of scb by position does not match scb address\n");
3503 }3504 printk("aic7xxx_queue: SCB pos=%d, cmdptr=0x%x, state=%d, freescb=0x%x\n",
3505 scb->position, (unsignedint) scb->cmd,
3506 scb->state, (unsignedint) p->free_scb);
3507 #endif3508 /*3509 * Pause the sequencer so we can play with its registers -3510 * wait for it to acknowledge the pause.3511 *3512 * XXX - should the interrupts be left on while doing this?3513 */3514 PAUSE_SEQUENCER(p);
3515
3516 /*3517 * Save the SCB pointer and put our own pointer in - this3518 * selects one of the four banks of SCB registers. Load3519 * the SCB, then write its pointer into the queue in FIFO3520 * and restore the saved SCB pointer.3521 */3522 #ifdefAIC7XXX_USE_DMA3523 aic7xxx_putscb(p->base, scb);
3524 #else3525 old_scbptr = inb(SCBPTR(p->base));
3526 outb(scb->position, SCBPTR(p->base));
3527
3528 aic7xxx_putscb(p->base, scb);
3529
3530 outb(scb->position, QINFIFO(p->base));
3531 outb(old_scbptr, SCBPTR(p->base));
3532 #endif3533 /*3534 * Make sure the Scsi_Cmnd pointer is saved, the struct it3535 * points to is set up properly, and the parity error flag3536 * is reset, then unpause the sequencer and watch the fun3537 * begin.3538 */3539 cmd->scsi_done = fn;
3540 aic7xxx_error(cmd) = DID_OK;
3541 aic7xxx_status(cmd) = 0;
3542
3543 cmd->result = 0;
3544 memset (&cmd->sense_buffer, 0, sizeof (cmd->sense_buffer));
3545
3546 UNPAUSE_SEQUENCER(p);
3547 restore_flags(flags);
3548 return(0);
3549 }3550
3551 /* return values from aic7xxx_kill */3552 typedefenum{3553 k_ok, /* scb found and message sent */3554 k_busy, /* message already present */3555 k_absent, /* couldn't locate scb */3556 k_disconnect, /* scb found, but disconnected */3557 }k_state;
3558
3559 /*+F*************************************************************************3560 * Function:3561 * aic7xxx_kill3562 *3563 * Description:3564 * This must be called with interrupts disabled - it's going to3565 * be messing around with the host data, and an interrupt being3566 * fielded in the middle could get ugly.3567 *3568 * Since so much of the abort and reset code is shared, this3569 * function performs more magic than it really should. If the3570 * command completes ok, then it will call scsi_done with the3571 * result code passed in. The unpause parameter controls whether3572 * or not the sequencer gets unpaused - the reset function, for3573 * instance, may want to do something more aggressive.3574 *3575 * Note that the command is checked for in our SCB_array first3576 * before the sequencer is paused, so if k_absent is returned,3577 * then the sequencer is NOT paused.3578 *-F*************************************************************************/3579 statick_state3580 aic7xxx_kill(Scsi_Cmnd *cmd, unsignedcharmessage,
/* */3581 unsignedintresult, intunpause)
3582 {3583 structaic7xxx_host *p;
3584 structaic7xxx_scb *scb;
3585 inti, active_scb, found, queued;
3586 unsignedcharscbsave[AIC7XXX_MAXSCB];
3587 unsignedcharflags;
3588 intscb_control;
3589 k_statestatus;
3590
3591 p = (structaic7xxx_host *) cmd->host->hostdata;
3592 scb = &p->scb_array[aic7xxx_position(cmd)];
3593
3594 #if 0
3595 printk("aic7xxx_kill: In the kill function...\n");
3596 #endif3597 PAUSE_SEQUENCER(p);
3598
3599 /*3600 * Case 1: In the QINFIFO3601 *3602 * This is the best case, really. Check to see if the3603 * command is still in the sequencer's input queue. If3604 * so, simply remove it. Reload the queue afterward.3605 */3606 queued = inb(QINCNT(p->base));
3607
3608 for (i = found = 0; i < (queued - found); i++)
3609 {3610 scbsave[i] = inb(QINFIFO(p->base));
3611
3612 if (scbsave[i] == scb->position)
3613 {3614 found = 1;
3615 i = i - 1;
3616 }3617 }3618
3619 for (queued = 0; queued < i; queued++)
3620 {3621 outb(scbsave[queued], QINFIFO(p->base));
3622 }3623
3624 if (found)
3625 {3626 status = k_ok;
3627 gotocomplete;
3628 }3629
3630 active_scb = inb(SCBPTR(p->base));
3631 /*3632 * Case 2: Not the active command3633 *3634 * Check the current SCB bank. If it's not the one belonging3635 * to the command we want to kill, select the scb we want to3636 * abort and turn off the disconnected bit. The driver will3637 * then abort the command and notify us of the abort.3638 */3639 if (active_scb != scb->position)
3640 {3641 outb(scb->position, SCBPTR(p->base));
3642 scb_control = inb(SCBARRAY(p->base));
3643 scb_control = scb_control & ~SCB_DIS;
3644 outb(scb_control, SCBARRAY(p->base));
3645 outb(active_scb, SCBPTR(p->base));
3646 status = k_disconnect;
3647 gotocomplete;
3648 }3649
3650 scb_control = inb(SCBARRAY(p->base));
3651 if (scb_control & SCB_DIS)
3652 {3653 scb_control = scb_control & ~SCB_DIS;
3654 outb(scb_control, SCBARRAY(p->base));
3655 status = k_disconnect;
3656 gotocomplete;
3657 }3658
3659 /*3660 * Presumably at this point our target command is active. Check3661 * to see if there's a message already in effect. If not, place3662 * our message in and assert ATN so the target goes into MESSAGE3663 * OUT phase.3664 */3665 flags = inb(HA_FLAGS(p->base));
3666 if (flags & ACTIVE_MSG)
3667 {3668 /*3669 * If there is a message in progress, reset the bus3670 * and have all devices renegotiate.3671 */3672 if (cmd->channel & 0x01)
3673 {3674 p->needsdtr = p->needsdtr_copy & 0xFF00;
3675 p->sdtr_pending = p->sdtr_pending & 0x00FF;
3676 outb(0, HA_ACTIVE1(p->base));
3677 }3678 else3679 {3680 if (p->bus_type == AIC_WIDE)
3681 {3682 p->needsdtr = p->needsdtr_copy;
3683 p->needwdtr = p->needwdtr_copy;
3684 p->sdtr_pending = 0;
3685 p->wdtr_pending = 0;
3686 outb(0, HA_ACTIVE0(p->base));
3687 outb(0, HA_ACTIVE1(p->base));
3688 }3689 else3690 {3691 p->needsdtr = p->needsdtr_copy & 0x00FF;
3692 p->sdtr_pending = p->sdtr_pending & 0xFF00;
3693 outb(0, HA_ACTIVE0(p->base));
3694 }3695 }3696 /* Reset the bus. */3697 outb(SCSIRSTO, SCSISEQ(p->base));
3698 udelay(1000);
3699 outb(0, SCSISEQ(p->base));
3700 aic7xxx_delay(AIC7XXX_RESET_DELAY);
3701
3702 status = k_busy;
3703 gotocomplete;
3704 }3705
3706 outb(flags | ACTIVE_MSG, HA_FLAGS(p->base)); /* active message */3707 outb(1, HA_MSG_LEN(p->base)); /* length = 1 */3708 outb(message, HA_MSG_START(p->base)); /* message body */3709
3710 /*3711 * Assert ATN. Use the value of SCSISIGO saved by the3712 * sequencer code so we don't alter its contents radically3713 * in the middle of something critical.3714 */3715 outb(inb(HA_SIGSTATE(p->base)) | 0x10, SCSISIGO(p->base));
3716
3717 status = k_ok;
3718
3719 /*3720 * The command has been killed. Do the bookkeeping, unpause3721 * the sequencer, and notify the higher-level SCSI code.3722 */3723 complete:
3724 if (unpause)
3725 {3726 UNPAUSE_SEQUENCER(p);
3727 }3728
3729 /*3730 * Mark the scb as free and clear the scbs command pointer.3731 * Add the scb to the head of the free list being careful3732 * to preserve the next pointers.3733 */3734 scb->state = SCB_FREE; /* mark the scb as free */3735 scb->cmd = NULL; /* clear the command pointer */3736 scb->next = p->free_scb; /* preserve next pointer */3737 p->free_scb = scb; /* add at head of free list */3738 cmd->result = cmd->result << 16;
3739 cmd->scsi_done(cmd);
3740 return(status);
3741 }3742
3743 /*+F*************************************************************************3744 * Function:3745 * aic7xxx_abort3746 *3747 * Description:3748 * Abort the current SCSI command(s).3749 *-F*************************************************************************/3750 int3751 aic7xxx_abort(Scsi_Cmnd *cmd)
/* */3752 {3753 intrv;
3754 longflags;
3755
3756 save_flags(flags);
3757 cli();
3758
3759 switch (aic7xxx_kill(cmd, ABORT, DID_ABORT, !0))
3760 {3761 casek_ok: rv = SCSI_ABORT_SUCCESS; break;
3762 casek_busy: rv = SCSI_ABORT_BUSY; break;
3763 casek_absent: rv = SCSI_ABORT_NOT_RUNNING; break;
3764 casek_disconnect: rv = SCSI_ABORT_SNOOZE; break;
3765 default: panic("aic7xxx_abort: internal error\n");
3766 }3767
3768 restore_flags(flags);
3769 return(rv);
3770 }3771
3772 /*+F*************************************************************************3773 * Function:3774 * aic7xxx_reset3775 *3776 * Description:3777 * Resetting the bus always succeeds - is has to, otherwise the3778 * kernel will panic! Try a surgical technique - sending a BUS3779 * DEVICE RESET message - on the offending target before pulling3780 * the SCSI bus reset line.3781 *-F*************************************************************************/3782 int3783 aic7xxx_reset(Scsi_Cmnd *cmd)
/* */3784 {3785 longflags;
3786 structaic7xxx_host *p;
3787
3788 p = (structaic7xxx_host *) cmd->host->hostdata;
3789 save_flags(flags);
3790 cli();
3791
3792 switch (aic7xxx_kill(cmd, BUS_DEVICE_RESET, DID_RESET, 0))
3793 {3794 casek_ok:
3795 /*3796 * The RESET message was sent to the target3797 * with no problems. Flag that target as3798 * needing a SDTR negotiation on the next3799 * connection and restart the sequencer.3800 */3801 p->needsdtr = p->needsdtr & (1 << cmd->target);
3802 UNPAUSE_SEQUENCER(p);
3803 break;
3804
3805 casek_absent:
3806 /*3807 * The sequencer will not be paused if aic7xxx_kill()3808 * couldn't find the command.3809 */3810 PAUSE_SEQUENCER(p);
3811 /* falls through */3812
3813 casek_busy:
3814 cmd->result = DID_RESET << 16; /* return reset code */3815 cmd->scsi_done(cmd);
3816 break;
3817
3818 casek_disconnect:
3819 /*3820 * Do a hard reset of the SCSI bus. According to the3821 * SCSI-2 draft specification, reset has to be asserted3822 * for at least 25us. I'm invoking the kernel delay3823 * function for 30us since I'm not totally trusting of3824 * the busy loop timing.3825 *3826 * XXX - I'm not convinced this works. I tried resetting3827 * the bus before, trying to get the devices on the3828 * bus to revert to asynchronous transfer, and it3829 * never seemed to work.3830 */3831 debug("aic7xxx: attempting to reset scsi bus and card\n");
3832
3833 outb(SCSIRSTO, SCSISEQ(p->base));
3834 udelay(1000);
3835 outb(0, SCSISEQ(p->base));
3836 aic7xxx_delay(AIC7XXX_RESET_DELAY);
3837
3838 UNPAUSE_SEQUENCER(p);
3839
3840 /*3841 * Locate the command and return a "reset" status3842 * for it. This is not completely correct and will3843 * probably return to haunt me later.3844 */3845 cmd->result = DID_RESET << 16; /* return reset code */3846 cmd->scsi_done(cmd);
3847 break;
3848
3849 default:
3850 panic("aic7xxx_reset: internal error\n");
3851 }3852
3853 restore_flags(flags);
3854 return(SCSI_RESET_SUCCESS);
3855 }3856
3857 /*+F*************************************************************************3858 * Function:3859 * aic7xxx_biosparam3860 *3861 * Description:3862 * Return the disk geometry for the given SCSI device.3863 *-F*************************************************************************/3864 int3865 aic7xxx_biosparam(Disk *disk, intdevno, intgeom[])
/* */3866 {3867 intheads, sectors, cylinders;
3868 structaic7xxx_host *p;
3869
3870 p = (structaic7xxx_host *) disk->device->host->hostdata;
3871
3872 /*3873 * XXX - if I could portably find the card's configuration3874 * information, then this could be autodetected instead3875 * of left to a boot-time switch.3876 */3877 heads = 64;
3878 sectors = 32;
3879 cylinders = disk->capacity / (heads * sectors);
3880
3881 if (p->extended && cylinders > 1024)
3882 {3883 heads = 255;
3884 sectors = 63;
3885 cylinders = disk->capacity / (255 * 63);
3886 }3887
3888 geom[0] = heads;
3889 geom[1] = sectors;
3890 geom[2] = cylinders;
3891
3892 return(0);
3893 }3894
3895 #ifdefMODULE3896 /* Eventually this will go into an include file, but this will be later */3897 Scsi_Host_Templatedriver_template = AIC7XXX;
3898
3899 #include "scsi_module.c"
3900 #endif3901