This source file includes following definitions.
- pci_lookup_dev
- pci_strbioserr
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
1
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8
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/bios32.h>
13 #include <linux/pci.h>
14 #include <linux/string.h>
15
16 #include <asm/page.h>
17
18 struct pci_bus pci_root;
19 struct pci_dev *pci_devices = 0;
20
21
22
23
24
25
26
27
28
29
30
31 #define DEVICE(vid,did,name) \
32 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
33
34 #define BRIDGE(vid,did,name,bridge) \
35 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
36
37 struct pci_dev_info dev_info[] = {
38 DEVICE( NCR, NCR_53C810, "53c810"),
39 DEVICE( NCR, NCR_53C815, "53c815"),
40 DEVICE( NCR, NCR_53C820, "53c820"),
41 DEVICE( NCR, NCR_53C825, "53c825"),
42 DEVICE( ADAPTEC, ADAPTEC_2940, "2940"),
43 DEVICE( ADAPTEC, ADAPTEC_294x, "294x"),
44 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
45 DEVICE( DPT, DPT, "SmartCache/Raid"),
46 DEVICE( S3, S3_864_1, "Vision 864-P"),
47 DEVICE( S3, S3_864_2, "Vision 864-P"),
48 DEVICE( S3, S3_868, "Vision 868"),
49 DEVICE( S3, S3_928, "Vision 928-P"),
50 DEVICE( S3, S3_964_1, "Vision 964-P"),
51 DEVICE( S3, S3_964_2, "Vision 964-P"),
52 DEVICE( S3, S3_811, "Trio32/Trio64"),
53 DEVICE( S3, S3_968, "Vision 968"),
54 DEVICE( OPTI, OPTI_82C822, "82C822"),
55 DEVICE( OPTI, OPTI_82C621, "82C621"),
56 DEVICE( OPTI, OPTI_82C557, "82C557"),
57 DEVICE( OPTI, OPTI_82C558, "82C558"),
58 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
59 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
60 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
61 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
62 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
63 DEVICE( DEC, DEC_TULIP, "DC21040"),
64 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
65 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
66 DEVICE( DEC, DEC_FDDI, "DEFPA"),
67 DEVICE( DEC, DEC_BRD, "DC21050"),
68 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
69 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
70 DEVICE( INTEL, INTEL_82378, "82378IB"),
71 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
72 DEVICE( INTEL, INTEL_82375, "82375EB"),
73 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
74 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
75 DEVICE( INTEL, INTEL_82437, "82437 Triton"),
76 DEVICE( INTEL, INTEL_82371, "82471 Triton"),
77 DEVICE( SMC, SMC_37C665, "FDC 37C665"),
78 DEVICE( ATI, ATI_M32, "Mach 32"),
79 DEVICE( ATI, ATI_M64, "Mach 64"),
80 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
81 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
82 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
83 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
84 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
85 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
86 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
87 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
88 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
89 DEVICE( N9, N9_I128, "Imagine 128"),
90 DEVICE( AI, AI_M1435, "M1435"),
91 DEVICE( AL, AL_M1445, "M1445"),
92 DEVICE( AL, AL_M1449, "M1449"),
93 DEVICE( AL, AL_M1451, "M1451"),
94 DEVICE( AL, AL_M4803, "M4803"),
95 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
96 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
97 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
98 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
99 DEVICE( CMD, CMD_640, "640A"),
100 DEVICE( VISION, VISION_QD8500, "QD-8500"),
101 DEVICE( VISION, VISION_QD8580, "QD-8580"),
102 DEVICE( AMD, AMD_LANCE, "79C970"),
103 DEVICE( AMD, AMD_SCSI, "53C974"),
104 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
105 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
106 DEVICE( ADL, ADL_2301, "2301"),
107 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
108 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
109 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
110 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
111 DEVICE( NS, NS_87410, "87410"),
112 DEVICE( VIA, VIA_82C505, "VT 82C505"),
113 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
114 DEVICE( VIA, VIA_82C561, "VT 82C561"),
115 DEVICE( SI, SI_496, "85C496"),
116 DEVICE( SI, SI_501, "85C501"),
117 DEVICE( SI, SI_503, "85C503"),
118 DEVICE( SI, SI_601, "85C601"),
119 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
120 DEVICE( IMS, IMS_8849, "8849"),
121 DEVICE( ZEINET, ZEINET_1221, "1221"),
122 DEVICE( EF, EF_ATM, "155P-MF1"),
123 DEVICE( HER, HER_STING, "Stingray"),
124 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
125 DEVICE( CT, CT_65545, "65545"),
126 DEVICE( FD, FD_36C70, "TMC-18C30"),
127 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
128 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
129 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
130 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
131 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
132 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
133 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
134 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
135 DEVICE( X, X_AGX016, "ITT AGX016"),
136 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b")
137 };
138
139
140 #ifdef CONFIG_PCI_OPTIMIZE
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157 struct optimization_type {
158 char *type;
159 char *off;
160 char *on;
161 } bridge_optimization[] = {
162 {"Cache L2", "write trough", "write back"},
163 {"CPU-PCI posted write", "off", "on"},
164 {"CPU-Memory posted write", "off", "on"},
165 {"PCI-Memory posted write", "off", "on"},
166 {"PCI burst", "off", "on"}
167 };
168
169 #define NUM_OPTIMIZATIONS \
170 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
171
172 struct bridge_mapping_type {
173 unsigned char addr;
174 unsigned char mask;
175 unsigned char value;
176 } bridge_mapping[] = {
177
178
179
180
181
182
183
184 {0x0 ,0x02 ,0x02 },
185 {0x53 ,0x02 ,0x02 },
186 {0x53 ,0x01 ,0x01 },
187 {0x54 ,0x01 ,0x01 },
188 {0x54 ,0x02 ,0x02 },
189
190
191
192
193
194 {0x50 ,0x10 ,0x00 },
195 {0x51 ,0x40 ,0x40 },
196 {0x0 ,0x0 ,0x0 },
197 {0x0 ,0x0 ,0x0 },
198 {0x0 ,0x0 ,0x0 },
199
200
201
202
203
204
205 {0x0 ,0x1 ,0x1 },
206 {0x0 ,0x2 ,0x0 },
207 {0x0 ,0x0 ,0x0 },
208 {0x0 ,0x0 ,0x0 },
209 {0x0 ,0x0 ,0x0 }
210 };
211
212 #endif
213
214
215
216
217
218
219 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
220 {
221 int i;
222
223 for (i = 0; i < sizeof(dev_info)/sizeof(dev_info[0]); ++i) {
224 if (dev_info[i].vendor == vendor &&
225 dev_info[i].device == dev)
226 {
227 return &dev_info[i];
228 }
229 }
230 return 0;
231 }
232
233
234 char *pci_strbioserr (int error)
235 {
236 switch (error) {
237 case PCIBIOS_SUCCESSFUL: return "SUCCESSFUL";
238 case PCIBIOS_FUNC_NOT_SUPPORTED: return "FUNC_NOT_SUPPORTED";
239 case PCIBIOS_BAD_VENDOR_ID: return "SUCCESSFUL";
240 case PCIBIOS_DEVICE_NOT_FOUND: return "DEVICE_NOT_FOUND";
241 case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
242 case PCIBIOS_SET_FAILED: return "SET_FAILED";
243 case PCIBIOS_BUFFER_TOO_SMALL: return "BUFFER_TOO_SMALL";
244 default: return "Unknown error status";
245 }
246 }
247
248
249 const char *pci_strclass (unsigned int class)
250 {
251 switch (class >> 8) {
252 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
253 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
254
255 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
256 case PCI_CLASS_STORAGE_IDE: return "IDE controller";
257 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
258 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
259 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
260
261 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
262 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
263 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
264 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
265
266 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
267 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
268 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
269
270 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
271 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
272 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
273
274 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
275 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
276 case PCI_CLASS_MEMORY_OTHER: return "Memory";
277
278 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
279 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
280 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
281 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
282 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
283 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
284 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
285
286 default: return "Unknown class";
287 }
288 }
289
290
291 const char *pci_strvendor(unsigned int vendor)
292 {
293 switch (vendor) {
294 case PCI_VENDOR_ID_NCR: return "NCR";
295 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
296 case PCI_VENDOR_ID_DPT: return "DPT";
297 case PCI_VENDOR_ID_S3: return "S3 Inc.";
298 case PCI_VENDOR_ID_OPTI: return "OPTI";
299 case PCI_VENDOR_ID_UMC: return "UMC";
300 case PCI_VENDOR_ID_DEC: return "DEC";
301 case PCI_VENDOR_ID_MATROX: return "Matrox";
302 case PCI_VENDOR_ID_INTEL: return "Intel";
303 case PCI_VENDOR_ID_SMC: return "SMC";
304 case PCI_VENDOR_ID_ATI: return "ATI";
305 case PCI_VENDOR_ID_WEITEK: return "Weitek";
306 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
307 case PCI_VENDOR_ID_BUSLOGIC: return "Bus Logic";
308 case PCI_VENDOR_ID_N9: return "Number Nine";
309 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
310 case PCI_VENDOR_ID_AL: return "Acer Labs";
311 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
312 case PCI_VENDOR_ID_CMD: return "CMD";
313 case PCI_VENDOR_ID_VISION: return "Vision";
314 case PCI_VENDOR_ID_AMD: return "AMD";
315 case PCI_VENDOR_ID_VLSI: return "VLSI";
316 case PCI_VENDOR_ID_ADL: return "Advance Logic";
317 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
318 case PCI_VENDOR_ID_TRIDENT: return "Trident";
319 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
320 case PCI_VENDOR_ID_NS: return "NS";
321 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
322 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
323 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
324 case PCI_VENDOR_ID_IMS: return "IMS";
325 case PCI_VENDOR_ID_ZEINET: return "ZeiNet";
326 case PCI_VENDOR_ID_EF: return "Efficient Networks";
327 case PCI_VENDOR_ID_HER: return "Hercules";
328 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
329 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
330 case PCI_VENDOR_ID_FD: return "Future Domain";
331 case PCI_VENDOR_ID_WINBOND: return "Winbond";
332 case PCI_VENDOR_ID_3COM: return "3Com";
333 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
334 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
335 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
336 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
337 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
338 default: return "Unknown vendor";
339 }
340 }
341
342
343 const char *pci_strdev(unsigned int vendor, unsigned int device)
344 {
345 struct pci_dev_info *info;
346
347 info = pci_lookup_dev(vendor, device);
348 return info ? info->name : "Unknown device";
349 }
350
351
352
353
354
355
356 static void burst_bridge(unsigned char bus, unsigned char devfn,
357 unsigned char pos, int turn_on)
358 {
359 #ifdef CONFIG_PCI_OPTIMIZE
360 struct bridge_mapping_type *bmap;
361 unsigned char val;
362 int i;
363
364 pos *= NUM_OPTIMIZATIONS;
365 printk("PCI bridge optimization.\n");
366 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
367 printk(" %s: ", bridge_optimization[i].type);
368 bmap = &bridge_mapping[pos + i];
369 if (!bmap->addr) {
370 printk("Not supported.");
371 } else {
372 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
373 if ((val & bmap->mask) == bmap->value) {
374 printk("%s.", bridge_optimization[i].on);
375 if (!turn_on) {
376 pcibios_write_config_byte(bus, devfn,
377 bmap->addr,
378 (val | bmap->mask)
379 - bmap->value);
380 printk("Changed! Now %s.", bridge_optimization[i].off);
381 }
382 } else {
383 printk("%s.", bridge_optimization[i].off);
384 if (turn_on) {
385 pcibios_write_config_byte(bus, devfn,
386 bmap->addr,
387 (val & (0xff - bmap->mask))
388 + bmap->value);
389 printk("Changed! Now %s.", bridge_optimization[i].on);
390 }
391 }
392 }
393 printk("\n");
394 }
395 #endif
396 }
397
398
399
400
401
402
403
404
405 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
406 {
407 unsigned long base;
408 unsigned int l, class_rev, bus, devfn;
409 unsigned short vendor, device, status;
410 unsigned char bist, latency, min_gnt, max_lat;
411 int reg, len = 0;
412 const char *str;
413
414 bus = dev->bus->number;
415 devfn = dev->devfn;
416
417 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
418 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
419 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
420 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
421 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
422 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
423 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
424 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
425 if (len + 80 > size) {
426 return -1;
427 }
428 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
429 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
430
431 if (len + 80 > size) {
432 return -1;
433 }
434 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
435 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
436 pci_strdev(vendor, device), class_rev & 0xff);
437
438 if (!pci_lookup_dev(vendor, device)) {
439 len += sprintf(buf + len,
440 "Vendor id=%x. Device id=%x.\n ",
441 vendor, device);
442 }
443
444 str = 0;
445 switch (status & PCI_STATUS_DEVSEL_MASK) {
446 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
447 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
448 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
449 }
450 if (len + strlen(str) > size) {
451 return -1;
452 }
453 len += sprintf(buf + len, str);
454
455 if (status & PCI_STATUS_FAST_BACK) {
456 # define fast_b2b_capable "Fast back-to-back capable. "
457 if (len + strlen(fast_b2b_capable) > size) {
458 return -1;
459 }
460 len += sprintf(buf + len, fast_b2b_capable);
461 # undef fast_b2b_capable
462 }
463
464 if (bist & PCI_BIST_CAPABLE) {
465 # define BIST_capable "BIST capable. "
466 if (len + strlen(BIST_capable) > size) {
467 return -1;
468 }
469 len += sprintf(buf + len, BIST_capable);
470 # undef BIST_capable
471 }
472
473 if (dev->irq) {
474 if (len + 40 > size) {
475 return -1;
476 }
477 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
478 }
479
480 if (dev->master) {
481 if (len + 80 > size) {
482 return -1;
483 }
484 len += sprintf(buf + len, "Master Capable. ");
485 if (latency)
486 len += sprintf(buf + len, "Latency=%d. ", latency);
487 else
488 len += sprintf(buf + len, "No bursts. ");
489 if (min_gnt)
490 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
491 if (max_lat)
492 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
493 }
494
495 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
496 if (len + 40 > size) {
497 return -1;
498 }
499 pcibios_read_config_dword(bus, devfn, reg, &l);
500 base = l;
501 if (!base) {
502 continue;
503 }
504
505 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
506 len += sprintf(buf + len,
507 "\n I/O at 0x%lx.",
508 base & PCI_BASE_ADDRESS_IO_MASK);
509 } else {
510 const char *pref, *type = "unknown";
511
512 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
513 pref = "P";
514 } else {
515 pref = "Non-p";
516 }
517 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
518 case PCI_BASE_ADDRESS_MEM_TYPE_32:
519 type = "32 bit"; break;
520 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
521 type = "20 bit"; break;
522 case PCI_BASE_ADDRESS_MEM_TYPE_64:
523 type = "64 bit";
524
525 reg += 4;
526 pcibios_read_config_dword(bus, devfn, reg, &l);
527 base |= ((u64) l) << 32;
528 break;
529 }
530 len += sprintf(buf + len,
531 "\n %srefetchable %s memory at "
532 "0x%lx.", pref, type,
533 base & PCI_BASE_ADDRESS_MEM_MASK);
534 }
535 }
536
537 len += sprintf(buf + len, "\n");
538 return len;
539 }
540
541
542
543
544
545
546 int get_pci_list(char *buf)
547 {
548 int nprinted, len, size;
549 struct pci_dev *dev;
550 # define MSG "\nwarning: page-size limit reached!\n"
551
552
553 size = PAGE_SIZE - (strlen(MSG) + 1);
554 len = sprintf(buf, "PCI devices found:\n");
555
556 for (dev = pci_devices; dev; dev = dev->next) {
557 nprinted = sprint_dev_config(dev, buf + len, size - len);
558 if (nprinted < 0) {
559 return len + sprintf(buf + len, MSG);
560 }
561 len += nprinted;
562 }
563 return len;
564 }
565
566
567
568
569
570
571 static void *pci_malloc(long size, unsigned long *mem_startp)
572 {
573 void *mem;
574
575 #ifdef DEBUG
576 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
577 #endif
578 mem = (void*) *mem_startp;
579 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
580 memset(mem, 0, size);
581 return mem;
582 }
583
584
585 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
586 {
587 unsigned int devfn, l, max;
588 unsigned char cmd, tmp, hdr_type = 0;
589 struct pci_dev_info *info;
590 struct pci_dev *dev;
591 struct pci_bus *child;
592
593 #ifdef DEBUG
594 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
595 #endif
596
597 max = bus->secondary;
598 for (devfn = 0; devfn < 0xff; ++devfn) {
599 if (PCI_FUNC(devfn) == 0) {
600 pcibios_read_config_byte(bus->number, devfn,
601 PCI_HEADER_TYPE, &hdr_type);
602 } else if (!(hdr_type & 0x80)) {
603
604 continue;
605 }
606
607 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
608 &l);
609
610 if (l == 0xffffffff || l == 0x00000000) {
611 hdr_type = 0;
612 continue;
613 }
614
615 dev = pci_malloc(sizeof(*dev), mem_startp);
616 dev->bus = bus;
617
618
619
620
621
622 dev->next = pci_devices;
623 pci_devices = dev;
624
625 dev->devfn = devfn;
626 dev->vendor = l & 0xffff;
627 dev->device = (l >> 16) & 0xffff;
628
629
630
631
632
633
634 info = pci_lookup_dev(dev->vendor, dev->device);
635 if (!info) {
636 printk("Warning : Unknown PCI device. Please read include/linux/pci.h \n");
637 } else {
638
639 if (info->bridge_type != 0xff) {
640 burst_bridge(bus->number, devfn,
641 info->bridge_type, 1);
642 }
643 }
644
645
646 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
647 &cmd);
648 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
649 cmd | PCI_COMMAND_MASTER);
650 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
651 &tmp);
652 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
653 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
654 cmd);
655
656
657 pcibios_read_config_byte(bus->number, devfn,
658 PCI_INTERRUPT_LINE, &dev->irq);
659
660
661 pcibios_read_config_dword(bus->number, devfn,
662 PCI_CLASS_REVISION, &l);
663 l = l >> 8;
664 dev->class = l;
665
666
667
668
669 dev->sibling = bus->devices;
670 bus->devices = dev;
671
672 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
673 unsigned int buses;
674
675
676
677
678 child = pci_malloc(sizeof(*child), mem_startp);
679 child->next = bus->children;
680 bus->children = child;
681 child->self = dev;
682 child->parent = bus;
683
684
685
686
687
688 child->number = child->secondary = ++max;
689 child->primary = bus->secondary;
690 child->subordinate = 0xff;
691
692
693
694
695 pcibios_write_config_word(bus->number, devfn,
696 PCI_COMMAND, 0x0000);
697 pcibios_write_config_word(bus->number, devfn,
698 PCI_STATUS, 0xffff);
699
700
701
702 pcibios_read_config_dword(bus->number, devfn, 0x18,
703 &buses);
704 buses &= 0xff000000;
705 buses |= (((unsigned int)(child->primary) << 0) |
706 ((unsigned int)(child->secondary) << 8) |
707 ((unsigned int)(child->subordinate) << 16));
708 pcibios_write_config_dword(bus->number, devfn, 0x18,
709 buses);
710
711
712
713 max = scan_bus(child, mem_startp);
714
715
716
717
718 child->subordinate = max;
719 buses = (buses & 0xff00ffff)
720 | ((unsigned int)(child->subordinate) << 16);
721 pcibios_write_config_dword(bus->number, devfn, 0x18,
722 buses);
723 }
724 }
725
726
727
728
729
730
731
732 return max;
733 }
734
735
736 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
737 {
738 mem_start = pcibios_init(mem_start, mem_end);
739
740 if (!pcibios_present()) {
741 printk("pci_init: no BIOS32 detected\n");
742 return mem_start;
743 }
744
745 printk("Probing PCI hardware.\n");
746
747 memset(&pci_root, 0, sizeof(pci_root));
748 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
749
750
751 mem_start = pcibios_fixup(mem_start, mem_end);
752
753 #ifdef DEBUG
754 {
755 int len = get_pci_list(mem_start);
756 if (len) {
757 ((char*)mem_start)[len] = '\0';
758 printk("%s\n", mem_start);
759 }
760 }
761 #endif
762 return mem_start;
763 }
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