root/arch/alpha/kernel/bios32.c

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DEFINITIONS

This source file includes following definitions.
  1. pcibios_present
  2. disable_dev
  3. layout_dev
  4. layout_bus
  5. pcibios_find_device
  6. pcibios_find_class
  7. pcibios_present
  8. pcibios_init
  9. enable_ide
  10. common_fixup
  11. eb66p_fixup
  12. cabriolet_fixup
  13. eb66_and_eb64p_fixup
  14. sio_fixup
  15. pcibios_fixup
  16. pcibios_strerror

   1 /*
   2  * bios32.c - PCI BIOS functions for Alpha systems not using BIOS
   3  *            emulation code.
   4  *
   5  * Written by Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *
   7  * Adapted to 64-bit kernel and then rewritten by David Mosberger
   8  * (davidm@cs.arizona.edu)
   9  *
  10  * For more information, please consult
  11  *
  12  * PCI BIOS Specification Revision
  13  * PCI Local Bus Specification
  14  * PCI System Design Guide
  15  *
  16  * PCI Special Interest Group
  17  * M/S HF3-15A
  18  * 5200 N.E. Elam Young Parkway
  19  * Hillsboro, Oregon 97124-6497
  20  * +1 (503) 696-2000
  21  * +1 (800) 433-5177
  22  *
  23  * Manuals are $25 each or $50 for all three, plus $7 shipping
  24  * within the United States, $35 abroad.
  25  */
  26 #include <linux/config.h>
  27 
  28 #ifndef CONFIG_PCI
  29 
  30 int pcibios_present(void)
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  31 {
  32         return 0;
  33 }
  34 
  35 #else /* CONFIG_PCI */
  36 
  37 #include <linux/kernel.h>
  38 #include <linux/bios32.h>
  39 #include <linux/pci.h>
  40 #include <linux/malloc.h>
  41 #include <linux/mm.h>
  42 
  43 #include <asm/hwrpb.h>
  44 #include <asm/io.h>
  45 
  46 
  47 #define KB              1024
  48 #define MB              (1024*KB)
  49 #define GB              (1024*MB)
  50 
  51 #define MAJOR_REV       0
  52 #define MINOR_REV       3
  53 
  54 /*
  55  * Align VAL to ALIGN, which must be a power of two.
  56  */
  57 #define ALIGN(val,align)        (((val) + ((align) - 1)) & ~((align) - 1))
  58 
  59 
  60 /*
  61  * Temporary internal macro.  If this 0, then do not write to any of
  62  * the PCI registers, merely read them (i.e., use configuration as
  63  * determined by SRM).  The SRM seem do be doing a less than perfect
  64  * job in configuring PCI devices, so for now we do it ourselves.
  65  * Reconfiguring PCI devices breaks console (RPB) callbacks, but
  66  * those don't work properly with 64 bit addresses anyways.
  67  *
  68  * The accepted convention seems to be that the console (POST
  69  * software) should fully configure boot devices and configure the
  70  * interrupt routing of *all* devices.  In particular, the base
  71  * addresses of non-boot devices need not be initialized.  For
  72  * example, on the AXPpci33 board, the base address a #9 GXE PCI
  73  * graphics card reads as zero (this may, however, be due to a bug in
  74  * the graphics card---there have been some rumor that the #9 BIOS
  75  * incorrectly resets that address to 0...).
  76  */
  77 #define PCI_MODIFY              1
  78 
  79 extern struct hwrpb_struct *hwrpb;
  80 
  81 
  82 #if PCI_MODIFY
  83 
  84 static unsigned int     io_base  = 64*KB;       /* <64KB are (E)ISA ports */
  85 static unsigned int     mem_base = 16*MB;       /* <16MB is ISA memory */
  86 
  87 /*
  88  * Disable PCI device DEV so that it does not respond to I/O or memory
  89  * accesses.
  90  */
  91 static void disable_dev(struct pci_dev *dev)
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  92 {
  93         struct pci_bus *bus;
  94         unsigned short cmd;
  95 
  96         bus = dev->bus;
  97         pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
  98 
  99         /* hack, turn it off first... */
 100         cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
 101         pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND, cmd);
 102 }
 103 
 104 
 105 /*
 106  * Layout memory and I/O for a device:
 107  */
 108 #define MAX(val1, val2) ( ((val1) > (val2)) ? val1 : val2)
 109 
 110 static void layout_dev(struct pci_dev *dev)
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 111 {
 112         struct pci_bus *bus;
 113         unsigned short cmd;
 114         unsigned int base, mask, size, reg;
 115         unsigned int alignto;
 116 
 117         bus = dev->bus;
 118         pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
 119 
 120         for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
 121                 /*
 122                  * Figure out how much space and of what type this
 123                  * device wants.
 124                  */
 125                 pcibios_write_config_dword(bus->number, dev->devfn, reg,
 126                                            0xffffffff);
 127                 pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
 128                 if (!base) {
 129                         /* this base-address register is unused */
 130                         continue;
 131                 }
 132 
 133                 /*
 134                  * We've read the base address register back after
 135                  * writing all ones and so now we must decode it.
 136                  */
 137                 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
 138                         /*
 139                          * I/O space base address register.
 140                          */
 141                         cmd |= PCI_COMMAND_IO;
 142 
 143                         base &= PCI_BASE_ADDRESS_IO_MASK;
 144                         mask = (~base << 1) | 0x1;
 145                         size = (mask & base) & 0xffffffff;
 146                         /* align to multiple of size of minimum base */
 147                         alignto = MAX(0x400, size) ;
 148                         base = ALIGN(io_base, alignto );
 149                         io_base = base + size;
 150                         pcibios_write_config_dword(bus->number, dev->devfn, 
 151                                                    reg, base | 0x1);
 152                 } else {
 153                         unsigned int type;
 154                         /*
 155                          * Memory space base address register.
 156                          */
 157                         cmd |= PCI_COMMAND_MEMORY;
 158                         type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 159                         base &= PCI_BASE_ADDRESS_MEM_MASK;
 160                         mask = (~base << 1) | 0x1;
 161                         size = (mask & base) & 0xffffffff;
 162                         switch (type) {
 163                               case PCI_BASE_ADDRESS_MEM_TYPE_32:
 164                                 break;
 165 
 166                               case PCI_BASE_ADDRESS_MEM_TYPE_64:
 167                                 printk("bios32 WARNING: "
 168                                        "ignoring 64-bit device in "
 169                                        "slot %d, function %d: \n",
 170                                        PCI_SLOT(dev->devfn),
 171                                        PCI_FUNC(dev->devfn));
 172                                 reg += 4;       /* skip extra 4 bytes */
 173                                 continue;
 174 
 175                               case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 176                                 /*
 177                                  * Allocating memory below 1MB is *very*
 178                                  * tricky, as there may be all kinds of
 179                                  * ISA devices lurking that we don't know
 180                                  * about.  For now, we just cross fingers
 181                                  * and hope nobody tries to do this on an
 182                                  * Alpha (or that the console has set it
 183                                  * up properly).
 184                                  */
 185                                 printk("bios32 WARNING: slot %d, function %d "
 186                                        "requests memory below 1MB---don't "
 187                                        "know how to do that.\n",
 188                                        PCI_SLOT(dev->devfn),
 189                                        PCI_FUNC(dev->devfn));
 190                                 continue;
 191                         }
 192                         /*
 193                          * The following holds at least for the Low Cost
 194                          * Alpha implementation of the PCI interface:
 195                          *
 196                          * In sparse memory address space, the first
 197                          * octant (16MB) of every 128MB segment is
 198                          * aliased to the the very first 16MB of the
 199                          * address space (i.e., it aliases the ISA
 200                          * memory address space).  Thus, we try to
 201                          * avoid allocating PCI devices in that range.
 202                          * Can be allocated in 2nd-7th octant only.
 203                          * Devices that need more than 112MB of
 204                          * address space must be accessed through
 205                          * dense memory space only!
 206                          */
 207                         /* align to multiple of size of minimum base */
 208                         alignto = MAX(0x1000, size) ;
 209                         base = ALIGN(mem_base, alignto);
 210                         if (size > 7 * 16*MB) {
 211                                 printk("bios32 WARNING: slot %d, function %d "
 212                                        "requests  %dB of contiguous address "
 213                                        " space---don't use sparse memory "
 214                                        " accesses on this device!!\n",
 215                                        PCI_SLOT(dev->devfn),
 216                                        PCI_FUNC(dev->devfn), size);
 217                         } else {
 218                                 if (((base / (16*MB)) & 0x7) == 0) {
 219                                         base &= ~(128*MB - 1);
 220                                         base += 16*MB;
 221                                         base  = ALIGN(base, alignto);
 222                                 }
 223                                 if (base / (128*MB) != (base + size) / (128*MB)) {
 224                                         base &= ~(128*MB - 1);
 225                                         base += (128 + 16)*MB;
 226                                         base  = ALIGN(base, alignto);
 227                                 }
 228                         }
 229                         mem_base = base + size;
 230                         pcibios_write_config_dword(bus->number, dev->devfn,
 231                                                    reg, base);
 232                 }
 233         }
 234         /* enable device: */
 235         if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
 236             dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
 237             dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
 238             dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
 239         {
 240                 /*
 241                  * All of these (may) have I/O scattered all around
 242                  * and may not use i/o-base address registers at all.
 243                  * So we just have to always enable I/O to these
 244                  * devices.
 245                  */
 246                 cmd |= PCI_COMMAND_IO;
 247         }
 248 
 249         pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
 250                                   cmd | PCI_COMMAND_MASTER);
 251 }
 252 
 253 
 254 static void layout_bus(struct pci_bus *bus)
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 255 {
 256         unsigned int l, tio, bio, tmem, bmem;
 257         struct pci_bus *child;
 258         struct pci_dev *dev;
 259 
 260         if (!bus->devices && !bus->children)
 261           return;
 262 
 263         /*
 264          * Align the current bases on appropriate boundaries (4K for
 265          * IO and 1MB for memory).
 266          */
 267         bio = io_base = ALIGN(io_base, 4*KB);
 268         bmem = mem_base = ALIGN(mem_base, 1*MB);
 269 
 270         /*
 271          * There are times when the PCI devices have already been
 272          * setup (e.g., by MILO or SRM).  In these cases there is a
 273          * window during which two devices may have an overlapping
 274          * address range.  To avoid this causing trouble, we first
 275          * turn off the I/O and memory address decoders for all PCI
 276          * devices.  They'll be re-enabled only once all address
 277          * decoders are programmed consistently.
 278          */
 279         for (dev = bus->devices; dev; dev = dev->sibling) {
 280                 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
 281                         disable_dev(dev) ;
 282                 }
 283         }
 284 
 285         /*
 286          * Allocate space to each device:
 287          */
 288         for (dev = bus->devices; dev; dev = dev->sibling) {
 289                 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
 290                         layout_dev(dev);
 291                 }
 292         }
 293         /*
 294          * Recursively allocate space for all of the sub-buses:
 295          */
 296         for (child = bus->children; child; child = child->next) {
 297                 layout_bus(child);
 298         }
 299         /*
 300          * Align the current bases on 4K and 1MB boundaries:
 301          */
 302         tio = io_base = ALIGN(io_base, 4*KB);
 303         tmem = mem_base = ALIGN(mem_base, 1*MB);
 304 
 305         if (bus->self) {
 306                 struct pci_dev *bridge = bus->self;
 307                 /*
 308                  * Set up the top and bottom of the I/O memory segment
 309                  * for this bus.
 310                  */
 311                 pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
 312                                           0x1c, &l);
 313                 l = l | (bio >> 8) | ((tio - 1) & 0xf000);
 314                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 315                                            0x1c, l);
 316 
 317                 l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
 318                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 319                                            0x20, l);
 320                 /*
 321                  * Turn off downstream PF memory address range:
 322                  */
 323                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 324                                            0x24, 0x0000ffff);
 325                 /*
 326                  * Tell bridge that there is an ISA bus in the system:
 327                  */
 328                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 329                                            0x3c, 0x00040000);
 330                 /*
 331                  * Clear status bits, enable I/O (for downstream I/O),
 332                  * turn on master enable (for upstream I/O), turn on
 333                  * memory enable (for downstream memory), turn on
 334                  * master enable (for upstream memory and I/O).
 335                  */
 336                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 337                                            0x4, 0xffff0007);
 338         }
 339 }
 340 
 341 #endif /* !PCI_MODIFY */
 342 
 343 
 344 /*
 345  * Given the vendor and device ids, find the n'th instance of that device
 346  * in the system.  
 347  */
 348 int pcibios_find_device (unsigned short vendor, unsigned short device_id,
     /* [previous][next][first][last][top][bottom][index][help] */
 349                          unsigned short index, unsigned char *bus,
 350                          unsigned char *devfn)
 351 {
 352         unsigned int curr = 0;
 353         struct pci_dev *dev;
 354 
 355         for (dev = pci_devices; dev; dev = dev->next) {
 356                 if (dev->vendor == vendor && dev->device == device_id) {
 357                         if (curr == index) {
 358                                 *devfn = dev->devfn;
 359                                 *bus = dev->bus->number;
 360                                 return PCIBIOS_SUCCESSFUL;
 361                         }
 362                         ++curr;
 363                 }
 364         }
 365         return PCIBIOS_DEVICE_NOT_FOUND;
 366 }
 367 
 368 
 369 /*
 370  * Given the class, find the n'th instance of that device
 371  * in the system.
 372  */
 373 int pcibios_find_class (unsigned int class_code, unsigned short index,
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 374                         unsigned char *bus, unsigned char *devfn)
 375 {
 376         unsigned int curr = 0;
 377         struct pci_dev *dev;
 378 
 379         for (dev = pci_devices; dev; dev = dev->next) {
 380                 if (dev->class == class_code) {
 381                         if (curr == index) {
 382                                 *devfn = dev->devfn;
 383                                 *bus = dev->bus->number;
 384                                 return PCIBIOS_SUCCESSFUL;
 385                         }
 386                         ++curr;
 387                 }
 388         }
 389         return PCIBIOS_DEVICE_NOT_FOUND;
 390 }
 391 
 392 
 393 int pcibios_present(void)
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 394 {
 395         return 1;
 396 }
 397 
 398 
 399 unsigned long pcibios_init(unsigned long mem_start,
     /* [previous][next][first][last][top][bottom][index][help] */
 400                            unsigned long mem_end)
 401 {
 402         printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
 403 
 404 #if !PCI_MODIFY
 405         printk("...NOT modifying existing (SRM) PCI configuration\n");
 406 #endif
 407         return mem_start;
 408 }
 409 
 410 /*
 411  * The SRM console *disables* the IDE interface, this code ensures its
 412  * enabled.
 413  *
 414  * This code bangs on a control register of the 87312 Super I/O chip
 415  * that implements parallel port/serial ports/IDE/FDI.  Depending on
 416  * the motherboard, the Super I/O chip can be configured through a
 417  * pair of registers that are located either at I/O ports 0x26e/0x26f
 418  * or 0x398/0x399.  Unfortunately, autodetecting which base address is
 419  * in use works only once (right after a reset).  The Super I/O chip
 420  * has the additional quirk that configuration register data must be
 421  * written twice (I believe this is a saftey feature to prevent
 422  * accidental modification---fun, isn't it?).
 423  */
 424 static inline void enable_ide(long ide_base)
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 425 {
 426         int data;
 427 
 428         outb(0, ide_base);              /* set the index register for reg #0 */
 429         data = inb(ide_base+1);         /* read the current contents */
 430         outb(0, ide_base);              /* set the index register for reg #0 */
 431         outb(data | 0x40, ide_base+1);  /* turn on IDE */
 432         outb(data | 0x40, ide_base+1);  /* turn on IDE, really! */
 433 }
 434 
 435 /*
 436  * Most evaluation boards share most of the fixup code, which is isolated here.
 437  * This function is declared "inline" as only one platform will ever be selected
 438  * in any given kernel.  If that platform doesn't need this code, we don't want
 439  * it around as dead code.
 440  */
 441 static inline void common_fixup(long min_idsel, long max_idsel, long irqs_per_slot,
     /* [previous][next][first][last][top][bottom][index][help] */
 442                                 char irq_tab[max_idsel - min_idsel + 1][irqs_per_slot],
 443                                 long ide_base)
 444 {
 445         struct pci_dev *dev;
 446         unsigned char pin;
 447 
 448         /*
 449          * Go through all devices, fixing up irqs as we see fit:
 450          */
 451         for (dev = pci_devices; dev; dev = dev->next) {
 452                 dev->irq = 0;
 453                 /*
 454                  * Ignore things not on the primary bus - I'll figure
 455                  * this out one day - Dave Rusling
 456                  */
 457                 if (dev->bus->number != 0)
 458                         continue;
 459 
 460                 /* read the pin */
 461                 pcibios_read_config_byte(dev->bus->number, dev->devfn,
 462                                          PCI_INTERRUPT_PIN, &pin);
 463                 if (irq_tab[PCI_SLOT(dev->devfn) - min_idsel][pin] != -1)
 464                         dev->irq = irq_tab[PCI_SLOT(dev->devfn) - min_idsel][pin];
 465 #if PCI_MODIFY
 466                 /* tell the device: */
 467                 pcibios_write_config_byte(dev->bus->number, dev->devfn,
 468                                           PCI_INTERRUPT_LINE, dev->irq);
 469 #endif
 470                 /*
 471                  * if its a VGA, enable its BIOS ROM at C0000
 472                  */
 473                 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
 474                         pcibios_write_config_dword(dev->bus->number, dev->devfn,
 475                                                    PCI_ROM_ADDRESS,
 476                                                    0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
 477                 }
 478         }
 479         if (ide_base) {
 480                 enable_ide(ide_base);
 481         }
 482 }
 483 
 484 /*
 485  * The EB66+ is very similar to the EB66 except that it does not have
 486  * the on-board NCR and Tulip chips.  In the code below, I have used
 487  * slot number to refer to the id select line and *not* the slot
 488  * number used in the EB66+ documentation.  However, in the table,
 489  * I've given the slot number, the id select line and the Jxx number
 490  * that's printed on the board.  The interrupt pins from the PCI slots
 491  * are wired into 3 interrupt summary registers at 0x804, 0x805 and
 492  * 0x806 ISA.
 493  *
 494  * In the table, -1 means don't assign an IRQ number.  This is usually
 495  * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 496  */
 497 static inline void eb66p_fixup(void)
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 498 {
 499         char irq_tab[5][5] = {
 500                 {16+0, 16+0, 16+5,  16+9, 16+13},       /* IdSel 6,  slot 0, J25 */
 501                 {16+1, 16+1, 16+6, 16+10, 16+14},       /* IdSel 7,  slot 1, J26 */
 502                 {  -1,   -1,   -1,    -1,    -1},       /* IdSel 8,  SIO         */
 503                 {16+2, 16+2, 16+7, 16+11, 16+15},       /* IdSel 9,  slot 2, J27 */
 504                 {16+3, 16+3, 16+8, 16+12,  16+6}        /* IdSel 10, slot 3, J28 */
 505         };
 506         common_fixup(6, 10, 5, irq_tab, 0x398);
 507 }
 508 
 509 
 510 /*
 511  * The AlphaPC64 is very similar to the EB66+ except that its slots
 512  * are numbered differently.  In the code below, I have used slot
 513  * number to refer to the id select line and *not* the slot number
 514  * used in the AlphaPC64 documentation.  However, in the table, I've
 515  * given the slot number, the id select line and the Jxx number that's
 516  * printed on the board.  The interrupt pins from the PCI slots are
 517  * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
 518  * ISA.
 519  *
 520  * In the table, -1 means don't assign an IRQ number.  This is usually
 521  * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 522  */
 523 static inline void cabriolet_fixup(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 524 {
 525         char irq_tab[5][5] = {
 526                 { 16+2, 16+2, 16+7, 16+11, 16+15},      /* IdSel 5,  slot 2, J21 */
 527                 { 16+0, 16+0, 16+5,  16+9, 16+13},      /* IdSel 6,  slot 0, J19 */
 528                 { 16+1, 16+1, 16+6, 16+10, 16+14},      /* IdSel 7,  slot 1, J20 */
 529                 {   -1,   -1,   -1,    -1,    -1},      /* IdSel 8,  SIO         */
 530                 { 16+3, 16+3, 16+8, 16+12, 16+16}       /* IdSel 9,  slot 3, J22 */
 531         };
 532 
 533         common_fixup(5, 9, 5, irq_tab, 0x398);
 534 }
 535 
 536 
 537 /*
 538  * Fixup configuration for EB66/EB64+ boards.
 539  *
 540  * Both these boards use the same interrupt summary scheme.  There are
 541  * two 8 bit external summary registers as follows:
 542  *
 543  * Summary @ 0x26:
 544  * Bit      Meaning
 545  * 0        Interrupt Line A from slot 0
 546  * 1        Interrupt Line A from slot 1
 547  * 2        Interrupt Line B from slot 0
 548  * 3        Interrupt Line B from slot 1
 549  * 4        Interrupt Line C from slot 0
 550  * 5        Interrupt line from the two ISA PICs
 551  * 6        Tulip (slot 
 552  * 7        NCR SCSI
 553  *
 554  * Summary @ 0x27
 555  * Bit      Meaning
 556  * 0        Interrupt Line C from slot 1
 557  * 1        Interrupt Line D from slot 0
 558  * 2        Interrupt Line D from slot 1
 559  * 3        RAZ
 560  * 4        RAZ
 561  * 5        RAZ
 562  * 6        RAZ
 563  * 7        RAZ
 564  *
 565  * The device to slot mapping looks like:
 566  *
 567  * Slot     Device
 568  *  5       NCR SCSI controller
 569  *  6       PCI on board slot 0
 570  *  7       PCI on board slot 1
 571  *  8       Intel SIO PCI-ISA bridge chip
 572  *  9       Tulip - DECchip 21040 ethernet controller
 573  *   
 574  *
 575  * This two layered interrupt approach means that we allocate IRQ 16 and 
 576  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 577  * comes in on.  This makes interrupt processing much easier.
 578  */
 579 static inline void eb66_and_eb64p_fixup(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 580 {
 581         char irq_tab[5][5] = {
 582                 {16+7, 16+7, 16+7, 16+7,  16+7},        /* IdSel 5,  slot ?, ?? */
 583                 {16+0, 16+0, 16+2, 16+4,  16+9},        /* IdSel 6,  slot ?, ?? */
 584                 {16+1, 16+1, 16+3, 16+8, 16+10},        /* IdSel 7,  slot ?, ?? */
 585                 {  -1,   -1,   -1,   -1,    -1},        /* IdSel 8,  SIO */
 586                 {16+6, 16+6, 16+6, 16+6,  16+6},        /* IdSel 9,  TULIP */
 587         };
 588         common_fixup(5, 9, 5, irq_tab, 0);
 589 }
 590 
 591 
 592 /*
 593  * Fixup configuration for all boards that route the PCI interrupts
 594  * through the SIO PCI/ISA bridge.  This includes Noname (AXPpci33),
 595  * Avanti (AlphaStation) and Kenetics's Platform 2000.
 596  */
 597 static inline void sio_fixup(void)
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 598 {
 599         struct pci_dev *dev;
 600         /*
 601          * The Noname board has 5 PCI slots with each of the 4
 602          * interrupt pins routed to different pins on the PCI/ISA
 603          * bridge (PIRQ0-PIRQ3).  The table below is based on
 604          * information available at:
 605          *
 606          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 607          *
 608          * I have no information on the Avanti interrupt routing, but
 609          * the routing seems to be identical to the Noname except
 610          * that the Avanti has an additional slot whose routing I'm
 611          * unsure of.
 612          *
 613          * pirq_tab[0] is a fake entry to deal with old PCI boards
 614          * that have the interrupt pin number hardwired to 0 (meaning
 615          * that they use the default INTA line, if they are interrupt
 616          * driven at all).
 617          */
 618         static const char pirq_tab[][5] = {
 619 #ifdef CONFIG_ALPHA_P2K
 620                 { 0,  0, -1, -1, -1}, /* idsel  6 (53c810) */
 621                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 622                 { 1,  1,  2,  3,  0}, /* idsel  8 (slot A) */
 623                 { 2,  2,  3,  0,  1}, /* idsel  9 (slot B) */
 624                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 625                 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
 626                 { 3,  3, -1, -1, -1}, /* idsel 12 (CMD0646) */
 627 #else
 628                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */ 
 629                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 630                 { 2,  2, -1, -1, -1}, /* idsel  8 (Noname hack: slot closest to ISA) */
 631                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 632                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 633                 { 0,  0,  2,  1,  0}, /* idsel 11 KN25_PCI_SLOT0 */
 634                 { 1,  1,  0,  2,  1}, /* idsel 12 KN25_PCI_SLOT1 */
 635                 { 2,  2,  1,  0,  2}, /* idsel 13 KN25_PCI_SLOT2 */
 636 #endif
 637         };
 638         /*
 639          * route_tab selects irq routing in PCI/ISA bridge so that:
 640          *              PIRQ0 -> irq 15
 641          *              PIRQ1 -> irq  9
 642          *              PIRQ2 -> irq 10
 643          *              PIRQ3 -> irq 11
 644          *
 645          * This probably ought to be configurable via MILO.  For
 646          * example, sound boards seem to like using IRQ 9.
 647          */
 648         const unsigned int route_tab = 0x0b0a090f;
 649         unsigned int level_bits;
 650         unsigned char pin;
 651         int pirq;
 652 
 653         pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
 654 
 655         /*
 656          * Go through all devices, fixing up irqs as we see fit:
 657          */
 658         level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
 659         for (dev = pci_devices; dev; dev = dev->next) {
 660                 dev->irq = 0;
 661                 if (dev->bus->number != 0) {
 662                         printk("bios32.sio_fixup: don't know how to fixup devices on bus %d\n",
 663                                dev->bus->number);
 664                         continue;
 665                 }
 666                 if (PCI_SLOT(dev->devfn) < 6 ||
 667                     PCI_SLOT(dev->devfn) >= 6 + sizeof(pirq_tab)/sizeof(pirq_tab[0]))
 668                 {
 669                         printk("bios32.sio_fixup: "
 670                                "weird, found device %04x:%04x in non-existent slot %d!!\n",
 671                                dev->vendor, dev->device, PCI_SLOT(dev->devfn));
 672                         continue;
 673                 }
 674                 pcibios_read_config_byte(dev->bus->number, dev->devfn,
 675                                          PCI_INTERRUPT_PIN, &pin);
 676                 pirq = pirq_tab[PCI_SLOT(dev->devfn) - 6][pin];
 677                 if (pirq < 0) {
 678                         continue;
 679                 }
 680 
 681                 /*
 682                  * if its a VGA, enable its BIOS ROM at C0000
 683                  */
 684                 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
 685                         pcibios_write_config_dword(dev->bus->number, dev->devfn,
 686                                                    PCI_ROM_ADDRESS,
 687                                                    0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
 688                 }
 689                 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
 690                         continue; /* for now, displays get no IRQ */
 691                 }
 692                 dev->irq = (route_tab >> (8 * pirq)) & 0xff;
 693 
 694                 /* must set the PCI IRQs to level triggered */
 695                 level_bits |= (1 << dev->irq);
 696 
 697 #if PCI_MODIFY
 698                 /* tell the device: */
 699                 pcibios_write_config_byte(dev->bus->number, dev->devfn,
 700                                           PCI_INTERRUPT_LINE, dev->irq);
 701 #endif
 702         }
 703         /*
 704          * Now, make all PCI interrupts level sensitive.  Notice:
 705          * these registers must be accessed byte-wise.  outw() doesn't
 706          * work.
 707          */
 708         outb((level_bits >> 0) & 0xff, 0x4d0);
 709         outb((level_bits >> 8) & 0xff, 0x4d1);
 710         enable_ide(0x26e);
 711 }
 712 
 713 
 714 #ifdef CONFIG_TGA_CONSOLE
 715 extern void tga_console_init(void);
 716 #endif /* CONFIG_TGA_CONSOLE */
 717 
 718 unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
     /* [previous][next][first][last][top][bottom][index][help] */
 719 {
 720 #if PCI_MODIFY
 721         /*
 722          * Scan the tree, allocating PCI memory and I/O space.
 723          */
 724         layout_bus(&pci_root);
 725 #endif
 726         
 727         /*
 728          * Now is the time to do all those dirty little deeds...
 729          */
 730 #if defined(CONFIG_ALPHA_NONAME) || defined(CONFIG_ALPHA_AVANTI) || defined(CONFIG_ALPHA_P2K)
 731         sio_fixup();
 732 #elif defined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB164)
 733         cabriolet_fixup();
 734 #elif defined(CONFIG_ALPHA_EB66P)
 735         eb66p_fixup();
 736 #elif defined(CONFIG_ALPHA_EB66)
 737         eb66_and_eb64p_fixup();
 738 #elif defined(CONFIG_ALPHA_EB64P)
 739         eb66_and_eb64p_fixup();
 740 #else
 741 #       error You must tell me what kind of platform you want.
 742 #endif
 743 
 744 #ifdef CONFIG_TGA_CONSOLE
 745         tga_console_init();
 746 #endif /* CONFIG_TGA_CONSOLE */
 747 
 748         return mem_start;
 749 }
 750 
 751 
 752 const char *pcibios_strerror (int error)
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 753 {
 754         static char buf[80];
 755 
 756         switch (error) {
 757                 case PCIBIOS_SUCCESSFUL:
 758                         return "SUCCESSFUL";
 759 
 760                 case PCIBIOS_FUNC_NOT_SUPPORTED:
 761                         return "FUNC_NOT_SUPPORTED";
 762 
 763                 case PCIBIOS_BAD_VENDOR_ID:
 764                         return "SUCCESSFUL";
 765 
 766                 case PCIBIOS_DEVICE_NOT_FOUND:
 767                         return "DEVICE_NOT_FOUND";
 768 
 769                 case PCIBIOS_BAD_REGISTER_NUMBER:
 770                         return "BAD_REGISTER_NUMBER";
 771 
 772                 default:
 773                         sprintf (buf, "UNKNOWN RETURN 0x%x", error);
 774                         return buf;
 775         }
 776 }
 777 
 778 #endif /* CONFIG_PCI */

/* [previous][next][first][last][top][bottom][index][help] */