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*/
1 /*
2 * include/asm-alpha/dma.h
3 *
4 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
5 * use ISA-compatible dma. The only extension is support for high-page
6 * registers that allow to set the top 8 bits of a 32-bit DMA address.
7 * This register should be written last when setting up a DMA address
8 * as this will also enable DMA across 64 KB boundaries.
9 */
10
11 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
12 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
13 * Written by Hennus Bergman, 1992.
14 * High DMA channel support & info by Hannu Savolainen
15 * and John Boyd, Nov. 1992.
16 */
17
18 #ifndef _ASM_DMA_H
19 #define _ASM_DMA_H
20
21 #include <linux/config.h>
22
23 #include <asm/io.h> /* need byte IO */
24
25 #define dma_outb outb
26 #define dma_inb inb
27
28 /*
29 * NOTES about DMA transfers:
30 *
31 * controller 1: channels 0-3, byte operations, ports 00-1F
32 * controller 2: channels 4-7, word operations, ports C0-DF
33 *
34 * - ALL registers are 8 bits only, regardless of transfer size
35 * - channel 4 is not used - cascades 1 into 2.
36 * - channels 0-3 are byte - addresses/counts are for physical bytes
37 * - channels 5-7 are word - addresses/counts are for physical words
38 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
39 * - transfer count loaded to registers is 1 less than actual count
40 * - controller 2 offsets are all even (2x offsets for controller 1)
41 * - page registers for 5-7 don't use data bit 0, represent 128K pages
42 * - page registers for 0-3 use bit 0, represent 64K pages
43 *
44 * DMA transfers are limited to the lower 16MB of _physical_ memory.
45 * Note that addresses loaded into registers must be _physical_ addresses,
46 * not logical addresses (which may differ if paging is active).
47 *
48 * Address mapping for channels 0-3:
49 *
50 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
51 * | ... | | ... | | ... |
52 * | ... | | ... | | ... |
53 * | ... | | ... | | ... |
54 * P7 ... P0 A7 ... A0 A7 ... A0
55 * | Page | Addr MSB | Addr LSB | (DMA registers)
56 *
57 * Address mapping for channels 5-7:
58 *
59 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
60 * | ... | \ \ ... \ \ \ ... \ \
61 * | ... | \ \ ... \ \ \ ... \ (not used)
62 * | ... | \ \ ... \ \ \ ... \
63 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
64 * | Page | Addr MSB | Addr LSB | (DMA registers)
65 *
66 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
67 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
68 * the hardware level, so odd-byte transfers aren't possible).
69 *
70 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
71 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
72 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
73 *
74 */
75
76 #define MAX_DMA_CHANNELS 8
77
78 #ifdef CONFIG_ALPHA_XL
79 /* The maximum address that we can perform a DMA transfer to on Alpha XL,
80 due to a hardware SIO (PCI<->ISA bus bridge) chip limitation, is 64MB.
81 see <asm/apecs.h> for more info */
82 #define MAX_DMA_ADDRESS (0xfffffc0004000000UL)
83 #else /* CONFIG_ALPHA_XL */
84 /* The maximum address that we can perform a DMA transfer to on normal
85 Alpha platforms */
86 #define MAX_DMA_ADDRESS (~0UL)
87 #endif /* CONFIG_ALPHA_XL */
88
89 /* 8237 DMA controllers */
90 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
91 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
92
93 /* DMA controller registers */
94 #define DMA1_CMD_REG 0x08 /* command register (w) */
95 #define DMA1_STAT_REG 0x08 /* status register (r) */
96 #define DMA1_REQ_REG 0x09 /* request register (w) */
97 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
98 #define DMA1_MODE_REG 0x0B /* mode register (w) */
99 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
100 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
101 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
102 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
103 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
104 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
105
106 #define DMA2_CMD_REG 0xD0 /* command register (w) */
107 #define DMA2_STAT_REG 0xD0 /* status register (r) */
108 #define DMA2_REQ_REG 0xD2 /* request register (w) */
109 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
110 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
111 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
112 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
113 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
114 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
115 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
116 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
117
118 #define DMA_ADDR_0 0x00 /* DMA address registers */
119 #define DMA_ADDR_1 0x02
120 #define DMA_ADDR_2 0x04
121 #define DMA_ADDR_3 0x06
122 #define DMA_ADDR_4 0xC0
123 #define DMA_ADDR_5 0xC4
124 #define DMA_ADDR_6 0xC8
125 #define DMA_ADDR_7 0xCC
126
127 #define DMA_CNT_0 0x01 /* DMA count registers */
128 #define DMA_CNT_1 0x03
129 #define DMA_CNT_2 0x05
130 #define DMA_CNT_3 0x07
131 #define DMA_CNT_4 0xC2
132 #define DMA_CNT_5 0xC6
133 #define DMA_CNT_6 0xCA
134 #define DMA_CNT_7 0xCE
135
136 #define DMA_PAGE_0 0x87 /* DMA page registers */
137 #define DMA_PAGE_1 0x83
138 #define DMA_PAGE_2 0x81
139 #define DMA_PAGE_3 0x82
140 #define DMA_PAGE_5 0x8B
141 #define DMA_PAGE_6 0x89
142 #define DMA_PAGE_7 0x8A
143
144 #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
145 #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
146 #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
147 #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
148 #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
149 #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
150 #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
151 #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7)
152
153 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
154 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
155 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
156
157 /* enable/disable a specific DMA channel */
158 static __inline__ void enable_dma(unsigned int dmanr)
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*/
159 {
160 if (dmanr<=3)
161 dma_outb(dmanr, DMA1_MASK_REG);
162 else
163 dma_outb(dmanr & 3, DMA2_MASK_REG);
164 }
165
166 static __inline__ void disable_dma(unsigned int dmanr)
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167 {
168 if (dmanr<=3)
169 dma_outb(dmanr | 4, DMA1_MASK_REG);
170 else
171 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
172 }
173
174 /* Clear the 'DMA Pointer Flip Flop'.
175 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
176 * Use this once to initialize the FF to a known state.
177 * After that, keep track of it. :-)
178 * --- In order to do that, the DMA routines below should ---
179 * --- only be used while interrupts are disabled! ---
180 */
181 static __inline__ void clear_dma_ff(unsigned int dmanr)
/* */
182 {
183 if (dmanr<=3)
184 dma_outb(0, DMA1_CLEAR_FF_REG);
185 else
186 dma_outb(0, DMA2_CLEAR_FF_REG);
187 }
188
189 /* set mode (above) for a specific DMA channel */
190 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
/* */
191 {
192 if (dmanr<=3)
193 dma_outb(mode | dmanr, DMA1_MODE_REG);
194 else
195 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
196 }
197
198 /* set extended mode for a specific DMA channel */
199 static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
/* */
200 {
201 if (dmanr<=3)
202 dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG);
203 else
204 dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG);
205 }
206
207 /* Set only the page register bits of the transfer address.
208 * This is used for successive transfers when we know the contents of
209 * the lower 16 bits of the DMA current address register.
210 */
211 static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
/* */
212 {
213 switch(dmanr) {
214 case 0:
215 dma_outb(pagenr, DMA_PAGE_0);
216 dma_outb((pagenr >> 8), DMA_HIPAGE_0);
217 break;
218 case 1:
219 dma_outb(pagenr, DMA_PAGE_1);
220 dma_outb((pagenr >> 8), DMA_HIPAGE_1);
221 break;
222 case 2:
223 dma_outb(pagenr, DMA_PAGE_2);
224 dma_outb((pagenr >> 8), DMA_HIPAGE_2);
225 break;
226 case 3:
227 dma_outb(pagenr, DMA_PAGE_3);
228 dma_outb((pagenr >> 8), DMA_HIPAGE_3);
229 break;
230 case 5:
231 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
232 dma_outb((pagenr >> 8), DMA_HIPAGE_5);
233 break;
234 case 6:
235 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
236 dma_outb((pagenr >> 8), DMA_HIPAGE_6);
237 break;
238 case 7:
239 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
240 dma_outb((pagenr >> 8), DMA_HIPAGE_7);
241 break;
242 }
243 }
244
245
246 /* Set transfer address & page bits for specific DMA channel.
247 * Assumes dma flipflop is clear.
248 */
249 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
/* */
250 {
251 if (dmanr <= 3) {
252 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
253 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
254 } else {
255 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
256 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
257 }
258 set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */
259 }
260
261
262 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
263 * a specific DMA channel.
264 * You must ensure the parameters are valid.
265 * NOTE: from a manual: "the number of transfers is one more
266 * than the initial word count"! This is taken into account.
267 * Assumes dma flip-flop is clear.
268 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
269 */
270 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
/* */
271 {
272 count--;
273 if (dmanr <= 3) {
274 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
275 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
276 } else {
277 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
278 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
279 }
280 }
281
282
283 /* Get DMA residue count. After a DMA transfer, this
284 * should return zero. Reading this while a DMA transfer is
285 * still in progress will return unpredictable results.
286 * If called before the channel has been used, it may return 1.
287 * Otherwise, it returns the number of _bytes_ left to transfer.
288 *
289 * Assumes DMA flip-flop is clear.
290 */
291 static __inline__ int get_dma_residue(unsigned int dmanr)
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292 {
293 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
294 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
295
296 /* using short to get 16-bit wrap around */
297 unsigned short count;
298
299 count = 1 + dma_inb(io_port);
300 count += dma_inb(io_port) << 8;
301
302 return (dmanr<=3)? count : (count<<1);
303 }
304
305
306 /* These are in kernel/dma.c: */
307 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
308 extern void free_dma(unsigned int dmanr); /* release it again */
309
310
311 #endif /* _ASM_DMA_H */
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*/