![[first]](../icons/first.png){kind=icon}
![[previous]](../icons/n_left.png){kind=icon}
![[next]](../icons/n_right.png){kind=icon}
![[last]](../icons/last.png){kind=icon}
![[top]](../icons/n_top.png){kind=icon}
![[bottom]](../icons/bottom.png){kind=icon}
![[index]](../icons/index.png){kind=icon}
![[help]](../icons/help.png){kind=icon}
*/
1 /*
2 * bios32.c - PCI BIOS functions for Alpha systems not using BIOS
3 * emulation code.
4 *
5 * Written by Dave Rusling (david.rusling@reo.mts.dec.com)
6 *
7 * Adapted to 64-bit kernel and then rewritten by David Mosberger
8 * (davidm@cs.arizona.edu)
9 *
10 * For more information, please consult
11 *
12 * PCI BIOS Specification Revision
13 * PCI Local Bus Specification
14 * PCI System Design Guide
15 *
16 * PCI Special Interest Group
17 * M/S HF3-15A
18 * 5200 N.E. Elam Young Parkway
19 * Hillsboro, Oregon 97124-6497
20 * +1 (503) 696-2000
21 * +1 (800) 433-5177
22 *
23 * Manuals are $25 each or $50 for all three, plus $7 shipping
24 * within the United States, $35 abroad.
25 */
26 #include <linux/config.h>
27
28 #ifndef CONFIG_PCI
29
30 int pcibios_present(void)
/* ![[next]](../icons/right.png)
![[first]](../icons/n_first.png)
![[top]](../icons/top.png)
*/
31 {
32 return 0;
33 }
34
35 #else /* CONFIG_PCI */
36
37 #include <linux/kernel.h>
38 #include <linux/bios32.h>
39 #include <linux/pci.h>
40 #include <linux/malloc.h>
41 #include <linux/mm.h>
42
43 #include <asm/hwrpb.h>
44 #include <asm/io.h>
45
46
47 #define KB 1024
48 #define MB (1024*KB)
49 #define GB (1024*MB)
50
51 #define MAJOR_REV 0
52 #define MINOR_REV 3
53
54 /*
55 * Align VAL to ALIGN, which must be a power of two.
56 */
57 #define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
58
59
60 /*
61 * Temporary internal macro. If this 0, then do not write to any of
62 * the PCI registers, merely read them (i.e., use configuration as
63 * determined by SRM). The SRM seem do be doing a less than perfect
64 * job in configuring PCI devices, so for now we do it ourselves.
65 * Reconfiguring PCI devices breaks console (RPB) callbacks, but
66 * those don't work properly with 64 bit addresses anyways.
67 *
68 * The accepted convention seems to be that the console (POST
69 * software) should fully configure boot devices and configure the
70 * interrupt routing of *all* devices. In particular, the base
71 * addresses of non-boot devices need not be initialized. For
72 * example, on the AXPpci33 board, the base address a #9 GXE PCI
73 * graphics card reads as zero (this may, however, be due to a bug in
74 * the graphics card---there have been some rumor that the #9 BIOS
75 * incorrectly resets that address to 0...).
76 */
77 #define PCI_MODIFY 1
78
79 extern struct hwrpb_struct *hwrpb;
80
81
82 #if PCI_MODIFY
83
84 static unsigned int io_base = 64*KB; /* <64KB are (E)ISA ports */
85
86 #if defined(CONFIG_ALPHA_XL)
87 /*
88 an AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
89 that get passed through the PCI<->ISA bridge chip. Because this causes
90 us to set the PCI->Mem window bases lower than normal, we've gotta allocate
91 PCI bus devices' memory addresses *above* the PCI<->memory mapping windows,
92 so that CPU memory DMA addresses issued by a bus device don't conflict
93 with bus memory addresses, like frame buffer memory for graphics cards.
94 */
95 static unsigned int mem_base = 1024*MB;
96 #else /* CONFIG_ALPHA_XL */
97 static unsigned int mem_base = 16*MB; /* <16MB is ISA memory */
98 #endif /* CONFIG_ALPHA_XL */
99
100 /*
101 * Disable PCI device DEV so that it does not respond to I/O or memory
102 * accesses.
103 */
104 static void disable_dev(struct pci_dev *dev)
/* ![[previous]](../icons/left.png)
*/
105 {
106 struct pci_bus *bus;
107 unsigned short cmd;
108
109 bus = dev->bus;
110 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
111
112 /* hack, turn it off first... */
113 cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
114 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND, cmd);
115 }
116
117
118 /*
119 * Layout memory and I/O for a device:
120 */
121 #define MAX(val1, val2) ( ((val1) > (val2)) ? val1 : val2)
122
123 static void layout_dev(struct pci_dev *dev)
/* */
124 {
125 struct pci_bus *bus;
126 unsigned short cmd;
127 unsigned int base, mask, size, reg;
128 unsigned int alignto;
129
130 bus = dev->bus;
131 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
132
133 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
134 /*
135 * Figure out how much space and of what type this
136 * device wants.
137 */
138 pcibios_write_config_dword(bus->number, dev->devfn, reg,
139 0xffffffff);
140 pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
141 if (!base) {
142 /* this base-address register is unused */
143 continue;
144 }
145
146 /*
147 * We've read the base address register back after
148 * writing all ones and so now we must decode it.
149 */
150 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
151 /*
152 * I/O space base address register.
153 */
154 cmd |= PCI_COMMAND_IO;
155
156 base &= PCI_BASE_ADDRESS_IO_MASK;
157 mask = (~base << 1) | 0x1;
158 size = (mask & base) & 0xffffffff;
159 /* align to multiple of size of minimum base */
160 alignto = MAX(0x400, size) ;
161 base = ALIGN(io_base, alignto );
162 io_base = base + size;
163 pcibios_write_config_dword(bus->number, dev->devfn,
164 reg, base | 0x1);
165 } else {
166 unsigned int type;
167 /*
168 * Memory space base address register.
169 */
170 cmd |= PCI_COMMAND_MEMORY;
171 type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
172 base &= PCI_BASE_ADDRESS_MEM_MASK;
173 mask = (~base << 1) | 0x1;
174 size = (mask & base) & 0xffffffff;
175 switch (type) {
176 case PCI_BASE_ADDRESS_MEM_TYPE_32:
177 break;
178
179 case PCI_BASE_ADDRESS_MEM_TYPE_64:
180 printk("bios32 WARNING: "
181 "ignoring 64-bit device in "
182 "slot %d, function %d: \n",
183 PCI_SLOT(dev->devfn),
184 PCI_FUNC(dev->devfn));
185 reg += 4; /* skip extra 4 bytes */
186 continue;
187
188 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
189 /*
190 * Allocating memory below 1MB is *very*
191 * tricky, as there may be all kinds of
192 * ISA devices lurking that we don't know
193 * about. For now, we just cross fingers
194 * and hope nobody tries to do this on an
195 * Alpha (or that the console has set it
196 * up properly).
197 */
198 printk("bios32 WARNING: slot %d, function %d "
199 "requests memory below 1MB---don't "
200 "know how to do that.\n",
201 PCI_SLOT(dev->devfn),
202 PCI_FUNC(dev->devfn));
203 continue;
204 }
205 /*
206 * The following holds at least for the Low Cost
207 * Alpha implementation of the PCI interface:
208 *
209 * In sparse memory address space, the first
210 * octant (16MB) of every 128MB segment is
211 * aliased to the the very first 16MB of the
212 * address space (i.e., it aliases the ISA
213 * memory address space). Thus, we try to
214 * avoid allocating PCI devices in that range.
215 * Can be allocated in 2nd-7th octant only.
216 * Devices that need more than 112MB of
217 * address space must be accessed through
218 * dense memory space only!
219 */
220 /* align to multiple of size of minimum base */
221 alignto = MAX(0x1000, size) ;
222 base = ALIGN(mem_base, alignto);
223 if (size > 7 * 16*MB) {
224 printk("bios32 WARNING: slot %d, function %d "
225 "requests %dB of contiguous address "
226 " space---don't use sparse memory "
227 " accesses on this device!!\n",
228 PCI_SLOT(dev->devfn),
229 PCI_FUNC(dev->devfn), size);
230 } else {
231 if (((base / (16*MB)) & 0x7) == 0) {
232 base &= ~(128*MB - 1);
233 base += 16*MB;
234 base = ALIGN(base, alignto);
235 }
236 if (base / (128*MB) != (base + size) / (128*MB)) {
237 base &= ~(128*MB - 1);
238 base += (128 + 16)*MB;
239 base = ALIGN(base, alignto);
240 }
241 }
242 mem_base = base + size;
243 pcibios_write_config_dword(bus->number, dev->devfn,
244 reg, base);
245 }
246 }
247 /* enable device: */
248 if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
249 dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
250 dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
251 dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
252 {
253 /*
254 * All of these (may) have I/O scattered all around
255 * and may not use i/o-base address registers at all.
256 * So we just have to always enable I/O to these
257 * devices.
258 */
259 cmd |= PCI_COMMAND_IO;
260 }
261
262 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
263 cmd | PCI_COMMAND_MASTER);
264 }
265
266
267 static void layout_bus(struct pci_bus *bus)
/* */
268 {
269 unsigned int l, tio, bio, tmem, bmem;
270 struct pci_bus *child;
271 struct pci_dev *dev;
272
273 if (!bus->devices && !bus->children)
274 return;
275
276 /*
277 * Align the current bases on appropriate boundaries (4K for
278 * IO and 1MB for memory).
279 */
280 bio = io_base = ALIGN(io_base, 4*KB);
281 bmem = mem_base = ALIGN(mem_base, 1*MB);
282
283 /*
284 * There are times when the PCI devices have already been
285 * setup (e.g., by MILO or SRM). In these cases there is a
286 * window during which two devices may have an overlapping
287 * address range. To avoid this causing trouble, we first
288 * turn off the I/O and memory address decoders for all PCI
289 * devices. They'll be re-enabled only once all address
290 * decoders are programmed consistently.
291 */
292 for (dev = bus->devices; dev; dev = dev->sibling) {
293 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
294 disable_dev(dev) ;
295 }
296 }
297
298 /*
299 * Allocate space to each device:
300 */
301 for (dev = bus->devices; dev; dev = dev->sibling) {
302 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
303 layout_dev(dev);
304 }
305 }
306 /*
307 * Recursively allocate space for all of the sub-buses:
308 */
309 for (child = bus->children; child; child = child->next) {
310 layout_bus(child);
311 }
312 /*
313 * Align the current bases on 4K and 1MB boundaries:
314 */
315 tio = io_base = ALIGN(io_base, 4*KB);
316 tmem = mem_base = ALIGN(mem_base, 1*MB);
317
318 if (bus->self) {
319 struct pci_dev *bridge = bus->self;
320 /*
321 * Set up the top and bottom of the I/O memory segment
322 * for this bus.
323 */
324 pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
325 0x1c, &l);
326 l = l | (bio >> 8) | ((tio - 1) & 0xf000);
327 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
328 0x1c, l);
329
330 l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
331 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
332 0x20, l);
333 /*
334 * Turn off downstream PF memory address range:
335 */
336 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
337 0x24, 0x0000ffff);
338 /*
339 * Tell bridge that there is an ISA bus in the system:
340 */
341 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
342 0x3c, 0x00040000);
343 /*
344 * Clear status bits, enable I/O (for downstream I/O),
345 * turn on master enable (for upstream I/O), turn on
346 * memory enable (for downstream memory), turn on
347 * master enable (for upstream memory and I/O).
348 */
349 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
350 0x4, 0xffff0007);
351 }
352 }
353
354 #endif /* !PCI_MODIFY */
355
356
357 /*
358 * Given the vendor and device ids, find the n'th instance of that device
359 * in the system.
360 */
361 int pcibios_find_device (unsigned short vendor, unsigned short device_id,
/* */
362 unsigned short index, unsigned char *bus,
363 unsigned char *devfn)
364 {
365 unsigned int curr = 0;
366 struct pci_dev *dev;
367
368 for (dev = pci_devices; dev; dev = dev->next) {
369 if (dev->vendor == vendor && dev->device == device_id) {
370 if (curr == index) {
371 *devfn = dev->devfn;
372 *bus = dev->bus->number;
373 return PCIBIOS_SUCCESSFUL;
374 }
375 ++curr;
376 }
377 }
378 return PCIBIOS_DEVICE_NOT_FOUND;
379 }
380
381
382 /*
383 * Given the class, find the n'th instance of that device
384 * in the system.
385 */
386 int pcibios_find_class (unsigned int class_code, unsigned short index,
/* */
387 unsigned char *bus, unsigned char *devfn)
388 {
389 unsigned int curr = 0;
390 struct pci_dev *dev;
391
392 for (dev = pci_devices; dev; dev = dev->next) {
393 if (dev->class == class_code) {
394 if (curr == index) {
395 *devfn = dev->devfn;
396 *bus = dev->bus->number;
397 return PCIBIOS_SUCCESSFUL;
398 }
399 ++curr;
400 }
401 }
402 return PCIBIOS_DEVICE_NOT_FOUND;
403 }
404
405
406 int pcibios_present(void)
/* */
407 {
408 return 1;
409 }
410
411
412 unsigned long pcibios_init(unsigned long mem_start,
/* */
413 unsigned long mem_end)
414 {
415 printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
416
417 #if !PCI_MODIFY
418 printk("...NOT modifying existing (SRM) PCI configuration\n");
419 #endif
420 return mem_start;
421 }
422
423 /*
424 * The SRM console *disables* the IDE interface, this code ensures its
425 * enabled.
426 *
427 * This code bangs on a control register of the 87312 Super I/O chip
428 * that implements parallel port/serial ports/IDE/FDI. Depending on
429 * the motherboard, the Super I/O chip can be configured through a
430 * pair of registers that are located either at I/O ports 0x26e/0x26f
431 * or 0x398/0x399. Unfortunately, autodetecting which base address is
432 * in use works only once (right after a reset). The Super I/O chip
433 * has the additional quirk that configuration register data must be
434 * written twice (I believe this is a safety feature to prevent
435 * accidental modification---fun, isn't it?).
436 */
437 static inline void enable_ide(long ide_base)
/* */
438 {
439 int data;
440
441 outb(0, ide_base); /* set the index register for reg #0 */
442 data = inb(ide_base+1); /* read the current contents */
443 outb(0, ide_base); /* set the index register for reg #0 */
444 outb(data | 0x40, ide_base+1); /* turn on IDE */
445 outb(data | 0x40, ide_base+1); /* turn on IDE, really! */
446 }
447
448 /*
449 * Most evaluation boards share most of the fixup code, which is isolated here.
450 * This function is declared "inline" as only one platform will ever be selected
451 * in any given kernel. If that platform doesn't need this code, we don't want
452 * it around as dead code.
453 */
454 static inline void common_fixup(long min_idsel, long max_idsel, long irqs_per_slot,
/* */
455 char irq_tab[max_idsel - min_idsel + 1][irqs_per_slot],
456 long ide_base)
457 {
458 struct pci_dev *dev;
459 unsigned char pin;
460
461 /*
462 * Go through all devices, fixing up irqs as we see fit:
463 */
464 for (dev = pci_devices; dev; dev = dev->next) {
465 dev->irq = 0;
466 /*
467 * Ignore things not on the primary bus - I'll figure
468 * this out one day - Dave Rusling
469 */
470 if (dev->bus->number != 0)
471 continue;
472
473 /* read the pin */
474 pcibios_read_config_byte(dev->bus->number, dev->devfn,
475 PCI_INTERRUPT_PIN, &pin);
476 if (irq_tab[PCI_SLOT(dev->devfn) - min_idsel][pin] != -1)
477 dev->irq = irq_tab[PCI_SLOT(dev->devfn) - min_idsel][pin];
478 #if PCI_MODIFY
479 /* tell the device: */
480 pcibios_write_config_byte(dev->bus->number, dev->devfn,
481 PCI_INTERRUPT_LINE, dev->irq);
482 #endif
483 /*
484 * if its a VGA, enable its BIOS ROM at C0000
485 */
486 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
487 pcibios_write_config_dword(dev->bus->number, dev->devfn,
488 PCI_ROM_ADDRESS,
489 0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
490 }
491 }
492 if (ide_base) {
493 enable_ide(ide_base);
494 }
495 }
496
497 /*
498 * The EB66+ is very similar to the EB66 except that it does not have
499 * the on-board NCR and Tulip chips. In the code below, I have used
500 * slot number to refer to the id select line and *not* the slot
501 * number used in the EB66+ documentation. However, in the table,
502 * I've given the slot number, the id select line and the Jxx number
503 * that's printed on the board. The interrupt pins from the PCI slots
504 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
505 * 0x806 ISA.
506 *
507 * In the table, -1 means don't assign an IRQ number. This is usually
508 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
509 */
510 static inline void eb66p_fixup(void)
/* */
511 {
512 char irq_tab[5][5] = {
513 {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
514 {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
515 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
516 {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
517 {16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
518 };
519 common_fixup(6, 10, 5, irq_tab, 0x398);
520 }
521
522
523 /*
524 * The AlphaPC64 is very similar to the EB66+ except that its slots
525 * are numbered differently. In the code below, I have used slot
526 * number to refer to the id select line and *not* the slot number
527 * used in the AlphaPC64 documentation. However, in the table, I've
528 * given the slot number, the id select line and the Jxx number that's
529 * printed on the board. The interrupt pins from the PCI slots are
530 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
531 * ISA.
532 *
533 * In the table, -1 means don't assign an IRQ number. This is usually
534 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
535 */
536 static inline void cabriolet_fixup(void)
/* */
537 {
538 char irq_tab[5][5] = {
539 { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
540 { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
541 { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
542 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
543 { 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
544 };
545
546 common_fixup(5, 9, 5, irq_tab, 0x398);
547 }
548
549
550 /*
551 * Fixup configuration for EB66/EB64+ boards.
552 *
553 * Both these boards use the same interrupt summary scheme. There are
554 * two 8 bit external summary registers as follows:
555 *
556 * Summary @ 0x26:
557 * Bit Meaning
558 * 0 Interrupt Line A from slot 0
559 * 1 Interrupt Line A from slot 1
560 * 2 Interrupt Line B from slot 0
561 * 3 Interrupt Line B from slot 1
562 * 4 Interrupt Line C from slot 0
563 * 5 Interrupt line from the two ISA PICs
564 * 6 Tulip (slot
565 * 7 NCR SCSI
566 *
567 * Summary @ 0x27
568 * Bit Meaning
569 * 0 Interrupt Line C from slot 1
570 * 1 Interrupt Line D from slot 0
571 * 2 Interrupt Line D from slot 1
572 * 3 RAZ
573 * 4 RAZ
574 * 5 RAZ
575 * 6 RAZ
576 * 7 RAZ
577 *
578 * The device to slot mapping looks like:
579 *
580 * Slot Device
581 * 5 NCR SCSI controller
582 * 6 PCI on board slot 0
583 * 7 PCI on board slot 1
584 * 8 Intel SIO PCI-ISA bridge chip
585 * 9 Tulip - DECchip 21040 ethernet controller
586 *
587 *
588 * This two layered interrupt approach means that we allocate IRQ 16 and
589 * above for PCI interrupts. The IRQ relates to which bit the interrupt
590 * comes in on. This makes interrupt processing much easier.
591 */
592 static inline void eb66_and_eb64p_fixup(void)
/* */
593 {
594 char irq_tab[5][5] = {
595 {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */
596 {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */
597 {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */
598 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
599 {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */
600 };
601 common_fixup(5, 9, 5, irq_tab, 0);
602 }
603
604
605 /*
606 * Fixup configuration for all boards that route the PCI interrupts
607 * through the SIO PCI/ISA bridge. This includes Noname (AXPpci33),
608 * Avanti (AlphaStation) and Kenetics's Platform 2000.
609 */
610 static inline void sio_fixup(void)
/* */
611 {
612 struct pci_dev *dev;
613 /*
614 * The Noname board has 5 PCI slots with each of the 4
615 * interrupt pins routed to different pins on the PCI/ISA
616 * bridge (PIRQ0-PIRQ3). The table below is based on
617 * information available at:
618 *
619 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
620 *
621 * I have no information on the Avanti interrupt routing, but
622 * the routing seems to be identical to the Noname except
623 * that the Avanti has an additional slot whose routing I'm
624 * unsure of.
625 *
626 * pirq_tab[0] is a fake entry to deal with old PCI boards
627 * that have the interrupt pin number hardwired to 0 (meaning
628 * that they use the default INTA line, if they are interrupt
629 * driven at all).
630 */
631 static const char pirq_tab[][5] = {
632 #ifdef CONFIG_ALPHA_P2K
633 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
634 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
635 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
636 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
637 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
638 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
639 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
640 #else
641 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
642 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
643 { 2, 2, -1, -1, -1}, /* idsel 8 (Noname hack: slot closest to ISA) */
644 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
645 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
646 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
647 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
648 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
649 #endif
650 };
651 /*
652 * route_tab selects irq routing in PCI/ISA bridge so that:
653 * PIRQ0 -> irq 15
654 * PIRQ1 -> irq 9
655 * PIRQ2 -> irq 10
656 * PIRQ3 -> irq 11
657 *
658 * This probably ought to be configurable via MILO. For
659 * example, sound boards seem to like using IRQ 9.
660 */
661 const unsigned int route_tab = 0x0b0a090f;
662 unsigned int level_bits;
663 unsigned char pin;
664 int pirq;
665
666 pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
667
668 /*
669 * Go through all devices, fixing up irqs as we see fit:
670 */
671 level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
672 for (dev = pci_devices; dev; dev = dev->next) {
673 dev->irq = 0;
674 if (dev->bus->number != 0) {
675 printk("bios32.sio_fixup: don't know how to fixup devices on bus %d\n",
676 dev->bus->number);
677 continue;
678 }
679 if (PCI_SLOT(dev->devfn) < 6 ||
680 PCI_SLOT(dev->devfn) >= 6 + sizeof(pirq_tab)/sizeof(pirq_tab[0]))
681 {
682 printk("bios32.sio_fixup: "
683 "weird, found device %04x:%04x in non-existent slot %d!!\n",
684 dev->vendor, dev->device, PCI_SLOT(dev->devfn));
685 continue;
686 }
687 pcibios_read_config_byte(dev->bus->number, dev->devfn,
688 PCI_INTERRUPT_PIN, &pin);
689 pirq = pirq_tab[PCI_SLOT(dev->devfn) - 6][pin];
690 if (pirq < 0) {
691 continue;
692 }
693
694 /*
695 * if its a VGA, enable its BIOS ROM at C0000
696 */
697 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
698 pcibios_write_config_dword(dev->bus->number, dev->devfn,
699 PCI_ROM_ADDRESS,
700 0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
701 }
702 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
703 continue; /* for now, displays get no IRQ */
704 }
705 dev->irq = (route_tab >> (8 * pirq)) & 0xff;
706
707 /* must set the PCI IRQs to level triggered */
708 level_bits |= (1 << dev->irq);
709
710 #if PCI_MODIFY
711 /* tell the device: */
712 pcibios_write_config_byte(dev->bus->number, dev->devfn,
713 PCI_INTERRUPT_LINE, dev->irq);
714 #endif
715 }
716 /*
717 * Now, make all PCI interrupts level sensitive. Notice:
718 * these registers must be accessed byte-wise. outw() doesn't
719 * work.
720 */
721 outb((level_bits >> 0) & 0xff, 0x4d0);
722 outb((level_bits >> 8) & 0xff, 0x4d1);
723 enable_ide(0x26e);
724 }
725
726
727 #ifdef CONFIG_TGA_CONSOLE
728 extern void tga_console_init(void);
729 #endif /* CONFIG_TGA_CONSOLE */
730
731 unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
/* */
732 {
733 #if PCI_MODIFY
734 /*
735 * Scan the tree, allocating PCI memory and I/O space.
736 */
737 layout_bus(&pci_root);
738 #endif
739
740 /*
741 * Now is the time to do all those dirty little deeds...
742 */
743 #if defined(CONFIG_ALPHA_NONAME) || defined(CONFIG_ALPHA_AVANTI) || defined(CONFIG_ALPHA_P2K)
744 sio_fixup();
745 #elif defined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB164)
746 cabriolet_fixup();
747 #elif defined(CONFIG_ALPHA_EB66P)
748 eb66p_fixup();
749 #elif defined(CONFIG_ALPHA_EB66)
750 eb66_and_eb64p_fixup();
751 #elif defined(CONFIG_ALPHA_EB64P)
752 eb66_and_eb64p_fixup();
753 #else
754 # error You must tell me what kind of platform you want.
755 #endif
756
757 #ifdef CONFIG_TGA_CONSOLE
758 tga_console_init();
759 #endif /* CONFIG_TGA_CONSOLE */
760
761 return mem_start;
762 }
763
764
765 const char *pcibios_strerror (int error)
/* ![[last]](../icons/n_last.png)
*/
766 {
767 static char buf[80];
768
769 switch (error) {
770 case PCIBIOS_SUCCESSFUL:
771 return "SUCCESSFUL";
772
773 case PCIBIOS_FUNC_NOT_SUPPORTED:
774 return "FUNC_NOT_SUPPORTED";
775
776 case PCIBIOS_BAD_VENDOR_ID:
777 return "SUCCESSFUL";
778
779 case PCIBIOS_DEVICE_NOT_FOUND:
780 return "DEVICE_NOT_FOUND";
781
782 case PCIBIOS_BAD_REGISTER_NUMBER:
783 return "BAD_REGISTER_NUMBER";
784
785 default:
786 sprintf (buf, "UNKNOWN RETURN 0x%x", error);
787 return buf;
788 }
789 }
790
791 #endif /* CONFIG_PCI */
![[bottom]](../icons/n_bottom.png){kind=icon}
*/