root/include/asm-mips/mipsregs.h

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INCLUDED FROM


   1 /*
   2  * include/asm-mips/mipsregs.h
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1994, 1995 by Ralf Baechle
   9  */
  10 
  11 #ifndef __ASM_MIPS_MIPSREGS_H
  12 #define __ASM_MIPS_MIPSREGS_H
  13 
  14 /*
  15  * The following macros are especially useful for __asm__
  16  * inline assembler.
  17  */
  18 
  19 #ifndef __STR
  20 #define __STR(x) #x
  21 #endif
  22 #ifndef STR
  23 #define STR(x) __STR(x)
  24 #endif
  25 
  26 /*
  27  * On the R2000/3000 load instructions are not interlocked -
  28  * we therefore sometimes need to fill load delay slots with a nop
  29  * which would be useless for ISA >= 2.
  30  */
  31 #if !defined (__R4000__)
  32 #define FILL_LDS nop
  33 #else
  34 #define FILL_LDS
  35 #endif
  36 
  37 /*
  38  * Coprocessor 0 register names
  39  */
  40 #define CP0_INDEX $0
  41 #define CP0_RANDOM $1
  42 #define CP0_ENTRYLO0 $2
  43 #define CP0_ENTRYLO1 $3
  44 #define CP0_CONTEXT $4
  45 #define CP0_PAGEMASK $5
  46 #define CP0_WIRED $6
  47 #define CP0_BADVADDR $8
  48 #define CP0_COUNT $9
  49 #define CP0_ENTRYHI $10
  50 #define CP0_COMPARE $11
  51 #define CP0_STATUS $12
  52 #define CP0_CAUSE $13
  53 #define CP0_EPC $14
  54 #define CP0_PRID $15
  55 #define CP0_CONFIG $16
  56 #define CP0_LLADDR $17
  57 #define CP0_WATCHLO $18
  58 #define CP0_WATCHHI $19
  59 #define CP0_XCONTEXT $20
  60 #define CP0_FRAMEMASK $21
  61 #define CP0_DIAGNOSTIC $22
  62 #define CP0_PERFORMANCE $25
  63 #define CP0_ECC $26
  64 #define CP0_CACHEERR $27
  65 #define CP0_TAGLO $28
  66 #define CP0_TAGHI $29
  67 #define CP0_ERROREPC $30
  68 
  69 /*
  70  * Coprocessor 1 (FPU) register names
  71  */
  72 #define CP1_REVISION   $0
  73 #define CP1_STATUS     $31
  74 
  75 /*
  76  * Values for PageMask register
  77  */
  78 #define PM_4K   0x00000000
  79 #define PM_16K  0x00006000
  80 #define PM_64K  0x0001e000
  81 #define PM_256K 0x0007e000
  82 #define PM_1M   0x001fe000
  83 #define PM_4M   0x007fe000
  84 #define PM_16M  0x01ffe000
  85 
  86 /*
  87  * Values used for computation of new tlb entries
  88  */
  89 #define PL_4K   12
  90 #define PL_16K  14
  91 #define PL_64K  16
  92 #define PL_256K 18
  93 #define PL_1M   20
  94 #define PL_4M   22
  95 #define PL_16M  24
  96 
  97 /*
  98  * Macros to access the system control coprocessor
  99  */
 100 #define read_32bit_cp0_register(source)                         \
 101 ({ int __res;                                                   \
 102         __asm__ __volatile__(                                   \
 103         "mfc0\t%0,"STR(source)                                  \
 104         : "=r" (__res));                                        \
 105         __res;})
 106 
 107 #define read_64bit_cp0_register(source)                         \
 108 ({ int __res;                                                   \
 109         __asm__ __volatile__(                                   \
 110         ".set\tmips3\n\t"                                       \
 111         "dmfc0\t%0,"STR(source)"\n\t"                           \
 112         ".set\tmips0"                                           \
 113         : "=r" (__res));                                        \
 114         __res;})
 115 
 116 #define write_32bit_cp0_register(register,value)                \
 117         __asm__ __volatile__(                                   \
 118         "mtc0\t%0,"STR(register)                                \
 119         : : "r" (value));
 120 
 121 #define write_64bit_cp0_register(register,value)                \
 122         __asm__ __volatile__(                                   \
 123         ".set\tmips3\n\t"                                       \
 124         "dmtc0\t%0,"STR(register)"\n\t"                         \
 125         ".set\tmips0"                                           \
 126         : : "r" (value))
 127 /*
 128  * R4x00 interrupt enable / cause bits
 129  */
 130 #define IE_SW0          (1<< 8)
 131 #define IE_SW1          (1<< 9)
 132 #define IE_IRQ0         (1<<10)
 133 #define IE_IRQ1         (1<<11)
 134 #define IE_IRQ2         (1<<12)
 135 #define IE_IRQ3         (1<<13)
 136 #define IE_IRQ4         (1<<14)
 137 #define IE_IRQ5         (1<<15)
 138 
 139 /*
 140  * R4x00 interrupt cause bits
 141  */
 142 #define C_SW0           (1<< 8)
 143 #define C_SW1           (1<< 9)
 144 #define C_IRQ0          (1<<10)
 145 #define C_IRQ1          (1<<11)
 146 #define C_IRQ2          (1<<12)
 147 #define C_IRQ3          (1<<13)
 148 #define C_IRQ4          (1<<14)
 149 #define C_IRQ5          (1<<15)
 150 
 151 #ifndef __LANGUAGE_ASSEMBLY__
 152 /*
 153  * Manipulate the status register.
 154  * Mostly used to access the interrupt bits.
 155  */
 156 #define BUILD_SET_CP0(name,register)                            \
 157 extern __inline__ unsigned int                                  \
 158 set_cp0_##name(unsigned int change, unsigned int new)           \
 159 {                                                               \
 160         unsigned int res;                                       \
 161                                                                 \
 162         res = read_32bit_cp0_register(register);                \
 163         res &= ~change;                                         \
 164         res |= (new & change);                                  \
 165         if(change)                                              \
 166                 write_32bit_cp0_register(register, res);        \
 167                                                                 \
 168         return res;                                             \
 169 }
 170 
 171 BUILD_SET_CP0(status,CP0_STATUS)
 172 BUILD_SET_CP0(cause,CP0_CAUSE)
 173 
 174 #endif /* defined (__LANGUAGE_ASSEMBLY__) */
 175 
 176 /*
 177  * Inline code for use of the ll and sc instructions
 178  *
 179  * FIXME: This instruction is only available on MIPS ISA >=3.
 180  * Since these operations are only being used for atomic operations
 181  * the easiest workaround for the R[23]00 is to disable interrupts.
 182  */
 183 #define load_linked(addr)                                       \
 184 ({                                                              \
 185         unsigned int __res;                                     \
 186                                                                 \
 187         __asm__ __volatile__(                                   \
 188         "ll\t%0,(%1)"                                           \
 189         : "=r" (__res)                                          \
 190         : "r" ((unsigned int) (addr)));                         \
 191                                                                 \
 192         __res;                                                  \
 193 })
 194 
 195 #define store_conditional(addr,value)                           \
 196 ({                                                              \
 197         int     __res;                                          \
 198                                                                 \
 199         __asm__ __volatile__(                                   \
 200         "sc\t%0,(%2)"                                           \
 201         : "=r" (__res)                                          \
 202         : "0" (value), "r" (addr));                             \
 203                                                                 \
 204         __res;                                                  \
 205 })
 206 
 207 /*
 208  * Bitfields in the cp0 status register
 209  *
 210  * Refer to the MIPS R4xx0 manuals, chapter 5 for explanation.
 211  * FIXME: This doesn't cover all R4xx0 processors.
 212  */
 213 #define ST0_IE                  (1   <<  0)
 214 #define ST0_EXL                 (1   <<  1)
 215 #define ST0_ERL                 (1   <<  2)
 216 #define ST0_KSU                 (3   <<  3)
 217 #  define KSU_USER              (2  <<   3)
 218 #  define KSU_SUPERVISOR        (1  <<   3)
 219 #  define KSU_KERNEL            (0  <<   3)
 220 #define ST0_UX                  (1   <<  5)
 221 #define ST0_SX                  (1   <<  6)
 222 #define ST0_KX                  (1   <<  7)
 223 #define ST0_IM                  (255 <<  8)
 224 #define ST0_DE                  (1   << 16)
 225 #define ST0_CE                  (1   << 17)
 226 #define ST0_CH                  (1   << 18)
 227 #define ST0_SR                  (1   << 20)
 228 #define ST0_BEV                 (1   << 22)
 229 #define ST0_RE                  (1   << 25)
 230 #define ST0_FR                  (1   << 26)
 231 #define ST0_CU                  (15  << 28)
 232 #define ST0_CU0                 (1   << 28)
 233 #define ST0_CU1                 (1   << 29)
 234 #define ST0_CU2                 (1   << 30)
 235 #define ST0_CU3                 (1   << 31)
 236 #define ST0_XX                  (1   << 31)     /* R8000/R10000 naming */
 237 
 238 /*
 239  * Bitfields and bit numbers in the coprocessor 0 cause register.
 240  *
 241  * Refer to to your MIPS R4xx0 manual, chapter 5 for explanation.
 242  */
 243 #define  CAUSEB_EXCCODE         2
 244 #define  CAUSEF_EXCCODE         (31  <<  2)
 245 #define  CAUSEB_IP              8
 246 #define  CAUSEF_IP              (255 <<  8)
 247 #define  CAUSEB_IP0             8
 248 #define  CAUSEF_IP0             (1   <<  8)
 249 #define  CAUSEB_IP1             9
 250 #define  CAUSEF_IP1             (1   <<  9)
 251 #define  CAUSEB_IP2             10
 252 #define  CAUSEF_IP2             (1   << 10)
 253 #define  CAUSEB_IP3             11
 254 #define  CAUSEF_IP3             (1   << 11)
 255 #define  CAUSEB_IP4             12
 256 #define  CAUSEF_IP4             (1   << 12)
 257 #define  CAUSEB_IP5             13
 258 #define  CAUSEF_IP5             (1   << 13)
 259 #define  CAUSEB_IP6             14
 260 #define  CAUSEF_IP6             (1   << 14)
 261 #define  CAUSEB_IP7             15
 262 #define  CAUSEF_IP7             (1   << 15)
 263 #define  CAUSEB_CE              28
 264 #define  CAUSEF_CE              (3   << 28)
 265 #define  CAUSEB_BD              31
 266 #define  CAUSEF_BD              (1   << 31)
 267 
 268 #endif /* __ASM_MIPS_MIPSREGS_H */

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