root/include/linux/scc.h

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   1 /* $Id: scc.h,v 1.15 1995/11/16 20:19:26 jreuter Exp jreuter $ */
   2 
   3 #ifndef _SCC_H
   4 #define _SCC_H
   5 
   6 /* selection of hardware types */
   7 
   8 #define PA0HZP          0x00    /* hardware type for PA0HZP SCC card and compatible */
   9 #define EAGLE           0x01    /* hardware type for EAGLE card */
  10 #define PC100           0x02    /* hardware type for PC100 card */
  11 #define PRIMUS          0x04    /* hardware type for PRIMUS-PC (DG9BL) card */
  12 #define DRSI            0x08    /* hardware type for DRSI PC*Packet card */
  13 #define BAYCOM          0x10    /* hardware type for BayCom (U)SCC */
  14 
  15 /* Paranoia check... */
  16 
  17 #define SCC_PARANOIA_CHECK      /* tell the user if something is going wrong */
  18 
  19 /* ioctl() commands */
  20 
  21 #define TIOCSCCCFG      0x2200          /* set hardware parameters */
  22 #define TIOCSCCINI      0x2201          /* init driver */
  23 #define TIOCCHANINI     0x2202          /* init channel */
  24 
  25 #define TIOCCHANMEM     0x2210          /* adjust buffer pools */
  26 
  27 #define TIOCGKISS       0x2282          /* get kiss parameter */
  28 #define TIOCSKISS       0x2283          /* set kiss parameter */
  29 
  30 #define TIOCSCCSTAT     0x2284          /* get scc status */
  31 
  32 
  33 /* magic number */
  34 
  35 #define SCC_MAGIC       0x8530          /* ;-) */
  36 
  37 /* KISS protocol flags */
  38 #define FEND    192
  39 #define FESC    219
  40 #define TFEND   220
  41 #define TFESC   221
  42 
  43 /* KISS state machine */
  44 
  45 #define KISS_IDLE       0
  46 #define KISS_DATA       1
  47 #define KISS_ESCAPE     2
  48 #define KISS_RXFRAME    3
  49 
  50 /* Device parameter control (from WAMPES) */
  51 
  52 #define PARAM_TXDELAY   1
  53 #define PARAM_PERSIST   2
  54 #define PARAM_SLOTTIME  3
  55 #define PARAM_TXTAIL    4
  56 #define PARAM_FULLDUP   5
  57 #define PARAM_SOFTDCD   6       /* was: PARAM_HW */
  58 #define PARAM_MUTE      7       /* ??? */
  59 #define PARAM_DTR       8
  60 #define PARAM_RTS       9
  61 #define PARAM_SPEED     10
  62 #define PARAM_ENDDELAY  11      /* ??? */
  63 #define PARAM_GROUP     12
  64 #define PARAM_IDLE      13
  65 #define PARAM_MIN       14
  66 #define PARAM_MAXKEY    15
  67 #define PARAM_WAIT      16
  68 #define PARAM_MAXDEFER  17
  69 #define PARAM_TX        18
  70 #define PARAM_SLIP      19
  71 #define PARAM_RETURN    255     /* reset kiss mode */
  72 
  73 #define TIMER_OFF       65535U  /* to switch off timers */
  74 #define NO_SUCH_PARAM   65534U  /* param not implemented */
  75 
  76 /* channel grouping */
  77 
  78 #define RXGROUP         0x100   /* if set, only tx when all channels clear */
  79 #define TXGROUP         0x200   /* if set, don't transmit simultaneously */
  80 
  81 /* Tx/Rx clock sources */
  82 
  83 #define CLK_DPLL        0       /* normal halfduplex operation */
  84 #define CLK_EXTERNAL    1       /* external clocking (G3RUH/DF9IC modems) */
  85 #define CLK_DIVIDER     2       /* Rx = DPLL, Tx = divider (fullduplex with */
  86                                 /* modems without clock regeneration */
  87 
  88 /* Tx state */
  89 
  90 #define TXS_IDLE        0       /* Transmitter off, no data pending */
  91 #define TXS_BUSY        1       /* waiting for permission to send / tailtime */
  92 #define TXS_ACTIVE      2       /* Transmitter on, sending data */
  93 #define TXS_NEWFRAME    3       /* reset CRC and send (next) frame */
  94 
  95 #define TX_ON           1       /* command for scc_key_trx() */
  96 #define TX_OFF          0       /* dto */
  97 
  98 /* Buffer management */
  99 
 100 #define BT_RECEIVE  1           /* buffer allocated by receive */
 101 #define BT_TRANSMIT 2           /* buffer allocated by transmit */
 102 
 103 #define NULLBUF  (struct mbuf *)0
 104 #define NULLBUFP (struct mbuf **)0
 105 
 106 
 107 typedef unsigned short io_port; /* type definition for an 'io port address' */
 108 typedef unsigned short ioaddr;  /* old def */
 109 
 110 #ifdef SCC_DELAY
 111 #define Inb(port)       inb_p(port)
 112 #define Outb(port, val) outb_p(val, port)
 113 #else
 114 #define Inb(port)       inb(port)
 115 #define Outb(port, val) outb(val, port)
 116 #endif
 117 
 118 /* some nasty macros (esp. Expired) */
 119 
 120 #define TIMER_STOPPED 65535U
 121 #define Running(k) (scc->k != TIMER_STOPPED)
 122 #define Expired(k) (scc->k != TIMER_STOPPED) && (!(scc->k) || (--(scc->k) == 0))
 123 #define Stop_Timer(k) scc->k = TIMER_STOPPED
 124 
 125 
 126 /* Basic message buffer structure */
 127 
 128 struct mbuf {
 129         struct mbuf *next;      /* Link to next buffer */
 130         struct mbuf *prev;      /* Link to previous buffer */
 131         
 132         int cnt;                /* Number of bytes stored in buffer */
 133         unsigned char *rw_ptr;  /* read-write pointer */
 134         unsigned char data[0];  /* anchor for allocated buffer */
 135 };
 136         
 137 /* SCC channel control structure for KISS */
 138 
 139 struct scc_kiss {
 140         unsigned char txdelay;          /* Transmit Delay 10 ms/cnt */
 141         unsigned char persist;          /* Persistence (0-255) as a % */
 142         unsigned char slottime;         /* Delay to wait on persistence hit */
 143         unsigned char tailtime;         /* Delay after XMTR OFF */
 144         unsigned char fulldup;          /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */
 145         unsigned char waittime;         /* Waittime before any transmit attempt */
 146         unsigned int  maxkeyup;         /* Maximum time to transmit (seconds) */
 147         unsigned char mintime;          /* Minimal offtime after MAXKEYUP timeout */
 148         unsigned int  idletime;         /* Maximum idle time in ALWAYS KEYED mode (seconds) */
 149         unsigned int  maxdefer;         /* Timer for CSMA channel busy limit */
 150         unsigned char tx_inhibit;       /* Transmit is not allowed when set */  
 151         unsigned char group;            /* group ID for AX.25 TX interlocking */
 152         unsigned char not_slip;         /* set to zero: use SLIP instead of KISS */
 153         unsigned char softdcd;          /* use DPLL instead of DCD pin for carrier detect */
 154 };
 155 
 156 
 157 /* SCC statistical information */
 158 
 159 struct scc_stat {
 160         long rxints;            /* Receiver interrupts */
 161         long txints;            /* Transmitter interrupts */
 162         long exints;            /* External/status interrupts */
 163         long spints;            /* Special receiver interrupts */
 164 
 165         long txframes;          /* Packets sent */
 166         long rxframes;          /* Number of Frames Actually Received */
 167         long rxerrs;            /* CRC Errors */
 168         long txerrs;            /* KISS errors */
 169         
 170         unsigned int nospace;   /* "Out of buffers" */
 171         unsigned int rx_over;   /* Receiver Overruns */
 172         unsigned int tx_under;  /* Transmitter Underruns */
 173 
 174         unsigned int tx_state;  /* Transmitter state */
 175         
 176         char tx_kiss_state;     /* state of the kiss interpreter */
 177         char rx_kiss_state;     /* state of the kiss encoder */
 178         
 179         int tx_queued;          /* tx frames enqueued */
 180         int rx_queued;          /* rx frames enqueued */
 181         
 182         unsigned int rxbuffers; /* allocated rx_buffers */
 183         unsigned int txbuffers; /* allocated tx_buffers */
 184         unsigned int bufsize;   /* used buffersize */
 185 };
 186 
 187 
 188 struct scc_modem {
 189         long speed;             /* Line speed, bps */
 190         char clocksrc;          /* 0 = DPLL, 1 = external, 2 = divider */
 191         char nrz;               /* NRZ instead of NRZI */       
 192 };
 193 
 194 struct ioctl_command {
 195         int      command;       /* one of the KISS-Commands defined above */
 196         unsigned param;         /* KISS-Param */
 197 };
 198 
 199 /* currently unused */
 200 
 201 struct scc_hw_config {
 202         io_port data_a;         /* data port channel A */
 203         io_port ctrl_a;         /* control port channel A */
 204         io_port data_b;         /* data port channel B */
 205         io_port ctrl_b;         /* control port channel B */
 206         io_port vector_latch;   /* INTACK-Latch (#) */
 207         io_port special;        /* special function port */
 208 
 209         int     irq;            /* irq */
 210         long    clock;          /* clock */
 211         char    option;         /* command for function port */
 212         
 213         char brand;             /* hardware type */
 214         char escc;              /* use ext. features of a 8580/85180/85280 */
 215 };
 216 
 217 struct scc_mem_config {
 218         unsigned int rxbuffers;
 219         unsigned int txbuffers;
 220         unsigned int bufsize;
 221 };
 222 
 223 /* (#) only one INTACK latch allowed. */
 224         
 225 
 226 /* SCC channel structure */
 227 
 228 struct scc_channel {
 229         int magic;              /* magic word */
 230         
 231         int init;               /* channel exists? */
 232         struct tty_struct *tty; /* link to tty control structure */
 233         char tty_opened;        /* No. of open() calls... */
 234         char throttled;         /* driver is throttled  */
 235                 
 236         char brand;             /* manufacturer of the board */
 237         long clock;             /* used clock */
 238         
 239         io_port ctrl;           /* I/O address of CONTROL register */
 240         io_port data;           /* I/O address of DATA register */
 241         io_port special;        /* I/O address of special function port */
 242         
 243         char option;
 244         char enhanced;          /* Enhanced SCC support */
 245 
 246         unsigned char wreg[16]; /* Copy of last written value in WRx */
 247         unsigned char status;   /* Copy of R0 at last external interrupt */
 248 
 249         struct scc_kiss kiss;   /* control structure for KISS params */
 250         struct scc_stat stat;   /* statistical information */
 251         struct scc_modem modem; /* modem information */
 252         
 253         struct mbuf *rx_buffer_pool; /* free buffers for rx/tx frames are */
 254         struct mbuf *tx_buffer_pool; /* linked in these ring chains */
 255         
 256         struct mbuf *rx_queue;  /* chain of received frames */
 257         struct mbuf *tx_queue;  /* chain of frames due to transmit */
 258         struct mbuf *rx_bp;     /* pointer to frame currently received */
 259         struct mbuf *tx_bp;     /* pointer to frame currently transmitted */
 260         
 261         struct mbuf *kiss_decode_bp; /* frame we are receiving from tty */
 262         struct mbuf *kiss_encode_bp; /* frame we are sending to tty */
 263         
 264         /* Timer */
 265         
 266         struct timer_list tx_t; /* tx timer for this channel */
 267         struct timer_list rx_t; /* rx timer */
 268 
 269         /* rx timer counters */
 270         
 271         unsigned int t_dwait;   /* wait time (DWAIT) */
 272         unsigned int t_slot;    /* channel sample frequency */
 273         unsigned int t_txdel;   /* TX delay */
 274         unsigned int t_tail;    /* tail time */
 275         unsigned int t_maxk;    /* max. key up */
 276         unsigned int t_min;     /* minimal key up */
 277         unsigned int t_idle;    /* */
 278         unsigned int t_mbusy;   /* time until defer if channel busy */          
 279 };
 280 
 281 
 282 /* 8530 Serial Communications Controller Register definitions */
 283 #define FLAG    0x7e
 284 
 285 /* Write Register 0 */
 286 #define R0      0               /* Register selects */
 287 #define R1      1
 288 #define R2      2
 289 #define R3      3
 290 #define R4      4
 291 #define R5      5
 292 #define R6      6
 293 #define R7      7
 294 #define R8      8
 295 #define R9      9
 296 #define R10     10
 297 #define R11     11
 298 #define R12     12
 299 #define R13     13
 300 #define R14     14
 301 #define R15     15
 302 
 303 #define NULLCODE        0       /* Null Code */
 304 #define POINT_HIGH      0x8     /* Select upper half of registers */
 305 #define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
 306 #define SEND_ABORT      0x18    /* HDLC Abort */
 307 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
 308 #define RES_Tx_P        0x28    /* Reset TxINT Pending */
 309 #define ERR_RES         0x30    /* Error Reset */
 310 #define RES_H_IUS       0x38    /* Reset highest IUS */
 311 
 312 #define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
 313 #define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
 314 #define RES_EOM_L       0xC0    /* Reset EOM latch */
 315 
 316 /* Write Register 1 */
 317 
 318 #define EXT_INT_ENAB    0x1     /* Ext Int Enable */
 319 #define TxINT_ENAB      0x2     /* Tx Int Enable */
 320 #define PAR_SPEC        0x4     /* Parity is special condition */
 321 
 322 #define RxINT_DISAB     0       /* Rx Int Disable */
 323 #define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
 324 #define INT_ALL_Rx      0x10    /* Int on all Rx Characters or error */
 325 #define INT_ERR_Rx      0x18    /* Int on error only */
 326 
 327 #define WT_RDY_RT       0x20    /* Wait/Ready on R/T */
 328 #define WT_FN_RDYFN     0x40    /* Wait/FN/Ready FN */
 329 #define WT_RDY_ENAB     0x80    /* Wait/Ready Enable */
 330 
 331 /* Write Register 2 (Interrupt Vector) */
 332 
 333 /* Write Register 3 */
 334 
 335 #define RxENABLE        0x1     /* Rx Enable */
 336 #define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
 337 #define ADD_SM          0x4     /* Address Search Mode (SDLC) */
 338 #define RxCRC_ENAB      0x8     /* Rx CRC Enable */
 339 #define ENT_HM          0x10    /* Enter Hunt Mode */
 340 #define AUTO_ENAB       0x20    /* Auto Enables */
 341 #define Rx5             0x0     /* Rx 5 Bits/Character */
 342 #define Rx7             0x40    /* Rx 7 Bits/Character */
 343 #define Rx6             0x80    /* Rx 6 Bits/Character */
 344 #define Rx8             0xc0    /* Rx 8 Bits/Character */
 345 
 346 /* Write Register 4 */
 347 
 348 #define PAR_ENA         0x1     /* Parity Enable */
 349 #define PAR_EVEN        0x2     /* Parity Even/Odd* */
 350 
 351 #define SYNC_ENAB       0       /* Sync Modes Enable */
 352 #define SB1             0x4     /* 1 stop bit/char */
 353 #define SB15            0x8     /* 1.5 stop bits/char */
 354 #define SB2             0xc     /* 2 stop bits/char */
 355 
 356 #define MONSYNC         0       /* 8 Bit Sync character */
 357 #define BISYNC          0x10    /* 16 bit sync character */
 358 #define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
 359 #define EXTSYNC         0x30    /* External Sync Mode */
 360 
 361 #define X1CLK           0x0     /* x1 clock mode */
 362 #define X16CLK          0x40    /* x16 clock mode */
 363 #define X32CLK          0x80    /* x32 clock mode */
 364 #define X64CLK          0xC0    /* x64 clock mode */
 365 
 366 /* Write Register 5 */
 367 
 368 #define TxCRC_ENAB      0x1     /* Tx CRC Enable */
 369 #define RTS             0x2     /* RTS */
 370 #define SDLC_CRC        0x4     /* SDLC/CRC-16 */
 371 #define TxENAB          0x8     /* Tx Enable */
 372 #define SND_BRK         0x10    /* Send Break */
 373 #define Tx5             0x0     /* Tx 5 bits (or less)/character */
 374 #define Tx7             0x20    /* Tx 7 bits/character */
 375 #define Tx6             0x40    /* Tx 6 bits/character */
 376 #define Tx8             0x60    /* Tx 8 bits/character */
 377 #define DTR             0x80    /* DTR */
 378 
 379 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
 380 
 381 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
 382 
 383 /* Write Register 8 (transmit buffer) */
 384 
 385 /* Write Register 9 (Master interrupt control) */
 386 #define VIS     1       /* Vector Includes Status */
 387 #define NV      2       /* No Vector */
 388 #define DLC     4       /* Disable Lower Chain */
 389 #define MIE     8       /* Master Interrupt Enable */
 390 #define STATHI  0x10    /* Status high */
 391 #define NORESET 0       /* No reset on write to R9 */
 392 #define CHRB    0x40    /* Reset channel B */
 393 #define CHRA    0x80    /* Reset channel A */
 394 #define FHWRES  0xc0    /* Force hardware reset */
 395 
 396 /* Write Register 10 (misc control bits) */
 397 #define BIT6    1       /* 6 bit/8bit sync */
 398 #define LOOPMODE 2      /* SDLC Loop mode */
 399 #define ABUNDER 4       /* Abort/flag on SDLC xmit underrun */
 400 #define MARKIDLE 8      /* Mark/flag on idle */
 401 #define GAOP    0x10    /* Go active on poll */
 402 #define NRZ     0       /* NRZ mode */
 403 #define NRZI    0x20    /* NRZI mode */
 404 #define FM1     0x40    /* FM1 (transition = 1) */
 405 #define FM0     0x60    /* FM0 (transition = 0) */
 406 #define CRCPS   0x80    /* CRC Preset I/O */
 407 
 408 /* Write Register 11 (Clock Mode control) */
 409 #define TRxCXT  0       /* TRxC = Xtal output */
 410 #define TRxCTC  1       /* TRxC = Transmit clock */
 411 #define TRxCBR  2       /* TRxC = BR Generator Output */
 412 #define TRxCDP  3       /* TRxC = DPLL output */
 413 #define TRxCOI  4       /* TRxC O/I */
 414 #define TCRTxCP 0       /* Transmit clock = RTxC pin */
 415 #define TCTRxCP 8       /* Transmit clock = TRxC pin */
 416 #define TCBR    0x10    /* Transmit clock = BR Generator output */
 417 #define TCDPLL  0x18    /* Transmit clock = DPLL output */
 418 #define RCRTxCP 0       /* Receive clock = RTxC pin */
 419 #define RCTRxCP 0x20    /* Receive clock = TRxC pin */
 420 #define RCBR    0x40    /* Receive clock = BR Generator output */
 421 #define RCDPLL  0x60    /* Receive clock = DPLL output */
 422 #define RTxCX   0x80    /* RTxC Xtal/No Xtal */
 423 
 424 /* Write Register 12 (lower byte of baud rate generator time constant) */
 425 
 426 /* Write Register 13 (upper byte of baud rate generator time constant) */
 427 
 428 /* Write Register 14 (Misc control bits) */
 429 #define BRENABL 1       /* Baud rate generator enable */
 430 #define BRSRC   2       /* Baud rate generator source */
 431 #define DTRREQ  4       /* DTR/Request function */
 432 #define AUTOECHO 8      /* Auto Echo */
 433 #define LOOPBAK 0x10    /* Local loopback */
 434 #define SEARCH  0x20    /* Enter search mode */
 435 #define RMC     0x40    /* Reset missing clock */
 436 #define DISDPLL 0x60    /* Disable DPLL */
 437 #define SSBR    0x80    /* Set DPLL source = BR generator */
 438 #define SSRTxC  0xa0    /* Set DPLL source = RTxC */
 439 #define SFMM    0xc0    /* Set FM mode */
 440 #define SNRZI   0xe0    /* Set NRZI mode */
 441 
 442 /* Write Register 15 (external/status interrupt control) */
 443 #define ZCIE    2       /* Zero count IE */
 444 #define DCDIE   8       /* DCD IE */
 445 #define SYNCIE  0x10    /* Sync/hunt IE */
 446 #define CTSIE   0x20    /* CTS IE */
 447 #define TxUIE   0x40    /* Tx Underrun/EOM IE */
 448 #define BRKIE   0x80    /* Break/Abort IE */
 449 
 450 
 451 /* Read Register 0 */
 452 #define Rx_CH_AV        0x1     /* Rx Character Available */
 453 #define ZCOUNT          0x2     /* Zero count */
 454 #define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
 455 #define DCD             0x8     /* DCD */
 456 #define SYNC_HUNT       0x10    /* Sync/hunt */
 457 #define CTS             0x20    /* CTS */
 458 #define TxEOM           0x40    /* Tx underrun */
 459 #define BRK_ABRT        0x80    /* Break/Abort */
 460 
 461 /* Read Register 1 */
 462 #define ALL_SNT         0x1     /* All sent */
 463 /* Residue Data for 8 Rx bits/char programmed */
 464 #define RES3            0x8     /* 0/3 */
 465 #define RES4            0x4     /* 0/4 */
 466 #define RES5            0xc     /* 0/5 */
 467 #define RES6            0x2     /* 0/6 */
 468 #define RES7            0xa     /* 0/7 */
 469 #define RES8            0x6     /* 0/8 */
 470 #define RES18           0xe     /* 1/8 */
 471 #define RES28           0x0     /* 2/8 */
 472 /* Special Rx Condition Interrupts */
 473 #define PAR_ERR         0x10    /* Parity error */
 474 #define Rx_OVR          0x20    /* Rx Overrun Error */
 475 #define CRC_ERR         0x40    /* CRC/Framing Error */
 476 #define END_FR          0x80    /* End of Frame (SDLC) */
 477 
 478 /* Read Register 2 (channel B only) - Interrupt vector */
 479 
 480 #define VECTOR_MASK     0x06
 481 
 482 #define TXINT   0x00
 483 #define EXINT   0x02
 484 #define RXINT   0x04
 485 #define SPINT   0x06
 486 
 487 
 488 /* Read Register 3 (interrupt pending register) ch a only */
 489 #define CHBEXT  0x1             /* Channel B Ext/Stat IP */
 490 #define CHBTxIP 0x2             /* Channel B Tx IP */
 491 #define CHBRxIP 0x4             /* Channel B Rx IP */
 492 #define CHAEXT  0x8             /* Channel A Ext/Stat IP */
 493 #define CHATxIP 0x10            /* Channel A Tx IP */
 494 #define CHARxIP 0x20            /* Channel A Rx IP */
 495 
 496 /* Read Register 8 (receive data register) */
 497 
 498 /* Read Register 10  (misc status bits) */
 499 #define ONLOOP  2               /* On loop */
 500 #define LOOPSEND 0x10           /* Loop sending */
 501 #define CLK2MIS 0x40            /* Two clocks missing */
 502 #define CLK1MIS 0x80            /* One clock missing */
 503 
 504 /* Read Register 12 (lower byte of baud rate generator constant) */
 505 
 506 /* Read Register 13 (upper byte of baud rate generator constant) */
 507 
 508 /* Read Register 15 (value of WR 15) */
 509 
 510 
 511 /* 8536 register definitions */
 512 
 513 #define CIO_MICR        0x00    /* Master interrupt control register */
 514 #define CIO_MCCR        0x01    /* Master configuration control register */
 515 #define CIO_CTMS1       0x1c    /* Counter/timer mode specification #1 */
 516 #define CIO_CTMS2       0x1d    /* Counter/timer mode specification #2 */
 517 #define CIO_CTMS3       0x1e    /* Counter/timer mode specification #3 */
 518 #define CIO_IVR         0x04    /* Interrupt vector register */
 519 
 520 #define CIO_CSR1        0x0a    /* Command and status register CTC #1 */
 521 #define CIO_CSR2        0x0b    /* Command and status register CTC #2 */
 522 #define CIO_CSR3        0x0c    /* Command and status register CTC #3 */
 523 
 524 #define CIO_CT1MSB      0x16    /* CTC #1 Timer constant - MSB */
 525 #define CIO_CT1LSB      0x17    /* CTC #1 Timer constant - LSB */
 526 #define CIO_CT2MSB      0x18    /* CTC #2 Timer constant - MSB */
 527 #define CIO_CT2LSB      0x19    /* CTC #2 Timer constant - LSB */
 528 #define CIO_CT3MSB      0x1a    /* CTC #3 Timer constant - MSB */
 529 #define CIO_CT3LSB      0x1b    /* CTC #3 Timer constant - LSB */
 530 #define CIO_PDCA        0x23    /* Port A data direction control */
 531 #define CIO_PDCB        0x2b    /* Port B data direction control */
 532 
 533 #define CIO_GCB         0x04    /* CTC Gate command bit */
 534 #define CIO_TCB         0x02    /* CTC Trigger command bit */
 535 #define CIO_IE          0xc0    /* CTC Interrupt enable (set) */
 536 #define CIO_CIP         0x20    /* CTC Clear interrupt pending */
 537 #define CIO_IP          0x20    /* CTC Interrupt pending */
 538 
 539 
 540 /* 8580/85180/85280 Enhanced SCC register definitions */
 541 
 542 /* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
 543 #define AUTOTXF 0x01            /* Auto Tx Flag */
 544 #define AUTOEOM 0x02            /* Auto EOM Latch Reset */
 545 #define AUTORTS 0x04            /* Auto RTS */
 546 #define TXDNRZI 0x08            /* TxD Pulled High in SDLC NRZI mode */
 547 #define FASTDTR 0x10            /* Fast DTR/REQ Mode */
 548 #define CRCCBCR 0x20            /* CRC Check Bytes Completely Received */
 549 #define EXTRDEN 0x40            /* Extended Read Enabled */
 550 
 551 /* Write Register 15 (external/status interrupt control) */
 552 #define SHDLCE  1               /* SDLC/HDLC Enhancements Enable */
 553 #define FIFOE   4               /* FIFO Enable */
 554 
 555 /* Read Register 6 (frame status FIFO) */
 556 #define BCLSB   0xff            /* LSB of 14 bits count */
 557 
 558 /* Read Register 7 (frame status FIFO) */
 559 #define BCMSB   0x3f            /* MSB of 14 bits count */
 560 #define FDA     0x40            /* FIFO Data Available Status */
 561 #define FOY     0x80            /* FIFO Overflow Status */
 562 
 563 #endif  /* _SCC_H */
 564 
 565 /* global functions */
 566 
 567 #ifdef PREV_LINUX_1_3_33
 568 extern long scc_init(long kmem_start);
 569 #else
 570 extern int scc_init(void);
 571 #endif

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