root/drivers/net/ibmtr.h

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INCLUDED FROM


   1 /* Definitions for an IBM Token Ring card. */
   2 /* This file is distributed under the GNU GPL   */
   3 
   4 /* ported to the Alpha architecture 02/20/96 (just used the HZ macro) */
   5 
   6 #define TR_RETRY_INTERVAL (5*HZ) /* 500 on PC = 5 s */
   7 #define TR_RESET_INTERVAL (HZ/20) /* 5 on PC = 50 ms */
   8 #define TR_BUSY_INTERVAL (HZ/5) /* 5 on PC = 200 ms */
   9 
  10 #define TR_ISA 1
  11 #define TR_MCA 2
  12 #define TR_ISAPNP 3
  13 #define NOTOK 0
  14 #define TOKDEBUG 1
  15 
  16 #ifndef IBMTR_SHARED_RAM_BASE
  17 #define IBMTR_SHARED_RAM_BASE 0xD0
  18 #define IBMTR_SHARED_RAM_SIZE 0x10
  19 #endif
  20 
  21 #define CHANNEL_ID      0X1F30
  22 #define AIP             0X1F00
  23 #define AIPCHKSUM1      0X1F60
  24 #define AIPCHKSUM2      0X1FF0
  25 #define AIPADAPTYPE     0X1FA0
  26 #define AIPDATARATE     0X1FA2
  27 #define AIPEARLYTOKEN   0X1FA4
  28 #define AIPAVAILSHRAM   0X1FA6
  29 #define AIPSHRAMPAGE    0X1FA8
  30 #define AIP4MBDHB       0X1FAA
  31 #define AIP16MBDHB      0X1FAC
  32 #define AIPFID          0X1FBA
  33 
  34 /* Note, 0xA20 == 0x220 since motherboard decodes 10 bits.  I left everything
  35    the way my documentation had it, ie: 0x0A20.     */
  36 #define ADAPTINTCNTRL   0x02f0  /* Adapter interrupt control */
  37 #define ADAPTRESET      0x1     /* Control Adapter reset (add to base) */
  38 #define ADAPTRESETREL   0x2     /* Release Adapter from reset ( """)  */
  39 #define ADAPTINTREL     0x3     /* Adapter interrupt release */
  40 
  41 #define MMIOStartLocP   0x0a20  /* Primary adapter's starting MMIO area */
  42 #define MMIOStartLocA   0x0a24  /* Alternate adapter's starting MMIO area */
  43 
  44 #define TR_IO_EXTENT    4       /* size of used IO range */
  45 
  46 #define GLOBAL_INT_ENABLE 0x02f0
  47 
  48 /* MMIO bits 0-4 select register */
  49 #define RRR_EVEN        0x00    /* Shared RAM relocation registers - even and odd */
  50 /* Used to set the starting address of shared RAM  */
  51 /* Bits 1 through 7 of this register map to bits 13 through 19 of the shared RAM address.*/
  52 /* ie: 0x02 sets RAM address to ...ato!  issy su wazzoo !! GODZILLA!!! */
  53 #define RRR_ODD         0x01
  54 /* Bits 2 and 3 of this register can be read to determine shared RAM size */
  55 /* 00 for 8k, 01 for 16k, 10 for 32k, 11 for 64k  */
  56 #define WRBR_EVEN       0x02    /* Write region base registers - even and odd */
  57 #define WRBR_ODD        0x03
  58 #define WWOR_EVEN       0x04    /* Write window open registers - even and odd */
  59 #define WWOR_ODD        0x05
  60 #define WWCR_EVEN       0x06    /* Write window close registers - even and odd */
  61 #define WWCR_ODD        0x07
  62 
  63 /* Interrupt status registers - PC system  - even and odd */
  64 #define ISRP_EVEN       0x08
  65 
  66 #define TCR_INT 0x10    /* Bit 4 - Timer interrupt.  The TVR_EVEN timer has
  67                                                                    expired. */
  68 #define ERR_INT 0x08    /* Bit 3 - Error interrupt.  The adapter has had an
  69                                                                    internal error. */
  70 #define ACCESS_INT 0x04    /* Bit 2 - Access interrupt.  You have attempted to
  71                                                            write to an invalid area of shared RAM or an invalid
  72                                                                    register within the MMIO. */
  73 /*      In addition, the following bits within ISRP_EVEN can be turned on or off by you */
  74 /*      to control the interrupt processing:   */
  75 #define INT_IRQ 0x80    /* Bit 7 - If 0 the adapter will issue a CHCK, if 1 and
  76                                                               IRQ.  This should normally be set (by you) to 1.  */
  77 #define INT_ENABLE 0x40 /* Bit 6 - Interrupt enable.  If 0, no interrupts will
  78                                                                    occur.  If 1, interrupts will occur normally.
  79                                                                    Normally set to 1.  */
  80 /* Bit 0 - Primary or alternate adapter.  Set to zero if this adapter is the primary adapter,*/
  81 /*         1 if this adapter is the alternate adapter. */
  82 
  83 
  84 #define ISRP_ODD        0x09
  85 
  86 #define ADAP_CHK_INT 0x40 /* Bit 6 - Adapter check.  the adapter has
  87                              encountered a serious problem and has closed
  88                              itself.  Whoa.  */
  89 #define SRB_RESP_INT 0x20 /* Bit 5 - SRB response.  The adapter has accepted
  90                              an SRB request and set the return code within
  91                              the SRB. */
  92 #define ASB_FREE_INT 0x10 /* Bit 4 - ASB free.  The adapter has read the ASB
  93                                                                           and this area can be safely reused. This interrupt
  94                                                                           is only used if your application has set the ASB
  95                                                                           free request bit in ISRA_ODD or if an error was
  96                                                                 detected in your response. */
  97 #define ARB_CMD_INT  0x08 /* Bit 3 - ARB command.  The adapter has given you a
  98                                                                           command for action.  The command is located in the
  99                                                                           ARB area of shared memory. */
 100 #define SSB_RESP_INT 0x04 /* Bit 2 - SSB response.  The adapter has posted a
 101                                                                           response to your SRB (the response is located in
 102                                                                           the SSB area of shared memory). */
 103 /* Bit 1 - Bridge frame forward complete. */
 104 
 105 
 106 
 107 #define ISRA_EVEN       0x0A    /* Interrupt status registers - adapter  - even and odd */
 108 /* Bit 7 - Internal parity error (on adapter's internal bus) */
 109 /* Bit 6 - Timer interrupt pending */
 110 /* Bit 5 - Access interrupt (attempt by adapter to access illegal address) */
 111 /* Bit 4 - Adapter microcode problem (microcode dead-man timer expired) */
 112 /* Bit 3 - Adapter processor check status */
 113 /* Bit 2 - Reserved */
 114 /* Bit 1 - Adapter hardware interrupt mask (prevents internal interrupts) */
 115 /* Bit 0 - Adapter software interrupt mask (prevents internal software interrupts) */
 116 
 117 #define ISRA_ODD        0x0B
 118 #define CMD_IN_SRB 0x20 /* Bit 5  - Indicates that you have placed a new
 119                            command in the SRB and are ready for the adapter to
 120                            process the command. */
 121 #define RESP_IN_ASB 0x10 /* Bit 4 - Indicates that you have placed a response
 122                                                                     (an ASB) in the shared RAM which is available for
 123                                                                          the adapter's use. */
 124 /* Bit 3 - Indicates that you are ready to put an SRB in the shared RAM, but that a previous */
 125 /*         command is still pending.  The adapter will then interrupt you when the previous */
 126 /*         command is completed */
 127 /* Bit 2 - Indicates that you are ready to put an ASB in the shared RAM, but that a previous */
 128 /*         ASB is still pending.  The adapter will then interrupt you when the previous ASB */
 129 /*         is copied.  */
 130 #define ARB_FREE 0x2
 131 #define SSB_FREE 0x1
 132 
 133 #define TCR_EVEN        0x0C    /* Timer control registers - even and odd */
 134 #define TCR_ODD         0x0D
 135 #define TVR_EVEN        0x0E    /* Timer value registers - even and odd */
 136 #define TVR_ODD         0x0F
 137 #define SRPR_EVEN       0x10    /* Shared RAM paging registers - even and odd */
 138 #define SRPR_ENABLE_PAGING 0xc0
 139 #define SRPR_ODD        0x11 /* Not used. */
 140 #define TOKREAD         0x60
 141 #define TOKOR           0x40
 142 #define TOKAND          0x20
 143 #define TOKWRITE        0x00
 144 
 145 /* MMIO bits 5-6 select operation */
 146 /* 00 is used to write to a register */
 147 /* 01 is used to bitwise AND a byte with a register */
 148 /* 10 is used to bitwise OR a byte with a register  */
 149 /* 11 is used to read from a register */
 150 
 151 /* MMIO bits 7-8 select area of interest.. see below */
 152 /* 00 selects attachment control area. */
 153 /* 01 is reserved. */
 154 /* 10 selects adapter identification area A containing the adapter encoded address. */
 155 /* 11 selects the adapter identification area B containing test patterns. */
 156 
 157 #define PCCHANNELID 5049434F3631313039393020
 158 #define MCCHANNELID 4D4152533633583435313820
 159 
 160 #define ACA_OFFSET 0x1e00
 161 #define ACA_SET 0x40
 162 #define ACA_RESET 0x20
 163 #define ACA_RW 0x00
 164 
 165 #ifdef ENABLE_PAGING
 166 #define SET_PAGE(x) (writeb(((x>>8)&ti.page_mask), \
 167   ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN))
 168 #else
 169 #define SET_PAGE(x)
 170 #endif
 171 
 172 typedef enum { IN_PROGRESS, SUCCESS, FAILURE, CLOSED } open_state;
 173 
 174 /* do_tok_int possible values */
 175 #define FIRST_INT 1
 176 #define NOT_FIRST 2
 177 
 178 struct tok_info {
 179         unsigned char irq;
 180         __u32 mmio;
 181         unsigned char hw_address[32];
 182         unsigned char adapter_type;
 183         unsigned char data_rate;
 184         unsigned char token_release;
 185         unsigned char avail_shared_ram;
 186         unsigned char shared_ram_paging;
 187         unsigned char dhb_size4mb;
 188         unsigned char dhb_size16mb;
 189         /* Additions by David Morris       */
 190         unsigned char do_tok_int;
 191         struct wait_queue *wait_for_tok_int;
 192         struct wait_queue *wait_for_reset;
 193         unsigned char sram_base;
 194         /* Additions by Peter De Schrijver */
 195         unsigned char page_mask;          /* mask to select RAM page to Map*/
 196         unsigned char mapped_ram_size;    /* size of RAM page */
 197         __u32 sram;                       /* Shared memory base address */
 198         __u32 init_srb;                   /* Initial System Request Block address */
 199         __u32 srb;                        /* System Request Block address */
 200         __u32 ssb;                        /* System Status Block address */
 201         __u32 arb;                        /* Adapter Request Block address */
 202         __u32 asb;                        /* Adapter Status Block address */
 203         unsigned short exsap_station_id;
 204         unsigned short global_int_enable;
 205         struct sk_buff *current_skb;
 206         struct tr_statistics tr_stats;
 207         unsigned char auto_ringspeedsave;
 208         open_state open_status;
 209 };
 210 
 211 /* token ring adapter commands */
 212 #define DIR_INTERRUPT           0x00 /* struct srb_interrupt */
 213 #define DIR_MOD_OPEN_PARAMS     0x01
 214 #define DIR_OPEN_ADAPTER        0x03 /* struct dir_open_adapter */
 215 #define DIR_CLOSE_ADAPTER       0x04
 216 #define DIR_SET_GRP_ADDR        0x06
 217 #define DIR_SET_FUNC_ADDR       0x07
 218 #define DIR_READ_LOG            0x08 /* struct srb_read_log */
 219 #define DLC_OPEN_SAP            0x15 /* struct dlc_open_sap */
 220 #define DLC_CLOSE_SAP           0x16
 221 #define DATA_LOST               0x20 /* struct asb_rec */
 222 #define REC_DATA                0x81 /* struct arb_rec_req */
 223 #define XMIT_DATA_REQ           0x82 /* struct arb_xmit_req */
 224 #define DLC_STATUS              0x83 /* struct arb_dlc_status */
 225 #define RING_STAT_CHANGE        0x84 /* struct dlc_open_sap ??? */
 226 
 227 /* DIR_OPEN_ADAPTER options */
 228 #define OPEN_PASS_BCON_MAC 0x0100
 229 #define NUM_RCV_BUF 16
 230 #define RCV_BUF_LEN 136
 231 #define DHB_LENGTH 2048
 232 #define NUM_DHB 2
 233 #define DLC_MAX_SAP 2
 234 #define DLC_MAX_STA 1
 235 
 236 /* DLC_OPEN_SAP options */
 237 #define MAX_I_FIELD 0x0088
 238 #define SAP_OPEN_IND_SAP 0x04
 239 #define SAP_OPEN_PRIORITY 0x20
 240 #define SAP_OPEN_STATION_CNT 0x1
 241 #define XMIT_DIR_FRAME 0x0A
 242 #define XMIT_UI_FRAME  0x0d
 243 #define XMIT_XID_CMD   0x0e
 244 #define XMIT_TEST_CMD  0x11
 245 
 246 /* srb close return code */
 247 #define SIGNAL_LOSS  0x8000
 248 #define HARD_ERROR   0x4000
 249 #define XMIT_BEACON  0x1000
 250 #define LOBE_FAULT   0x0800
 251 #define AUTO_REMOVAL 0x0400
 252 #define REMOVE_RECV  0x0100
 253 #define LOG_OVERFLOW 0x0080
 254 #define RING_RECOVER 0x0020
 255 
 256 struct srb_init_response {
 257         unsigned char command;
 258         unsigned char init_status;
 259         unsigned char init_status_2;
 260         unsigned char reserved[3];
 261         __u16 bring_up_code;
 262         __u16 encoded_address;
 263         __u16 level_address;
 264         __u16 adapter_address;
 265         __u16 parms_address;
 266         __u16 mac_address;
 267 };
 268 
 269 struct dir_open_adapter {
 270         unsigned char command;
 271         char reserved[7];
 272         __u16 open_options;
 273         unsigned char node_address[6];
 274         unsigned char group_address[4];
 275         unsigned char funct_address[4];
 276         __u16 num_rcv_buf;
 277         __u16 rcv_buf_len;
 278         __u16 dhb_length;
 279         unsigned char num_dhb;
 280         char reserved2;
 281         unsigned char dlc_max_sap;
 282         unsigned char dlc_max_sta;
 283         unsigned char dlc_max_gsap;
 284         unsigned char dlc_max_gmem;
 285         unsigned char dlc_t1_tick_1;
 286         unsigned char dlc_t2_tick_1;
 287         unsigned char dlc_ti_tick_1;
 288         unsigned char dlc_t1_tick_2;
 289         unsigned char dlc_t2_tick_2;
 290         unsigned char dlc_ti_tick_2;
 291         unsigned char product_id[18];
 292 };
 293 
 294 struct srb_open_response {
 295         unsigned char command;
 296         unsigned char reserved1;
 297         unsigned char ret_code;
 298         unsigned char reserved2[3];
 299         __u16 error_code;
 300         __u16 asb_addr;
 301         __u16 srb_addr;
 302         __u16 arb_addr;
 303         __u16 ssb_addr;
 304 };
 305 
 306 struct dlc_open_sap {
 307         unsigned char command;
 308         unsigned char reserved1;
 309         unsigned char ret_code;
 310         unsigned char reserved2;
 311         __u16 station_id;
 312         unsigned char timer_t1;
 313         unsigned char timer_t2;
 314         unsigned char timer_ti;
 315         unsigned char maxout;
 316         unsigned char maxin;
 317         unsigned char maxout_incr;
 318         unsigned char max_retry_count;
 319         unsigned char gsap_max_mem;
 320         __u16 max_i_field;
 321         unsigned char sap_value;
 322         unsigned char sap_options;
 323         unsigned char station_count;
 324         unsigned char sap_gsap_mem;
 325         unsigned char gsap[0];
 326 };
 327 
 328 struct srb_xmit {
 329         unsigned char command;
 330         unsigned char cmd_corr;
 331         unsigned char ret_code;
 332         unsigned char reserved1;
 333         __u16 station_id;
 334 };
 335 
 336 struct srb_interrupt {
 337         unsigned char command;
 338         unsigned char cmd_corr;
 339         unsigned char ret_code;
 340 };
 341 
 342 struct srb_read_log {
 343         unsigned char command;
 344         unsigned char reserved1;
 345         unsigned char ret_code;
 346         unsigned char reserved2;
 347         unsigned char line_errors;
 348         unsigned char internal_errors;
 349         unsigned char burst_errors;
 350         unsigned char A_C_errors;
 351         unsigned char abort_delimiters;
 352         unsigned char reserved3;
 353         unsigned char lost_frames;
 354         unsigned char recv_congest_count;
 355         unsigned char frame_copied_errors;
 356         unsigned char frequency_errors;
 357         unsigned char token_errors;
 358 };
 359 
 360 struct asb_xmit_resp {
 361         unsigned char command;
 362         unsigned char cmd_corr;
 363         unsigned char ret_code;
 364         unsigned char reserved;
 365         __u16 station_id;
 366         __u16 frame_length;
 367         unsigned char hdr_length;
 368         unsigned char rsap_value;
 369 };
 370 
 371 struct arb_xmit_req {
 372         unsigned char command;
 373         unsigned char cmd_corr;
 374         unsigned char reserved1[2];
 375         __u16 station_id;
 376         __u16 dhb_address;
 377 };
 378 
 379 struct arb_rec_req {
 380         unsigned char command;
 381         unsigned char reserved1[3];
 382         __u16 station_id;
 383         __u16 rec_buf_addr;
 384         unsigned char lan_hdr_len;
 385         unsigned char dlc_hdr_len;
 386         __u16 frame_len;
 387         unsigned char msg_type;
 388 };
 389 
 390 struct asb_rec {
 391         unsigned char command;
 392         unsigned char reserved1;
 393         unsigned char ret_code;
 394         unsigned char reserved2;
 395         __u16 station_id;
 396         __u16 rec_buf_addr;
 397 };
 398 
 399 struct rec_buf {
 400         unsigned char reserved1[2];
 401         __u16 buf_ptr;
 402         unsigned char reserved2;
 403         __u16 buf_len;
 404         unsigned char data[0];
 405 };
 406 
 407 struct arb_dlc_status {
 408         unsigned char command;
 409         unsigned char reserved1[3];
 410         __u16 station_id;
 411         __u16 status;
 412         unsigned char frmr_data[5];
 413         unsigned char access_prio;
 414         unsigned char rem_addr[TR_ALEN];
 415         unsigned char rsap_value;
 416 };
 417 
 418 struct arb_ring_stat_change {
 419         unsigned char command;
 420         unsigned char reserved1[5];
 421         __u16 ring_status;
 422 };
 423 
 424 struct srb_close_adapter {
 425         unsigned char command;
 426         unsigned char reserved1;
 427         unsigned char ret_code;
 428 };
 429 

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