include/linux/pci.h

/* */
   1 /*
   2  * PCI defines and function prototypes
   3  * Copyright 1994, Drew Eckhardt
   4  *
   5  * For more information, please consult 
   6  * 
   7  * PCI BIOS Specification Revision
   8  * PCI Local Bus Specification
   9  * PCI System Design Guide
  10  *
  11  * PCI Special Interest Group
  12  * M/S HF3-15A
  13  * 5200 N.E. Elam Young Parkway
  14  * Hillsboro, Oregon 97124-6497
  15  * +1 (503) 696-2000 
  16  * +1 (800) 433-5177
  17  * 
  18  * Manuals are $25 each or $50 for all three, plus $7 shipping 
  19  * within the United States, $35 abroad.
  20  */
  21 
  22 
  23 
  24 /*      PROCEDURE TO REPORT NEW PCI DEVICES
  25  * We are trying to collect informations on new PCI devices, using
  26  * the standart PCI identification procedure. If some warning is
  27  * displayed at boot time, please report 
  28  *      - /proc/pci
  29  *      - your exact hardware description. Try to find out
  30  *        which device is unknown. It may be you mainboard chipset.
  31  *        PCI-CPU bridge or PCI-ISA bridge.
  32  *      - Send all that to frederic@cao-vlsi.ibp.fr, and I'll add
  33  *        your device to the list as soon as possible
  34  *              fred.
  35  */
  36 
  37 
  38 
  39 #ifndef PCI_H
  40 #define PCI_H
  41 
  42 /*
  43  * Under PCI, each device has 256 bytes of configuration address space,
  44  * of which the first 64 bytes are standardized as follows:
  45  */
  46 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  47 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  48 #define PCI_COMMAND             0x04    /* 16 bits */
  49 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  50 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
  51 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
  52 #define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
  53 #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
  54 #define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
  55 #define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
  56 #define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
  57 #define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
  58 #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
  59 
  60 #define PCI_STATUS              0x06    /* 16 bits */
  61 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  62 #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  63 #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  64 #define  PCI_STATUS_DEVSEL_FAST 0x000   
  65 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
  66 #define  PCI_STATUS_DEVSEL_SLOW 0x400
  67 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  68 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  69 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  70 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  71 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  72 
  73 #define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
  74                                            revision */
  75 #define PCI_REVISION_ID         0x08    /* Revision ID */
  76 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
  77 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
  78 
  79 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  80 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  81 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  82 #define PCI_BIST                0x0f    /* 8 bits */
  83 #define PCI_BIST_CODE_MASK      0x0f    /* Return result */
  84 #define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
  85 #define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */
  86 
  87 /*
  88  * Base addresses specify locations in memory or I/O space.
  89  * Decoded size can be determined by writing a value of 
  90  * 0xffffffff to the register, and reading it back.  Only 
  91  * 1 bits are decoded.
  92  */
  93 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
  94 #define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
  95 #define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
  96 #define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
  97 #define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
  98 #define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
  99 #define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
 100 #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
 101 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
 102 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
 103 #define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
 104 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M */
 105 #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
 106 #define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
 107 #define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0f)
 108 #define  PCI_BASE_ADDRESS_IO_MASK       (~0x03)
 109 /* bit 1 is reserved if address_space = 1 */
 110 
 111 /* 0x28-0x2f are reserved */
 112 #define PCI_ROM_ADDRESS         0x30    /* 32 bits */
 113 #define  PCI_ROM_ADDRESS_ENABLE 0x01    /* Write 1 to enable ROM,
 114                                            bits 31..11 are address,
 115                                            10..2 are reserved */
 116 /* 0x34-0x3b are reserved */
 117 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 118 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 119 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 120 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 121 
 122 #define PCI_CLASS_NOT_DEFINED           0x0000
 123 #define PCI_CLASS_NOT_DEFINED_VGA       0x0001
 124 
 125 #define PCI_BASE_CLASS_STORAGE          0x01
 126 #define PCI_CLASS_STORAGE_SCSI          0x0100
 127 #define PCI_CLASS_STORAGE_IDE           0x0101
 128 #define PCI_CLASS_STORAGE_FLOPPY        0x0102
 129 #define PCI_CLASS_STORAGE_IPI           0x0103
 130 #define PCI_CLASS_STORAGE_OTHER         0x0180
 131 
 132 #define PCI_BASE_CLASS_NETWORK          0x02
 133 #define PCI_CLASS_NETWORK_ETHERNET      0x0200
 134 #define PCI_CLASS_NETWORK_TOKEN_RING    0x0201
 135 #define PCI_CLASS_NETWORK_FDDI          0x0202
 136 #define PCI_CLASS_NETWORK_OTHER         0x0280
 137 
 138 #define PCI_BASE_CLASS_DISPLAY          0x03
 139 #define PCI_CLASS_DISPLAY_VGA           0x0300
 140 #define PCI_CLASS_DISPLAY_XGA           0x0301
 141 #define PCI_CLASS_DISPLAY_OTHER         0x0380
 142 
 143 #define PCI_BASE_CLASS_MULTIMEDIA       0x04
 144 #define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
 145 #define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
 146 #define PCI_CLASS_MULTIMEDIA_OTHER      0x0480
 147 
 148 #define PCI_BASE_CLASS_MEMORY           0x05
 149 #define  PCI_CLASS_MEMORY_RAM           0x0500
 150 #define  PCI_CLASS_MEMORY_FLASH         0x0501
 151 #define  PCI_CLASS_MEMORY_OTHER         0x0580
 152 
 153 #define PCI_BASE_CLASS_BRIDGE           0x06
 154 #define  PCI_CLASS_BRIDGE_HOST          0x0600
 155 #define  PCI_CLASS_BRIDGE_ISA           0x0601
 156 #define  PCI_CLASS_BRIDGE_EISA          0x0602
 157 #define  PCI_CLASS_BRIDGE_MC            0x0603
 158 #define  PCI_CLASS_BRIDGE_PCI           0x0604
 159 #define  PCI_CLASS_BRIDGE_PCMCIA        0x0605
 160 #define  PCI_CLASS_BRIDGE_OTHER         0x0680
 161 
 162 #define PCI_CLASS_OTHERS                0xff
 163 
 164 
 165 #define PCI_VENDOR_ID_NCR               0x1000
 166 #define PCI_DEVICE_ID_NCR_53C810        0x0001
 167 #define PCI_DEVICE_ID_NCR_53C815        0x0004
 168 #define PCI_DEVICE_ID_NCR_53C820        0x0002
 169 #define PCI_DEVICE_ID_NCR_53C825        0x0003
 170 
 171 #define PCI_VENDOR_ID_ADAPTEC           0x9004
 172 #define PCI_DEVICE_ID_ADAPTEC_2940      0x7178
 173 #define PCI_DEVICE_ID_ADAPTEC_294x      0x7078
 174 #define PCI_DEVICE_ID_ADAPTEC_7850      0x5078
 175 
 176 #define PCI_VENDOR_ID_DPT               0x1044   
 177 #define PCI_DEVICE_ID_DPT               0xa400  
 178 
 179 #define PCI_VENDOR_ID_S3                0x5333
 180 #define PCI_DEVICE_ID_S3_864_1          0x88c0
 181 #define PCI_DEVICE_ID_S3_864_2          0x88c1
 182 #define PCI_DEVICE_ID_S3_868            0x8880
 183 #define PCI_DEVICE_ID_S3_928            0x88b0
 184 #define PCI_DEVICE_ID_S3_964_1          0x88d0
 185 #define PCI_DEVICE_ID_S3_964_2          0x88d1
 186 #define PCI_DEVICE_ID_S3_811            0x8811
 187 #define PCI_DEVICE_ID_S3_968            0x88f0
 188 
 189 #define PCI_VENDOR_ID_OPTI              0x1045
 190 #define PCI_DEVICE_ID_OPTI_82C822       0xc822
 191 #define PCI_DEVICE_ID_OPTI_82C621       0xc621
 192 #define PCI_DEVICE_ID_OPTI_82C557       0xc557
 193 #define PCI_DEVICE_ID_OPTI_82C558       0xc558
 194 
 195 #define PCI_VENDOR_ID_UMC               0x1060
 196 #define PCI_DEVICE_ID_UMC_UM8881F       0x8881
 197 #define PCI_DEVICE_ID_UMC_UM8891A       0x0891
 198 #define PCI_DEVICE_ID_UMC_UM8886F       0x8886
 199 #define PCI_DEVICE_ID_UMC_UM8886A       0x886a
 200 #define PCI_DEVICE_ID_UMC_UM8673F       0x0101
 201 
 202 #define PCI_VENDOR_ID_DEC               0x1011
 203 #define PCI_DEVICE_ID_DEC_TULIP         0x0002
 204 #define PCI_DEVICE_ID_DEC_TULIP_FAST    0x0009
 205 #define PCI_DEVICE_ID_DEC_TULIP_PLUS    0x0014
 206 #define PCI_DEVICE_ID_DEC_FDDI          0x000F
 207 #define PCI_DEVICE_ID_DEC_BRD           0x0001
 208 
 209 #define PCI_VENDOR_ID_MATROX            0x102B
 210 #define PCI_DEVICE_ID_MATROX_MGA_2      0x0518
 211 #define PCI_DEVICE_ID_MATROX_MGA_IMP    0x0d10
 212 
 213 #define PCI_VENDOR_ID_INTEL             0x8086
 214 #define PCI_DEVICE_ID_INTEL_82378       0x0484
 215 #define PCI_DEVICE_ID_INTEL_82424       0x0483
 216 #define PCI_DEVICE_ID_INTEL_82375       0x0482
 217 #define PCI_DEVICE_ID_INTEL_82434       0x04a3
 218 #define PCI_DEVICE_ID_INTEL_82430       0x0486
 219 #define PCI_DEVICE_ID_INTEL_82437       0x122d
 220 #define PCI_DEVICE_ID_INTEL_82371       0x122e
 221 #define PCI_DEVICE_ID_INTEL_82438       0x1230
 222 #define PCI_DEVICE_ID_INTEL_7116        0x1223
 223 
 224 #define PCI_VENDOR_ID_SMC               0x1042
 225 #define PCI_DEVICE_ID_SMC_37C665        0x1000
 226 
 227 #define PCI_VENDOR_ID_ATI               0x1002
 228 #define PCI_DEVICE_ID_ATI_M32           0x4158
 229 #define PCI_DEVICE_ID_ATI_M64           0x4758
 230 
 231 #define PCI_VENDOR_ID_WEITEK            0x100e
 232 #define PCI_DEVICE_ID_WEITEK_P9000      0x9001
 233 #define PCI_DEVICE_ID_WEITEK_P9100      0x9100
 234 
 235 #define PCI_VENDOR_ID_CIRRUS            0x1013
 236 #define PCI_DEVICE_ID_CIRRUS_5430       0x00A0
 237 #define PCI_DEVICE_ID_CIRRUS_5434_4     0x00A4
 238 #define PCI_DEVICE_ID_CIRRUS_5434_8     0x00A8
 239 #define PCI_DEVICE_ID_CIRRUS_6729       0x1100
 240 #define PCI_DEVICE_ID_CIRRUS_7542       0x1200
 241 
 242 #define PCI_VENDOR_ID_BUSLOGIC          0x104B
 243 #define PCI_DEVICE_ID_BUSLOGIC_946C     0x1040
 244 #define PCI_DEVICE_ID_BUSLOGIC_946C_2   0x0140
 245 
 246 #define PCI_VENDOR_ID_N9                0x105D
 247 #define PCI_DEVICE_ID_N9_I128           0x2309
 248 
 249 #define PCI_VENDOR_ID_AI                0x1025
 250 #define PCI_DEVICE_ID_AI_M1435          0x1435
 251 
 252 #define PCI_VENDOR_ID_AL                0x10b9
 253 #define PCI_DEVICE_ID_AL_M1445          0x1445
 254 #define PCI_DEVICE_ID_AL_M1449          0x1449
 255 #define PCI_DEVICE_ID_AL_M1451          0x1451
 256 #define PCI_DEVICE_ID_AL_M4803          0x5215
 257 
 258 #define PCI_VENDOR_ID_TSENG             0x100c
 259 #define PCI_DEVICE_ID_TSENG_W32P_2      0x3202
 260 #define PCI_DEVICE_ID_TSENG_W32P_b      0x3205
 261 #define PCI_DEVICE_ID_TSENG_W32P_c      0x3206
 262 #define PCI_DEVICE_ID_TSENG_W32P_d      0x3207
 263 
 264 #define PCI_VENDOR_ID_CMD               0x1095
 265 #define PCI_DEVICE_ID_CMD_640           0x0640
 266 
 267 #define PCI_VENDOR_ID_VISION            0x1098
 268 #define PCI_DEVICE_ID_VISION_QD8500     0x0001
 269 #define PCI_DEVICE_ID_VISION_QD8580     0x0002
 270 
 271 #define PCI_VENDOR_ID_AMD               0x1022
 272 #define PCI_DEVICE_ID_AMD_LANCE         0x2000
 273 #define PCI_DEVICE_ID_AMD_SCSI          0x2020
 274 
 275 #define PCI_VENDOR_ID_VLSI              0x1004
 276 #define PCI_DEVICE_ID_VLSI_82C593       0x0006
 277 #define PCI_DEVICE_ID_VLSI_82C592       0x0005
 278 
 279 #define PCI_VENDOR_ID_ADL               0x1005
 280 #define PCI_DEVICE_ID_ADL_2301          0x2301
 281 
 282 #define PCI_VENDOR_ID_SYMPHONY          0x1c1c
 283 #define PCI_DEVICE_ID_SYMPHONY_101      0x0001
 284 
 285 #define PCI_VENDOR_ID_TRIDENT           0x1023
 286 #define PCI_DEVICE_ID_TRIDENT_9420      0x9420
 287 #define PCI_DEVICE_ID_TRIDENT_9440      0x9440
 288 
 289 #define PCI_VENDOR_ID_CONTAQ            0x1080
 290 #define PCI_DEVICE_ID_CONTAQ_82C599     0x0600
 291 
 292 #define PCI_VENDOR_ID_NS                0x100b
 293 #define PCI_DEVICE_ID_NS_87410          0xd001
 294 
 295 #define PCI_VENDOR_ID_VIA               0x1106
 296 #define PCI_DEVICE_ID_VIA_82C505        0x0505
 297 #define PCI_DEVICE_ID_VIA_82C576        0x0576
 298 #define PCI_DEVICE_ID_VIA_82C561        0x0561
 299 
 300 #define PCI_VENDOR_ID_SI                0x1039
 301 #define PCI_DEVICE_ID_SI_496            0x0496
 302 #define PCI_DEVICE_ID_SI_501            0x0406
 303 #define PCI_DEVICE_ID_SI_503            0x0008
 304 #define PCI_DEVICE_ID_SI_601            0x0601
 305 
 306 #define PCI_VENDOR_ID_LEADTEK           0x107d
 307 #define PCI_DEVICE_ID_LEADTEK_805       0x0000
 308 
 309 #define PCI_VENDOR_ID_IMS               0x10e0
 310 #define PCI_DEVICE_ID_IMS_8849          0x8849
 311 
 312 #define PCI_VENDOR_ID_ZEINET            0x1193
 313 #define PCI_DEVICE_ID_ZEINET_1221       0x0001
 314 
 315 #define PCI_VENDOR_ID_EF                0x111a
 316 #define PCI_DEVICE_ID_EF_ATM            0x0000
 317 
 318 #define PCI_VENDOR_ID_HER               0xedd8
 319 #define PCI_DEVICE_ID_HER_STING         0xa091
 320 
 321 #define PCI_VENDOR_ID_ATRONICS          0x907f
 322 #define PCI_DEVICE_ID_ATRONICS_2015     0x2015
 323 
 324 #define PCI_VENDOR_ID_CT                0x102c
 325 #define PCI_DEVICE_ID_CT_65545          0x00d8
 326 
 327 #define PCI_VENDOR_ID_FD                0x1036
 328 #define PCI_DEVICE_ID_FD_36C70          0x0000
 329 
 330 #define PCI_VENDOR_ID_WINBOND           0x10ad
 331 #define PCI_DEVICE_ID_WINBOND_83769     0x0001
 332 
 333 #define PCI_VENDOR_ID_3COM              0x10b7
 334 #define PCI_DEVICE_ID_3COM_3C590        0x5900
 335 #define PCI_DEVICE_ID_3COM_3C595TX      0x5950
 336 #define PCI_DEVICE_ID_3COM_3C595T4      0x5951
 337 #define PCI_DEVICE_ID_3COM_3C595MII     0x5952
 338 
 339 #define PCI_VENDOR_ID_PROMISE           0x105a
 340 #define PCI_DEVICE_ID_PROMISE_5300      0x5300
 341 
 342 #define PCI_VENDOR_ID_QLOGIC            0x1077
 343 #define PCI_DEVICE_ID_QLOGIC_ISP1020    0x1020
 344 #define PCI_DEVICE_ID_QLOGIC_ISP1022    0x1022
 345 
 346 #define PCI_VENDOR_ID_X                 0x1061
 347 #define PCI_DEVICE_ID_X_AGX016          0x0001
 348 
 349 #define PCI_VENDOR_ID_ACC               0x10aa
 350 
 351 #define PCI_VENDOR_ID_VORTEX            0x1119
 352 #define PCI_DEVICE_ID_VORTEX_GDT        0x0001
 353 
 354 
 355 /*
 356  * The PCI interface treats multi-function devices as independent
 357  * devices.  The slot/function address of each device is encoded
 358  * in a single byte as follows:
 359  *
 360  *      7:4 = slot
 361  *      3:0 = function
 362  */
 363 #define PCI_DEVFN(slot,func)    ((((slot) & 0x1f) << 3) | ((func) & 0x07))
 364 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
 365 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
 366 
 367 /*
 368  * There is one pci_dev structure for each slot-number/function-number
 369  * combination:
 370  */
 371 struct pci_dev {
 372         struct pci_bus  *bus;           /* bus this device is on */
 373         struct pci_dev  *sibling;       /* next device on this bus */
 374         struct pci_dev  *next;          /* chain of all devices */
 375 
 376         void            *sysdata;       /* hook for sys-specific extension */
 377 
 378         unsigned int    devfn;          /* encoded device & function index */
 379         unsigned short  vendor;
 380         unsigned short  device;
 381         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
 382         unsigned int    master : 1;     /* set if device is master capable */
 383         /*
 384          * In theory, the irq level can be read from configuration
 385          * space and all would be fine.  However, old PCI chips don't
 386          * support these registers and return 0 instead.  For example,
 387          * the Vision864-P rev 0 chip can uses INTA, but returns 0 in
 388          * the interrupt line and pin registers.  pci_init()
 389          * initializes this field with the value at PCI_INTERRUPT_LINE
 390          * and it is the job of pcibios_fixup() to change it if
 391          * necessary.  The field must not be 0 unless the device
 392          * cannot generate interrupts at all.
 393          */
 394         unsigned char   irq;            /* irq generated by this device */
 395 };
 396 
 397 struct pci_bus {
 398         struct pci_bus  *parent;        /* parent bus this bridge is on */
 399         struct pci_bus  *children;      /* chain of P2P bridges on this bus */
 400         struct pci_bus  *next;          /* chain of all PCI buses */
 401 
 402         struct pci_dev  *self;          /* bridge device as seen by parent */
 403         struct pci_dev  *devices;       /* devices behind this bridge */
 404 
 405         void            *sysdata;       /* hook for sys-specific extension */
 406 
 407         unsigned char   number;         /* bus number */
 408         unsigned char   primary;        /* number of primary bridge */
 409         unsigned char   secondary;      /* number of secondary bridge */
 410         unsigned char   subordinate;    /* max number of subordinate buses */
 411 };
 412 
 413 /*
 414  * This is used to map a vendor-id/device-id pair into device-specific
 415  * information.
 416  */
 417 struct pci_dev_info {
 418         unsigned short  vendor;         /* vendor id */
 419         unsigned short  device;         /* device id */
 420 
 421         const char      *name;          /* device name */
 422         unsigned char   bridge_type;    /* bridge type or 0xff */
 423 };
 424 
 425 extern struct pci_bus   pci_root;       /* root bus */
 426 extern struct pci_dev   *pci_devices;   /* list of all devices */
 427 
 428 
 429 extern unsigned long pci_init (unsigned long mem_start, unsigned long mem_end);
 430 
 431 extern struct pci_dev_info *pci_lookup_dev (unsigned int vendor,
 432                                             unsigned int dev);
 433 extern char *pci_strbioserr (int error);
 434 extern const char *pci_strclass (unsigned int class);
 435 extern const char *pci_strvendor (unsigned int vendor);
 436 extern const char *pci_strdev (unsigned int vendor, unsigned int device);
 437 
 438 extern int get_pci_list (char *buf);
 439 
 440 #endif /* PCI_H */
/* */
root/include/linux/pci.h

INCLUDED FROM
