root/arch/alpha/kernel/bios32.c

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DEFINITIONS

This source file includes following definitions.
  1. pcibios_present
  2. disable_dev
  3. layout_dev
  4. layout_bus
  5. pcibios_find_device
  6. pcibios_find_class
  7. pcibios_present
  8. pcibios_init
  9. enable_ide
  10. bridge_swizzle
  11. common_fixup
  12. eb66p_fixup
  13. cabriolet_fixup
  14. eb66_and_eb64p_fixup
  15. sio_fixup
  16. pcibios_fixup
  17. pcibios_strerror

   1 /*
   2  * bios32.c - PCI BIOS functions for Alpha systems not using BIOS
   3  *            emulation code.
   4  *
   5  * Written by Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *
   7  * Adapted to 64-bit kernel and then rewritten by David Mosberger
   8  * (davidm@cs.arizona.edu)
   9  *
  10  * For more information, please consult
  11  *
  12  * PCI BIOS Specification Revision
  13  * PCI Local Bus Specification
  14  * PCI System Design Guide
  15  *
  16  * PCI Special Interest Group
  17  * M/S HF3-15A
  18  * 5200 N.E. Elam Young Parkway
  19  * Hillsboro, Oregon 97124-6497
  20  * +1 (503) 696-2000
  21  * +1 (800) 433-5177
  22  *
  23  * Manuals are $25 each or $50 for all three, plus $7 shipping
  24  * within the United States, $35 abroad.
  25  */
  26 #include <linux/config.h>
  27 
  28 #ifndef CONFIG_PCI
  29 
  30 int pcibios_present(void)
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  31 {
  32         return 0;
  33 }
  34 
  35 #else /* CONFIG_PCI */
  36 
  37 #include <linux/kernel.h>
  38 #include <linux/bios32.h>
  39 #include <linux/pci.h>
  40 #include <linux/malloc.h>
  41 #include <linux/mm.h>
  42 
  43 #include <asm/hwrpb.h>
  44 #include <asm/io.h>
  45 
  46 
  47 #define KB              1024
  48 #define MB              (1024*KB)
  49 #define GB              (1024*MB)
  50 
  51 #define MAJOR_REV       0
  52 #define MINOR_REV       3
  53 
  54 /*
  55  * Align VAL to ALIGN, which must be a power of two.
  56  */
  57 #define ALIGN(val,align)        (((val) + ((align) - 1)) & ~((align) - 1))
  58 
  59 
  60 /*
  61  * Temporary internal macro.  If this 0, then do not write to any of
  62  * the PCI registers, merely read them (i.e., use configuration as
  63  * determined by SRM).  The SRM seem do be doing a less than perfect
  64  * job in configuring PCI devices, so for now we do it ourselves.
  65  * Reconfiguring PCI devices breaks console (RPB) callbacks, but
  66  * those don't work properly with 64 bit addresses anyways.
  67  *
  68  * The accepted convention seems to be that the console (POST
  69  * software) should fully configure boot devices and configure the
  70  * interrupt routing of *all* devices.  In particular, the base
  71  * addresses of non-boot devices need not be initialized.  For
  72  * example, on the AXPpci33 board, the base address a #9 GXE PCI
  73  * graphics card reads as zero (this may, however, be due to a bug in
  74  * the graphics card---there have been some rumor that the #9 BIOS
  75  * incorrectly resets that address to 0...).
  76  */
  77 #define PCI_MODIFY              1
  78 
  79 extern struct hwrpb_struct *hwrpb;
  80 
  81 
  82 #if PCI_MODIFY
  83 
  84 #if 0
  85 static unsigned int     io_base  = 64*KB;       /* <64KB are (E)ISA ports */
  86 #else
  87 static unsigned int     io_base  = 0xb000;
  88 #endif
  89 
  90 #if defined(CONFIG_ALPHA_XL)
  91 /*
  92    an AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
  93    that get passed through the PCI<->ISA bridge chip. Because this causes
  94    us to set the PCI->Mem window bases lower than normal, we've gotta allocate
  95    PCI bus devices' memory addresses *above* the PCI<->memory mapping windows,
  96    so that CPU memory DMA addresses issued by a bus device don't conflict
  97    with bus memory addresses, like frame buffer memory for graphics cards.
  98 */
  99 static unsigned int     mem_base = 1024*MB;
 100 #else /* CONFIG_ALPHA_XL */
 101 static unsigned int     mem_base = 16*MB;       /* <16MB is ISA memory */
 102 #endif /* CONFIG_ALPHA_XL */
 103 
 104 /*
 105  * Disable PCI device DEV so that it does not respond to I/O or memory
 106  * accesses.
 107  */
 108 static void disable_dev(struct pci_dev *dev)
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 109 {
 110         struct pci_bus *bus;
 111         unsigned short cmd;
 112 
 113         bus = dev->bus;
 114         pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
 115 
 116         /* hack, turn it off first... */
 117         cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
 118         pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND, cmd);
 119 }
 120 
 121 
 122 /*
 123  * Layout memory and I/O for a device:
 124  */
 125 #define MAX(val1, val2) ( ((val1) > (val2)) ? val1 : val2)
 126 
 127 static void layout_dev(struct pci_dev *dev)
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 128 {
 129         struct pci_bus *bus;
 130         unsigned short cmd;
 131         unsigned int base, mask, size, reg;
 132         unsigned int alignto;
 133 
 134         bus = dev->bus;
 135         pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
 136 
 137         for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
 138                 /*
 139                  * Figure out how much space and of what type this
 140                  * device wants.
 141                  */
 142                 pcibios_write_config_dword(bus->number, dev->devfn, reg,
 143                                            0xffffffff);
 144                 pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
 145                 if (!base) {
 146                         /* this base-address register is unused */
 147                         continue;
 148                 }
 149 
 150                 /*
 151                  * We've read the base address register back after
 152                  * writing all ones and so now we must decode it.
 153                  */
 154                 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
 155                         /*
 156                          * I/O space base address register.
 157                          */
 158                         cmd |= PCI_COMMAND_IO;
 159 
 160                         base &= PCI_BASE_ADDRESS_IO_MASK;
 161                         mask = (~base << 1) | 0x1;
 162                         size = (mask & base) & 0xffffffff;
 163                         /* align to multiple of size of minimum base */
 164                         alignto = MAX(0x400, size) ;
 165                         base = ALIGN(io_base, alignto );
 166                         io_base = base + size;
 167                         pcibios_write_config_dword(bus->number, dev->devfn, 
 168                                                    reg, base | 0x1);
 169                 } else {
 170                         unsigned int type;
 171                         /*
 172                          * Memory space base address register.
 173                          */
 174                         cmd |= PCI_COMMAND_MEMORY;
 175                         type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 176                         base &= PCI_BASE_ADDRESS_MEM_MASK;
 177                         mask = (~base << 1) | 0x1;
 178                         size = (mask & base) & 0xffffffff;
 179                         switch (type) {
 180                               case PCI_BASE_ADDRESS_MEM_TYPE_32:
 181                                 break;
 182 
 183                               case PCI_BASE_ADDRESS_MEM_TYPE_64:
 184                                 printk("bios32 WARNING: "
 185                                        "ignoring 64-bit device in "
 186                                        "slot %d, function %d: \n",
 187                                        PCI_SLOT(dev->devfn),
 188                                        PCI_FUNC(dev->devfn));
 189                                 reg += 4;       /* skip extra 4 bytes */
 190                                 continue;
 191 
 192                               case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 193                                 /*
 194                                  * Allocating memory below 1MB is *very*
 195                                  * tricky, as there may be all kinds of
 196                                  * ISA devices lurking that we don't know
 197                                  * about.  For now, we just cross fingers
 198                                  * and hope nobody tries to do this on an
 199                                  * Alpha (or that the console has set it
 200                                  * up properly).
 201                                  */
 202                                 printk("bios32 WARNING: slot %d, function %d "
 203                                        "requests memory below 1MB---don't "
 204                                        "know how to do that.\n",
 205                                        PCI_SLOT(dev->devfn),
 206                                        PCI_FUNC(dev->devfn));
 207                                 continue;
 208                         }
 209                         /*
 210                          * The following holds at least for the Low Cost
 211                          * Alpha implementation of the PCI interface:
 212                          *
 213                          * In sparse memory address space, the first
 214                          * octant (16MB) of every 128MB segment is
 215                          * aliased to the the very first 16MB of the
 216                          * address space (i.e., it aliases the ISA
 217                          * memory address space).  Thus, we try to
 218                          * avoid allocating PCI devices in that range.
 219                          * Can be allocated in 2nd-7th octant only.
 220                          * Devices that need more than 112MB of
 221                          * address space must be accessed through
 222                          * dense memory space only!
 223                          */
 224                         /* align to multiple of size of minimum base */
 225                         alignto = MAX(0x1000, size) ;
 226                         base = ALIGN(mem_base, alignto);
 227                         if (size > 7 * 16*MB) {
 228                                 printk("bios32 WARNING: slot %d, function %d "
 229                                        "requests  %dB of contiguous address "
 230                                        " space---don't use sparse memory "
 231                                        " accesses on this device!!\n",
 232                                        PCI_SLOT(dev->devfn),
 233                                        PCI_FUNC(dev->devfn), size);
 234                         } else {
 235                                 if (((base / (16*MB)) & 0x7) == 0) {
 236                                         base &= ~(128*MB - 1);
 237                                         base += 16*MB;
 238                                         base  = ALIGN(base, alignto);
 239                                 }
 240                                 if (base / (128*MB) != (base + size) / (128*MB)) {
 241                                         base &= ~(128*MB - 1);
 242                                         base += (128 + 16)*MB;
 243                                         base  = ALIGN(base, alignto);
 244                                 }
 245                         }
 246                         mem_base = base + size;
 247                         pcibios_write_config_dword(bus->number, dev->devfn,
 248                                                    reg, base);
 249                 }
 250         }
 251         /* enable device: */
 252         if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
 253             dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
 254             dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
 255             dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
 256         {
 257                 /*
 258                  * All of these (may) have I/O scattered all around
 259                  * and may not use i/o-base address registers at all.
 260                  * So we just have to always enable I/O to these
 261                  * devices.
 262                  */
 263                 cmd |= PCI_COMMAND_IO;
 264         }
 265 
 266         pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
 267                                   cmd | PCI_COMMAND_MASTER);
 268 }
 269 
 270 
 271 static void layout_bus(struct pci_bus *bus)
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 272 {
 273         unsigned int l, tio, bio, tmem, bmem;
 274         struct pci_bus *child;
 275         struct pci_dev *dev;
 276 
 277         if (!bus->devices && !bus->children)
 278           return;
 279 
 280         /*
 281          * Align the current bases on appropriate boundaries (4K for
 282          * IO and 1MB for memory).
 283          */
 284         bio = io_base = ALIGN(io_base, 4*KB);
 285         bmem = mem_base = ALIGN(mem_base, 1*MB);
 286 
 287         /*
 288          * There are times when the PCI devices have already been
 289          * setup (e.g., by MILO or SRM).  In these cases there is a
 290          * window during which two devices may have an overlapping
 291          * address range.  To avoid this causing trouble, we first
 292          * turn off the I/O and memory address decoders for all PCI
 293          * devices.  They'll be re-enabled only once all address
 294          * decoders are programmed consistently.
 295          */
 296         for (dev = bus->devices; dev; dev = dev->sibling) {
 297                 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
 298                         disable_dev(dev) ;
 299                 }
 300         }
 301 
 302         /*
 303          * Allocate space to each device:
 304          */
 305         for (dev = bus->devices; dev; dev = dev->sibling) {
 306                 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
 307                         layout_dev(dev);
 308                 }
 309         }
 310         /*
 311          * Recursively allocate space for all of the sub-buses:
 312          */
 313         for (child = bus->children; child; child = child->next) {
 314                 layout_bus(child);
 315         }
 316         /*
 317          * Align the current bases on 4K and 1MB boundaries:
 318          */
 319         tio = io_base = ALIGN(io_base, 4*KB);
 320         tmem = mem_base = ALIGN(mem_base, 1*MB);
 321 
 322         if (bus->self) {
 323                 struct pci_dev *bridge = bus->self;
 324                 /*
 325                  * Set up the top and bottom of the PCI I/O segment
 326                  * for this bus.
 327                  */
 328                 pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
 329                                           0x1c, &l);
 330                 l = (l & 0xffff0000) | (bio >> 8) | ((tio - 1) & 0xf000);
 331                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 332                                            0x1c, l);
 333                 /*
 334                  * Set up the top and bottom of the  PCI Memory segment
 335                  * for this bus.
 336                  */
 337                 l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
 338                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 339                                            0x20, l);
 340                 /*
 341                  * Turn off downstream PF memory address range:
 342                  */
 343                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 344                                            0x24, 0x0000ffff);
 345                 /*
 346                  * Tell bridge that there is an ISA bus in the system:
 347                  */
 348                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 349                                            0x3c, 0x00040000);
 350                 /*
 351                  * Clear status bits, enable I/O (for downstream I/O),
 352                  * turn on master enable (for upstream I/O), turn on
 353                  * memory enable (for downstream memory), turn on
 354                  * master enable (for upstream memory and I/O).
 355                  */
 356                 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
 357                                            0x4, 0xffff0007);
 358         }
 359 }
 360 
 361 #endif /* !PCI_MODIFY */
 362 
 363 
 364 /*
 365  * Given the vendor and device ids, find the n'th instance of that device
 366  * in the system.  
 367  */
 368 int pcibios_find_device (unsigned short vendor, unsigned short device_id,
     /* [previous][next][first][last][top][bottom][index][help] */
 369                          unsigned short index, unsigned char *bus,
 370                          unsigned char *devfn)
 371 {
 372         unsigned int curr = 0;
 373         struct pci_dev *dev;
 374 
 375         for (dev = pci_devices; dev; dev = dev->next) {
 376                 if (dev->vendor == vendor && dev->device == device_id) {
 377                         if (curr == index) {
 378                                 *devfn = dev->devfn;
 379                                 *bus = dev->bus->number;
 380                                 return PCIBIOS_SUCCESSFUL;
 381                         }
 382                         ++curr;
 383                 }
 384         }
 385         return PCIBIOS_DEVICE_NOT_FOUND;
 386 }
 387 
 388 
 389 /*
 390  * Given the class, find the n'th instance of that device
 391  * in the system.
 392  */
 393 int pcibios_find_class (unsigned int class_code, unsigned short index,
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 394                         unsigned char *bus, unsigned char *devfn)
 395 {
 396         unsigned int curr = 0;
 397         struct pci_dev *dev;
 398 
 399         for (dev = pci_devices; dev; dev = dev->next) {
 400                 if (dev->class == class_code) {
 401                         if (curr == index) {
 402                                 *devfn = dev->devfn;
 403                                 *bus = dev->bus->number;
 404                                 return PCIBIOS_SUCCESSFUL;
 405                         }
 406                         ++curr;
 407                 }
 408         }
 409         return PCIBIOS_DEVICE_NOT_FOUND;
 410 }
 411 
 412 
 413 int pcibios_present(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 414 {
 415         return 1;
 416 }
 417 
 418 
 419 unsigned long pcibios_init(unsigned long mem_start,
     /* [previous][next][first][last][top][bottom][index][help] */
 420                            unsigned long mem_end)
 421 {
 422         printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
 423 
 424 #if !PCI_MODIFY
 425         printk("...NOT modifying existing (SRM) PCI configuration\n");
 426 #endif
 427         return mem_start;
 428 }
 429 
 430 /*
 431  * The SRM console *disables* the IDE interface, this code ensures its
 432  * enabled.
 433  *
 434  * This code bangs on a control register of the 87312 Super I/O chip
 435  * that implements parallel port/serial ports/IDE/FDI.  Depending on
 436  * the motherboard, the Super I/O chip can be configured through a
 437  * pair of registers that are located either at I/O ports 0x26e/0x26f
 438  * or 0x398/0x399.  Unfortunately, autodetecting which base address is
 439  * in use works only once (right after a reset).  The Super I/O chip
 440  * has the additional quirk that configuration register data must be
 441  * written twice (I believe this is a safety feature to prevent
 442  * accidental modification---fun, isn't it?).
 443  */
 444 static inline void enable_ide(long ide_base)
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 445 {
 446         int data;
 447 
 448         outb(0, ide_base);              /* set the index register for reg #0 */
 449         data = inb(ide_base+1);         /* read the current contents */
 450         outb(0, ide_base);              /* set the index register for reg #0 */
 451         outb(data | 0x40, ide_base+1);  /* turn on IDE */
 452         outb(data | 0x40, ide_base+1);  /* turn on IDE, really! */
 453 }
 454 
 455 /* 
 456  * A small note about bridges and interrupts.    The DECchip 21050 (and later chips)
 457  * adheres to the PCI-PCI bridge specification.   This says that the interrupts on
 458  * the other side of a bridge are swizzled in the following manner:
 459  *
 460  * Dev    Interrupt   Interrupt 
 461  *        Pin on      Pin on 
 462  *        Device      Connector
 463  *
 464  *   4    A           A
 465  *        B           B
 466  *        C           C
 467  *        D           D
 468  * 
 469  *   5    A           B
 470  *        B           C
 471  *        C           D
 472  *        D           A
 473  *
 474  *   6    A           C
 475  *        B           D
 476  *        C           A
 477  *        D           B
 478  *
 479  *   7    A           D
 480  *        B           A
 481  *        C           B
 482  *        D           C
 483  *
 484  *   Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
 485  *   Thus, each swizzle is ((pin-1) + (device#-4)) % 4
 486  *
 487  *   The following code is somewhat simplistic as it assumes only one bridge.
 488  *   I will fix it later (david.rusling@reo.mts.dec.com).
 489  */
 490 static inline unsigned char bridge_swizzle(unsigned char pin, unsigned int slot) 
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 491 {
 492         /* swizzle */
 493         return (((pin-1) + slot) % 4) + 1 ;
 494 }
 495 
 496 /*
 497  * Most evaluation boards share most of the fixup code, which is isolated here.
 498  * This function is declared "inline" as only one platform will ever be selected
 499  * in any given kernel.  If that platform doesn't need this code, we don't want
 500  * it around as dead code.
 501  */
 502 static inline void common_fixup(long min_idsel, long max_idsel, long irqs_per_slot,
     /* [previous][next][first][last][top][bottom][index][help] */
 503                                 char irq_tab[max_idsel - min_idsel + 1][irqs_per_slot],
 504                                 long ide_base)
 505 {
 506         struct pci_dev *dev;
 507         unsigned char pin;
 508         unsigned char slot ;
 509 
 510         /*
 511          * Go through all devices, fixing up irqs as we see fit:
 512          */
 513         for (dev = pci_devices; dev; dev = dev->next) {
 514                 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
 515                         dev->irq = 0;
 516                         /*
 517                          * This device is not on the primary bus, we need to figure out which
 518                          * interrupt pin it will come in on.   We know which slot it will come
 519                          * in on 'cos that slot is where the bridge is.   Each time the interrupt
 520                          * line passes through a PCI-PCI bridge we must apply the swizzle function
 521                          * (see the inline static routine above).
 522                          */
 523                         if (dev->bus->number != 0) {
 524                                 struct pci_dev *curr = dev ;
 525                                 /* read the pin and do the PCI-PCI bridge interrupt pin swizzle */
 526                                 pcibios_read_config_byte(dev->bus->number, dev->devfn,
 527                                                          PCI_INTERRUPT_PIN, &pin);
 528                                 /* cope with 0 */
 529                                 if (pin == 0) pin = 1 ;
 530                                 /* follow the chain of bridges, swizzling as we go */
 531                                 do {
 532                                         /* swizzle */
 533                                         pin = bridge_swizzle(pin, PCI_SLOT(curr->devfn)) ;
 534                                         /* move up the chain of bridges */
 535                                         curr = curr->bus->self ;
 536                                 } while (curr->bus->self) ;
 537                                 /* The slot is the slot of the last bridge. */
 538                                 slot = PCI_SLOT(curr->devfn) ;
 539                         } else {
 540                                 /* work out the slot */
 541                                 slot = PCI_SLOT(dev->devfn) ;
 542                                 /* read the pin */
 543                                 pcibios_read_config_byte(dev->bus->number, dev->devfn,
 544                                                  PCI_INTERRUPT_PIN, &pin);
 545                         }
 546                         if (irq_tab[slot - min_idsel][pin] != -1)
 547                                 dev->irq = irq_tab[slot - min_idsel][pin];
 548 #if PCI_MODIFY
 549                         /* tell the device: */
 550                         pcibios_write_config_byte(dev->bus->number, dev->devfn,
 551                                                   PCI_INTERRUPT_LINE, dev->irq);
 552 #endif
 553                         /*
 554                          * if its a VGA, enable its BIOS ROM at C0000
 555                          */
 556                         if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
 557                           pcibios_write_config_dword(dev->bus->number, dev->devfn,
 558                                                      PCI_ROM_ADDRESS,
 559                                                      0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
 560                         }
 561                 }
 562 
 563                 if (ide_base) {
 564                         enable_ide(ide_base);
 565                 }
 566         }
 567 }
 568 
 569 /*
 570  * The EB66+ is very similar to the EB66 except that it does not have
 571  * the on-board NCR and Tulip chips.  In the code below, I have used
 572  * slot number to refer to the id select line and *not* the slot
 573  * number used in the EB66+ documentation.  However, in the table,
 574  * I've given the slot number, the id select line and the Jxx number
 575  * that's printed on the board.  The interrupt pins from the PCI slots
 576  * are wired into 3 interrupt summary registers at 0x804, 0x805 and
 577  * 0x806 ISA.
 578  *
 579  * In the table, -1 means don't assign an IRQ number.  This is usually
 580  * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 581  */
 582 static inline void eb66p_fixup(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 583 {
 584         char irq_tab[5][5] = {
 585                 {16+0, 16+0, 16+5,  16+9, 16+13},       /* IdSel 6,  slot 0, J25 */
 586                 {16+1, 16+1, 16+6, 16+10, 16+14},       /* IdSel 7,  slot 1, J26 */
 587                 {  -1,   -1,   -1,    -1,    -1},       /* IdSel 8,  SIO         */
 588                 {16+2, 16+2, 16+7, 16+11, 16+15},       /* IdSel 9,  slot 2, J27 */
 589                 {16+3, 16+3, 16+8, 16+12,  16+6}        /* IdSel 10, slot 3, J28 */
 590         };
 591         common_fixup(6, 10, 5, irq_tab, 0x398);
 592 }
 593 
 594 
 595 /*
 596  * The AlphaPC64 is very similar to the EB66+ except that its slots
 597  * are numbered differently.  In the code below, I have used slot
 598  * number to refer to the id select line and *not* the slot number
 599  * used in the AlphaPC64 documentation.  However, in the table, I've
 600  * given the slot number, the id select line and the Jxx number that's
 601  * printed on the board.  The interrupt pins from the PCI slots are
 602  * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
 603  * ISA.
 604  *
 605  * In the table, -1 means don't assign an IRQ number.  This is usually
 606  * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 607  */
 608 static inline void cabriolet_fixup(void)
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 609 {
 610         char irq_tab[5][5] = {
 611                 { 16+2, 16+2, 16+7, 16+11, 16+15},      /* IdSel 5,  slot 2, J21 */
 612                 { 16+0, 16+0, 16+5,  16+9, 16+13},      /* IdSel 6,  slot 0, J19 */
 613                 { 16+1, 16+1, 16+6, 16+10, 16+14},      /* IdSel 7,  slot 1, J20 */
 614                 {   -1,   -1,   -1,    -1,    -1},      /* IdSel 8,  SIO         */
 615                 { 16+3, 16+3, 16+8, 16+12, 16+16}       /* IdSel 9,  slot 3, J22 */
 616         };
 617 
 618         common_fixup(5, 9, 5, irq_tab, 0x398);
 619 }
 620 
 621 
 622 /*
 623  * Fixup configuration for EB66/EB64+ boards.
 624  *
 625  * Both these boards use the same interrupt summary scheme.  There are
 626  * two 8 bit external summary registers as follows:
 627  *
 628  * Summary @ 0x26:
 629  * Bit      Meaning
 630  * 0        Interrupt Line A from slot 0
 631  * 1        Interrupt Line A from slot 1
 632  * 2        Interrupt Line B from slot 0
 633  * 3        Interrupt Line B from slot 1
 634  * 4        Interrupt Line C from slot 0
 635  * 5        Interrupt line from the two ISA PICs
 636  * 6        Tulip (slot 
 637  * 7        NCR SCSI
 638  *
 639  * Summary @ 0x27
 640  * Bit      Meaning
 641  * 0        Interrupt Line C from slot 1
 642  * 1        Interrupt Line D from slot 0
 643  * 2        Interrupt Line D from slot 1
 644  * 3        RAZ
 645  * 4        RAZ
 646  * 5        RAZ
 647  * 6        RAZ
 648  * 7        RAZ
 649  *
 650  * The device to slot mapping looks like:
 651  *
 652  * Slot     Device
 653  *  5       NCR SCSI controller
 654  *  6       PCI on board slot 0
 655  *  7       PCI on board slot 1
 656  *  8       Intel SIO PCI-ISA bridge chip
 657  *  9       Tulip - DECchip 21040 ethernet controller
 658  *   
 659  *
 660  * This two layered interrupt approach means that we allocate IRQ 16 and 
 661  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 662  * comes in on.  This makes interrupt processing much easier.
 663  */
 664 static inline void eb66_and_eb64p_fixup(void)
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 665 {
 666         char irq_tab[5][5] = {
 667                 {16+7, 16+7, 16+7, 16+7,  16+7},        /* IdSel 5,  slot ?, ?? */
 668                 {16+0, 16+0, 16+2, 16+4,  16+9},        /* IdSel 6,  slot ?, ?? */
 669                 {16+1, 16+1, 16+3, 16+8, 16+10},        /* IdSel 7,  slot ?, ?? */
 670                 {  -1,   -1,   -1,   -1,    -1},        /* IdSel 8,  SIO */
 671                 {16+6, 16+6, 16+6, 16+6,  16+6},        /* IdSel 9,  TULIP */
 672         };
 673         common_fixup(5, 9, 5, irq_tab, 0);
 674 }
 675 
 676 
 677 /*
 678  * Fixup configuration for all boards that route the PCI interrupts
 679  * through the SIO PCI/ISA bridge.  This includes Noname (AXPpci33),
 680  * Avanti (AlphaStation) and Kenetics's Platform 2000.
 681  */
 682 static inline void sio_fixup(void)
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 683 {
 684         struct pci_dev *dev;
 685         /*
 686          * The Noname board has 5 PCI slots with each of the 4
 687          * interrupt pins routed to different pins on the PCI/ISA
 688          * bridge (PIRQ0-PIRQ3).  The table below is based on
 689          * information available at:
 690          *
 691          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 692          *
 693          * I have no information on the Avanti interrupt routing, but
 694          * the routing seems to be identical to the Noname except
 695          * that the Avanti has an additional slot whose routing I'm
 696          * unsure of.
 697          *
 698          * pirq_tab[0] is a fake entry to deal with old PCI boards
 699          * that have the interrupt pin number hardwired to 0 (meaning
 700          * that they use the default INTA line, if they are interrupt
 701          * driven at all).
 702          */
 703         static const char pirq_tab[][5] = {
 704 #ifdef CONFIG_ALPHA_P2K
 705                 { 0,  0, -1, -1, -1}, /* idsel  6 (53c810) */
 706                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 707                 { 1,  1,  2,  3,  0}, /* idsel  8 (slot A) */
 708                 { 2,  2,  3,  0,  1}, /* idsel  9 (slot B) */
 709                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 710                 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
 711                 { 3,  3, -1, -1, -1}, /* idsel 12 (CMD0646) */
 712 #else
 713                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */ 
 714                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 715                 { 2,  2, -1, -1, -1}, /* idsel  8 (Noname hack: slot closest to ISA) */
 716                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 717                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 718                 { 0,  0,  2,  1,  0}, /* idsel 11 KN25_PCI_SLOT0 */
 719                 { 1,  1,  0,  2,  1}, /* idsel 12 KN25_PCI_SLOT1 */
 720                 { 2,  2,  1,  0,  2}, /* idsel 13 KN25_PCI_SLOT2 */
 721 #endif
 722         };
 723         /*
 724          * route_tab selects irq routing in PCI/ISA bridge so that:
 725          *              PIRQ0 -> irq 15
 726          *              PIRQ1 -> irq  9
 727          *              PIRQ2 -> irq 10
 728          *              PIRQ3 -> irq 11
 729          *
 730          * This probably ought to be configurable via MILO.  For
 731          * example, sound boards seem to like using IRQ 9.
 732          */
 733         const unsigned int route_tab = 0x0b0a090f;
 734         unsigned int level_bits;
 735         unsigned char pin;
 736         int pirq;
 737 
 738         pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
 739 
 740         /*
 741          * Go through all devices, fixing up irqs as we see fit:
 742          */
 743         level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
 744         for (dev = pci_devices; dev; dev = dev->next) {
 745                 dev->irq = 0;
 746                 if (dev->bus->number != 0) {
 747                         printk("bios32.sio_fixup: don't know how to fixup devices on bus %d\n",
 748                                dev->bus->number);
 749                         continue;
 750                 }
 751                 if (PCI_SLOT(dev->devfn) < 6 ||
 752                     PCI_SLOT(dev->devfn) >= 6 + sizeof(pirq_tab)/sizeof(pirq_tab[0]))
 753                 {
 754                         printk("bios32.sio_fixup: "
 755                                "weird, found device %04x:%04x in non-existent slot %d!!\n",
 756                                dev->vendor, dev->device, PCI_SLOT(dev->devfn));
 757                         continue;
 758                 }
 759                 pcibios_read_config_byte(dev->bus->number, dev->devfn,
 760                                          PCI_INTERRUPT_PIN, &pin);
 761                 pirq = pirq_tab[PCI_SLOT(dev->devfn) - 6][pin];
 762                 if (pirq < 0) {
 763                         continue;
 764                 }
 765 
 766                 /*
 767                  * if its a VGA, enable its BIOS ROM at C0000
 768                  */
 769                 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
 770                         pcibios_write_config_dword(dev->bus->number, dev->devfn,
 771                                                    PCI_ROM_ADDRESS,
 772                                                    0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
 773                 }
 774                 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
 775                         continue; /* for now, displays get no IRQ */
 776                 }
 777                 dev->irq = (route_tab >> (8 * pirq)) & 0xff;
 778 
 779                 /* must set the PCI IRQs to level triggered */
 780                 level_bits |= (1 << dev->irq);
 781 
 782 #if PCI_MODIFY
 783                 /* tell the device: */
 784                 pcibios_write_config_byte(dev->bus->number, dev->devfn,
 785                                           PCI_INTERRUPT_LINE, dev->irq);
 786 #endif
 787         }
 788         /*
 789          * Now, make all PCI interrupts level sensitive.  Notice:
 790          * these registers must be accessed byte-wise.  outw() doesn't
 791          * work.
 792          */
 793         outb((level_bits >> 0) & 0xff, 0x4d0);
 794         outb((level_bits >> 8) & 0xff, 0x4d1);
 795         enable_ide(0x26e);
 796 }
 797 
 798 
 799 #ifdef CONFIG_TGA_CONSOLE
 800 extern void tga_console_init(void);
 801 #endif /* CONFIG_TGA_CONSOLE */
 802 
 803 unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
     /* [previous][next][first][last][top][bottom][index][help] */
 804 {
 805 #if PCI_MODIFY
 806         /*
 807          * Scan the tree, allocating PCI memory and I/O space.
 808          */
 809         layout_bus(&pci_root);
 810 #endif
 811         
 812         /*
 813          * Now is the time to do all those dirty little deeds...
 814          */
 815 #if defined(CONFIG_ALPHA_NONAME) || defined(CONFIG_ALPHA_AVANTI) || defined(CONFIG_ALPHA_P2K)
 816         sio_fixup();
 817 #elif defined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB164)
 818         cabriolet_fixup();
 819 #elif defined(CONFIG_ALPHA_EB66P)
 820         eb66p_fixup();
 821 #elif defined(CONFIG_ALPHA_EB66)
 822         eb66_and_eb64p_fixup();
 823 #elif defined(CONFIG_ALPHA_EB64P)
 824         eb66_and_eb64p_fixup();
 825 #else
 826 #       error You must tell me what kind of platform you want.
 827 #endif
 828 
 829 #ifdef CONFIG_TGA_CONSOLE
 830         tga_console_init();
 831 #endif /* CONFIG_TGA_CONSOLE */
 832 
 833         return mem_start;
 834 }
 835 
 836 
 837 const char *pcibios_strerror (int error)
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 838 {
 839         static char buf[80];
 840 
 841         switch (error) {
 842                 case PCIBIOS_SUCCESSFUL:
 843                         return "SUCCESSFUL";
 844 
 845                 case PCIBIOS_FUNC_NOT_SUPPORTED:
 846                         return "FUNC_NOT_SUPPORTED";
 847 
 848                 case PCIBIOS_BAD_VENDOR_ID:
 849                         return "SUCCESSFUL";
 850 
 851                 case PCIBIOS_DEVICE_NOT_FOUND:
 852                         return "DEVICE_NOT_FOUND";
 853 
 854                 case PCIBIOS_BAD_REGISTER_NUMBER:
 855                         return "BAD_REGISTER_NUMBER";
 856 
 857                 default:
 858                         sprintf (buf, "UNKNOWN RETURN 0x%x", error);
 859                         return buf;
 860         }
 861 }
 862 
 863 #endif /* CONFIG_PCI */

/* [previous][next][first][last][top][bottom][index][help] */