root/include/asm-mips/dma.h

/* [previous][next][first][last][top][bottom][index][help] */

INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. enable_dma
  2. disable_dma
  3. clear_dma_ff
  4. set_dma_mode
  5. set_dma_page
  6. set_dma_addr
  7. set_dma_count
  8. get_dma_residue

   1 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
   2  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3  * Written by Hennus Bergman, 1992.
   4  * High DMA channel support & info by Hannu Savolainen
   5  * and John Boyd, Nov. 1992.
   6  *
   7  * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
   8  * and can only be used for expansion cards. Onboard DMA controller, such
   9  * as the R4030 on Jazz boards behave totally different!
  10  */
  11 
  12 #ifndef __ASM_MIPS_DMA_H
  13 #define __ASM_MIPS_DMA_H
  14 
  15 #include <asm/io.h>             /* need byte IO */
  16 
  17 
  18 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  19 #define dma_outb        outb_p
  20 #else
  21 #define dma_outb        outb
  22 #endif
  23 
  24 #define dma_inb         inb
  25 
  26 /*
  27  * NOTES about DMA transfers:
  28  *
  29  *  controller 1: channels 0-3, byte operations, ports 00-1F
  30  *  controller 2: channels 4-7, word operations, ports C0-DF
  31  *
  32  *  - ALL registers are 8 bits only, regardless of transfer size
  33  *  - channel 4 is not used - cascades 1 into 2.
  34  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  35  *  - channels 5-7 are word - addresses/counts are for physical words
  36  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  37  *  - transfer count loaded to registers is 1 less than actual count
  38  *  - controller 2 offsets are all even (2x offsets for controller 1)
  39  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  40  *  - page registers for 0-3 use bit 0, represent 64K pages
  41  *
  42  * DMA transfers are limited to the lower 16MB of _physical_ memory.  
  43  * Note that addresses loaded into registers must be _physical_ addresses,
  44  * not logical addresses (which may differ if paging is active).
  45  *
  46  *  Address mapping for channels 0-3:
  47  *
  48  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  49  *    |  ...  |   |  ... |   |  ... |
  50  *    |  ...  |   |  ... |   |  ... |
  51  *    |  ...  |   |  ... |   |  ... |
  52  *   P7  ...  P0  A7 ... A0  A7 ... A0   
  53  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  54  *
  55  *  Address mapping for channels 5-7:
  56  *
  57  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  58  *    |  ...  |   \   \   ... \  \  \  ... \  \
  59  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  60  *    |  ...  |     \   \   ... \  \  \  ... \
  61  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
  62  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  63  *
  64  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  65  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  66  * the hardware level, so odd-byte transfers aren't possible).
  67  *
  68  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  69  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  70  * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
  71  *
  72  */
  73 
  74 #define MAX_DMA_CHANNELS        8
  75 
  76 /*
  77  * The maximum address that we can perform a DMA transfer to on this platform
  78  * This describes only the PC style part of the DMA logic like on Deskstations
  79  * or Acer PICA but not the much more versatile DMA logic used for the
  80  * local devices on Acer PICA or Magnums.
  81  */
  82 #define MAX_DMA_ADDRESS         0x1000000
  83 
  84 /* 8237 DMA controllers */
  85 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
  86 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
  87 
  88 /* DMA controller registers */
  89 #define DMA1_CMD_REG            0x08    /* command register (w) */
  90 #define DMA1_STAT_REG           0x08    /* status register (r) */
  91 #define DMA1_REQ_REG            0x09    /* request register (w) */
  92 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
  93 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
  94 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
  95 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
  96 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
  97 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
  98 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
  99 
 100 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 101 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 102 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 103 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 104 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 105 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 106 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 107 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 108 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 109 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 110 
 111 #define DMA_ADDR_0              0x00    /* DMA address registers */
 112 #define DMA_ADDR_1              0x02
 113 #define DMA_ADDR_2              0x04
 114 #define DMA_ADDR_3              0x06
 115 #define DMA_ADDR_4              0xC0
 116 #define DMA_ADDR_5              0xC4
 117 #define DMA_ADDR_6              0xC8
 118 #define DMA_ADDR_7              0xCC
 119 
 120 #define DMA_CNT_0               0x01    /* DMA count registers */
 121 #define DMA_CNT_1               0x03
 122 #define DMA_CNT_2               0x05
 123 #define DMA_CNT_3               0x07
 124 #define DMA_CNT_4               0xC2
 125 #define DMA_CNT_5               0xC6
 126 #define DMA_CNT_6               0xCA
 127 #define DMA_CNT_7               0xCE
 128 
 129 #define DMA_PAGE_0              0x87    /* DMA page registers */
 130 #define DMA_PAGE_1              0x83
 131 #define DMA_PAGE_2              0x81
 132 #define DMA_PAGE_3              0x82
 133 #define DMA_PAGE_5              0x8B
 134 #define DMA_PAGE_6              0x89
 135 #define DMA_PAGE_7              0x8A
 136 
 137 #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 138 #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 139 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 140 
 141 /* enable/disable a specific DMA channel */
 142 static __inline__ void enable_dma(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 143 {
 144         if (dmanr<=3)
 145                 dma_outb(dmanr,  DMA1_MASK_REG);
 146         else
 147                 dma_outb(dmanr & 3,  DMA2_MASK_REG);
 148 }
 149 
 150 static __inline__ void disable_dma(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 151 {
 152         if (dmanr<=3)
 153                 dma_outb(dmanr | 4,  DMA1_MASK_REG);
 154         else
 155                 dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 156 }
 157 
 158 /* Clear the 'DMA Pointer Flip Flop'.
 159  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 160  * Use this once to initialize the FF to a known state.
 161  * After that, keep track of it. :-)
 162  * --- In order to do that, the DMA routines below should ---
 163  * --- only be used while interrupts are disabled! ---
 164  */
 165 static __inline__ void clear_dma_ff(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 166 {
 167         if (dmanr<=3)
 168                 dma_outb(0,  DMA1_CLEAR_FF_REG);
 169         else
 170                 dma_outb(0,  DMA2_CLEAR_FF_REG);
 171 }
 172 
 173 /* set mode (above) for a specific DMA channel */
 174 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
     /* [previous][next][first][last][top][bottom][index][help] */
 175 {
 176         if (dmanr<=3)
 177                 dma_outb(mode | dmanr,  DMA1_MODE_REG);
 178         else
 179                 dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 180 }
 181 
 182 /* Set only the page register bits of the transfer address.
 183  * This is used for successive transfers when we know the contents of
 184  * the lower 16 bits of the DMA current address register, but a 64k boundary
 185  * may have been crossed.
 186  */
 187 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
     /* [previous][next][first][last][top][bottom][index][help] */
 188 {
 189         switch(dmanr) {
 190                 case 0:
 191                         dma_outb(pagenr, DMA_PAGE_0);
 192                         break;
 193                 case 1:
 194                         dma_outb(pagenr, DMA_PAGE_1);
 195                         break;
 196                 case 2:
 197                         dma_outb(pagenr, DMA_PAGE_2);
 198                         break;
 199                 case 3:
 200                         dma_outb(pagenr, DMA_PAGE_3);
 201                         break;
 202                 case 5:
 203                         dma_outb(pagenr & 0xfe, DMA_PAGE_5);
 204                         break;
 205                 case 6:
 206                         dma_outb(pagenr & 0xfe, DMA_PAGE_6);
 207                         break;
 208                 case 7:
 209                         dma_outb(pagenr & 0xfe, DMA_PAGE_7);
 210                         break;
 211         }
 212 }
 213 
 214 
 215 /* Set transfer address & page bits for specific DMA channel.
 216  * Assumes dma flipflop is clear.
 217  */
 218 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
     /* [previous][next][first][last][top][bottom][index][help] */
 219 {
 220         set_dma_page(dmanr, a>>16);
 221         if (dmanr <= 3)  {
 222             dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 223             dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 224         }  else  {
 225             dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 226             dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 227         }
 228 }
 229 
 230 
 231 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 232  * a specific DMA channel.
 233  * You must ensure the parameters are valid.
 234  * NOTE: from a manual: "the number of transfers is one more
 235  * than the initial word count"! This is taken into account.
 236  * Assumes dma flip-flop is clear.
 237  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 238  */
 239 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
     /* [previous][next][first][last][top][bottom][index][help] */
 240 {
 241         count--;
 242         if (dmanr <= 3)  {
 243             dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 244             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 245         } else {
 246             dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 247             dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 248         }
 249 }
 250 
 251 
 252 /* Get DMA residue count. After a DMA transfer, this
 253  * should return zero. Reading this while a DMA transfer is
 254  * still in progress will return unpredictable results.
 255  * If called before the channel has been used, it may return 1.
 256  * Otherwise, it returns the number of _bytes_ left to transfer.
 257  *
 258  * Assumes DMA flip-flop is clear.
 259  */
 260 static __inline__ int get_dma_residue(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 261 {
 262         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 263                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 264 
 265         /* using short to get 16-bit wrap around */
 266         unsigned short count;
 267 
 268         count = 1 + dma_inb(io_port);
 269         count += dma_inb(io_port) << 8;
 270         
 271         return (dmanr<=3)? count : (count<<1);
 272 }
 273 
 274 
 275 /* These are in kernel/dma.c: */
 276 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 277 extern void free_dma(unsigned int dmanr);       /* release it again */
 278 
 279 /*
 280  * DMA memory allocation - formerly in include/linux/mm.h
 281  */
 282 #define __get_dma_pages(priority, order) __get_free_pages((priority),(order), 1)
 283 
 284 #endif /* __ASM_MIPS_DMA_H */

/* [previous][next][first][last][top][bottom][index][help] */