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*/
1 /*
2 * bios32.c - PCI BIOS functions for Alpha systems not using BIOS
3 * emulation code.
4 *
5 * Written by Dave Rusling (david.rusling@reo.mts.dec.com)
6 *
7 * Adapted to 64-bit kernel and then rewritten by David Mosberger
8 * (davidm@cs.arizona.edu)
9 *
10 * For more information, please consult
11 *
12 * PCI BIOS Specification Revision
13 * PCI Local Bus Specification
14 * PCI System Design Guide
15 *
16 * PCI Special Interest Group
17 * M/S HF3-15A
18 * 5200 N.E. Elam Young Parkway
19 * Hillsboro, Oregon 97124-6497
20 * +1 (503) 696-2000
21 * +1 (800) 433-5177
22 *
23 * Manuals are $25 each or $50 for all three, plus $7 shipping
24 * within the United States, $35 abroad.
25 */
26 #include <linux/config.h>
27
28 #if 0
29 #define DEBUG_PRINT_DEVS 1
30 #endif
31
32 #ifndef CONFIG_PCI
33
34 int pcibios_present(void)
/* ![[next]](../icons/right.png)
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*/
35 {
36 return 0;
37 }
38
39 #else /* CONFIG_PCI */
40
41 #include <linux/kernel.h>
42 #include <linux/bios32.h>
43 #include <linux/pci.h>
44 #include <linux/malloc.h>
45 #include <linux/mm.h>
46
47 #include <asm/hwrpb.h>
48 #include <asm/io.h>
49
50
51 #define KB 1024
52 #define MB (1024*KB)
53 #define GB (1024*MB)
54
55 #define MAJOR_REV 0
56 #define MINOR_REV 3
57
58 /*
59 * Align VAL to ALIGN, which must be a power of two.
60 */
61 #define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
62
63
64 /*
65 * Temporary internal macro. If this 0, then do not write to any of
66 * the PCI registers, merely read them (i.e., use configuration as
67 * determined by SRM). The SRM seem do be doing a less than perfect
68 * job in configuring PCI devices, so for now we do it ourselves.
69 * Reconfiguring PCI devices breaks console (RPB) callbacks, but
70 * those don't work properly with 64 bit addresses anyways.
71 *
72 * The accepted convention seems to be that the console (POST
73 * software) should fully configure boot devices and configure the
74 * interrupt routing of *all* devices. In particular, the base
75 * addresses of non-boot devices need not be initialized. For
76 * example, on the AXPpci33 board, the base address a #9 GXE PCI
77 * graphics card reads as zero (this may, however, be due to a bug in
78 * the graphics card---there have been some rumor that the #9 BIOS
79 * incorrectly resets that address to 0...).
80 */
81 #define PCI_MODIFY 1
82
83 extern struct hwrpb_struct *hwrpb;
84
85
86 #if PCI_MODIFY
87
88 #if 0
89 static unsigned int io_base = 64*KB; /* <64KB are (E)ISA ports */
90 #else
91 static unsigned int io_base = 0xb000;
92 #endif
93
94 #if defined(CONFIG_ALPHA_XL)
95 /*
96 an AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
97 that get passed through the PCI<->ISA bridge chip. Because this causes
98 us to set the PCI->Mem window bases lower than normal, we've gotta allocate
99 PCI bus devices' memory addresses *above* the PCI<->memory mapping windows,
100 so that CPU memory DMA addresses issued by a bus device don't conflict
101 with bus memory addresses, like frame buffer memory for graphics cards.
102 */
103 static unsigned int mem_base = 1024*MB;
104 #else /* CONFIG_ALPHA_XL */
105 static unsigned int mem_base = 16*MB; /* <16MB is ISA memory */
106 #endif /* CONFIG_ALPHA_XL */
107
108 /*
109 * Disable PCI device DEV so that it does not respond to I/O or memory
110 * accesses.
111 */
112 static void disable_dev(struct pci_dev *dev)
/* ![[previous]](../icons/left.png)
*/
113 {
114 struct pci_bus *bus;
115 unsigned short cmd;
116
117 bus = dev->bus;
118 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
119
120 /* hack, turn it off first... */
121 cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
122 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND, cmd);
123 }
124
125
126 /*
127 * Layout memory and I/O for a device:
128 */
129 #define MAX(val1, val2) ( ((val1) > (val2)) ? val1 : val2)
130
131 static void layout_dev(struct pci_dev *dev)
/* */
132 {
133 struct pci_bus *bus;
134 unsigned short cmd;
135 unsigned int base, mask, size, reg;
136 unsigned int alignto;
137
138 bus = dev->bus;
139 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
140
141 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
142 /*
143 * Figure out how much space and of what type this
144 * device wants.
145 */
146 pcibios_write_config_dword(bus->number, dev->devfn, reg,
147 0xffffffff);
148 pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
149 if (!base) {
150 /* this base-address register is unused */
151 continue;
152 }
153
154 /*
155 * We've read the base address register back after
156 * writing all ones and so now we must decode it.
157 */
158 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
159 /*
160 * I/O space base address register.
161 */
162 cmd |= PCI_COMMAND_IO;
163
164 base &= PCI_BASE_ADDRESS_IO_MASK;
165 mask = (~base << 1) | 0x1;
166 size = (mask & base) & 0xffffffff;
167 /* align to multiple of size of minimum base */
168 alignto = MAX(0x400, size) ;
169 base = ALIGN(io_base, alignto );
170 io_base = base + size;
171 pcibios_write_config_dword(bus->number, dev->devfn,
172 reg, base | 0x1);
173 } else {
174 unsigned int type;
175 /*
176 * Memory space base address register.
177 */
178 cmd |= PCI_COMMAND_MEMORY;
179 type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
180 base &= PCI_BASE_ADDRESS_MEM_MASK;
181 mask = (~base << 1) | 0x1;
182 size = (mask & base) & 0xffffffff;
183 switch (type) {
184 case PCI_BASE_ADDRESS_MEM_TYPE_32:
185 break;
186
187 case PCI_BASE_ADDRESS_MEM_TYPE_64:
188 printk("bios32 WARNING: "
189 "ignoring 64-bit device in "
190 "slot %d, function %d: \n",
191 PCI_SLOT(dev->devfn),
192 PCI_FUNC(dev->devfn));
193 reg += 4; /* skip extra 4 bytes */
194 continue;
195
196 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
197 /*
198 * Allocating memory below 1MB is *very*
199 * tricky, as there may be all kinds of
200 * ISA devices lurking that we don't know
201 * about. For now, we just cross fingers
202 * and hope nobody tries to do this on an
203 * Alpha (or that the console has set it
204 * up properly).
205 */
206 printk("bios32 WARNING: slot %d, function %d "
207 "requests memory below 1MB---don't "
208 "know how to do that.\n",
209 PCI_SLOT(dev->devfn),
210 PCI_FUNC(dev->devfn));
211 continue;
212 }
213 /*
214 * The following holds at least for the Low Cost
215 * Alpha implementation of the PCI interface:
216 *
217 * In sparse memory address space, the first
218 * octant (16MB) of every 128MB segment is
219 * aliased to the the very first 16MB of the
220 * address space (i.e., it aliases the ISA
221 * memory address space). Thus, we try to
222 * avoid allocating PCI devices in that range.
223 * Can be allocated in 2nd-7th octant only.
224 * Devices that need more than 112MB of
225 * address space must be accessed through
226 * dense memory space only!
227 */
228 /* align to multiple of size of minimum base */
229 alignto = MAX(0x1000, size) ;
230 base = ALIGN(mem_base, alignto);
231 if (size > 7 * 16*MB) {
232 printk("bios32 WARNING: slot %d, function %d "
233 "requests %dB of contiguous address "
234 " space---don't use sparse memory "
235 " accesses on this device!!\n",
236 PCI_SLOT(dev->devfn),
237 PCI_FUNC(dev->devfn), size);
238 } else {
239 if (((base / (16*MB)) & 0x7) == 0) {
240 base &= ~(128*MB - 1);
241 base += 16*MB;
242 base = ALIGN(base, alignto);
243 }
244 if (base / (128*MB) != (base + size) / (128*MB)) {
245 base &= ~(128*MB - 1);
246 base += (128 + 16)*MB;
247 base = ALIGN(base, alignto);
248 }
249 }
250 mem_base = base + size;
251 pcibios_write_config_dword(bus->number, dev->devfn,
252 reg, base);
253 }
254 }
255 /* enable device: */
256 if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
257 dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
258 dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
259 dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
260 {
261 /*
262 * All of these (may) have I/O scattered all around
263 * and may not use i/o-base address registers at all.
264 * So we just have to always enable I/O to these
265 * devices.
266 */
267 cmd |= PCI_COMMAND_IO;
268 }
269
270 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
271 cmd | PCI_COMMAND_MASTER);
272 #if DEBUG_PRINT_DEVS
273 printk("layout_dev: bus %d slot 0x%x VID 0x%x DID 0x%x class 0x%x\n",
274 bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device, dev->class);
275 #endif
276 }
277
278
279 static void layout_bus(struct pci_bus *bus)
/* */
280 {
281 unsigned int l, tio, bio, tmem, bmem;
282 struct pci_bus *child;
283 struct pci_dev *dev;
284
285 #if DEBUG_PRINT_DEVS
286 printk("layout_bus: starting bus %d\n", bus->number);
287 #endif
288
289 if (!bus->devices && !bus->children)
290 return;
291
292 /*
293 * Align the current bases on appropriate boundaries (4K for
294 * IO and 1MB for memory).
295 */
296 bio = io_base = ALIGN(io_base, 4*KB);
297 bmem = mem_base = ALIGN(mem_base, 1*MB);
298
299 /*
300 * There are times when the PCI devices have already been
301 * setup (e.g., by MILO or SRM). In these cases there is a
302 * window during which two devices may have an overlapping
303 * address range. To avoid this causing trouble, we first
304 * turn off the I/O and memory address decoders for all PCI
305 * devices. They'll be re-enabled only once all address
306 * decoders are programmed consistently.
307 */
308 for (dev = bus->devices; dev; dev = dev->sibling) {
309 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
310 disable_dev(dev) ;
311 }
312 }
313
314 /*
315 * Allocate space to each device:
316 */
317 #if DEBUG_PRINT_DEVS
318 printk("layout_bus: starting bus %d devices\n", bus->number);
319 #endif
320
321 for (dev = bus->devices; dev; dev = dev->sibling) {
322 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
323 layout_dev(dev);
324 }
325 }
326 /*
327 * Recursively allocate space for all of the sub-buses:
328 */
329 #if DEBUG_PRINT_DEVS
330 printk("layout_bus: starting bus %d children\n", bus->number);
331 #endif
332
333 for (child = bus->children; child; child = child->next) {
334 layout_bus(child);
335 }
336 /*
337 * Align the current bases on 4K and 1MB boundaries:
338 */
339 tio = io_base = ALIGN(io_base, 4*KB);
340 tmem = mem_base = ALIGN(mem_base, 1*MB);
341
342 if (bus->self) {
343 struct pci_dev *bridge = bus->self;
344 /*
345 * Set up the top and bottom of the PCI I/O segment
346 * for this bus.
347 */
348 pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
349 0x1c, &l);
350 l = (l & 0xffff0000) | (bio >> 8) | ((tio - 1) & 0xf000);
351 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
352 0x1c, l);
353 /*
354 * Set up the top and bottom of the PCI Memory segment
355 * for this bus.
356 */
357 l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
358 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
359 0x20, l);
360 /*
361 * Turn off downstream PF memory address range:
362 */
363 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
364 0x24, 0x0000ffff);
365 /*
366 * Tell bridge that there is an ISA bus in the system:
367 */
368 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
369 0x3c, 0x00040000);
370 /*
371 * Clear status bits, enable I/O (for downstream I/O),
372 * turn on master enable (for upstream I/O), turn on
373 * memory enable (for downstream memory), turn on
374 * master enable (for upstream memory and I/O).
375 */
376 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
377 0x4, 0xffff0007);
378 }
379 }
380
381 #endif /* !PCI_MODIFY */
382
383
384 /*
385 * Given the vendor and device ids, find the n'th instance of that device
386 * in the system.
387 */
388 int pcibios_find_device (unsigned short vendor, unsigned short device_id,
/* */
389 unsigned short index, unsigned char *bus,
390 unsigned char *devfn)
391 {
392 unsigned int curr = 0;
393 struct pci_dev *dev;
394
395 for (dev = pci_devices; dev; dev = dev->next) {
396 if (dev->vendor == vendor && dev->device == device_id) {
397 if (curr == index) {
398 *devfn = dev->devfn;
399 *bus = dev->bus->number;
400 return PCIBIOS_SUCCESSFUL;
401 }
402 ++curr;
403 }
404 }
405 return PCIBIOS_DEVICE_NOT_FOUND;
406 }
407
408
409 /*
410 * Given the class, find the n'th instance of that device
411 * in the system.
412 */
413 int pcibios_find_class (unsigned int class_code, unsigned short index,
/* */
414 unsigned char *bus, unsigned char *devfn)
415 {
416 unsigned int curr = 0;
417 struct pci_dev *dev;
418
419 for (dev = pci_devices; dev; dev = dev->next) {
420 if (dev->class == class_code) {
421 if (curr == index) {
422 *devfn = dev->devfn;
423 *bus = dev->bus->number;
424 return PCIBIOS_SUCCESSFUL;
425 }
426 ++curr;
427 }
428 }
429 return PCIBIOS_DEVICE_NOT_FOUND;
430 }
431
432
433 int pcibios_present(void)
/* */
434 {
435 return 1;
436 }
437
438
439 unsigned long pcibios_init(unsigned long mem_start,
/* */
440 unsigned long mem_end)
441 {
442 printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
443
444 #if !PCI_MODIFY
445 printk("...NOT modifying existing (SRM) PCI configuration\n");
446 #endif
447 return mem_start;
448 }
449
450 /*
451 * The SRM console *disables* the IDE interface, this code ensures its
452 * enabled.
453 *
454 * This code bangs on a control register of the 87312 Super I/O chip
455 * that implements parallel port/serial ports/IDE/FDI. Depending on
456 * the motherboard, the Super I/O chip can be configured through a
457 * pair of registers that are located either at I/O ports 0x26e/0x26f
458 * or 0x398/0x399. Unfortunately, autodetecting which base address is
459 * in use works only once (right after a reset). The Super I/O chip
460 * has the additional quirk that configuration register data must be
461 * written twice (I believe this is a safety feature to prevent
462 * accidental modification---fun, isn't it?).
463 */
464 static inline void enable_ide(long ide_base)
/* */
465 {
466 int data;
467
468 outb(0, ide_base); /* set the index register for reg #0 */
469 data = inb(ide_base+1); /* read the current contents */
470 outb(0, ide_base); /* set the index register for reg #0 */
471 outb(data | 0x40, ide_base+1); /* turn on IDE */
472 outb(data | 0x40, ide_base+1); /* turn on IDE, really! */
473 }
474
475 /*
476 * A small note about bridges and interrupts. The DECchip 21050 (and later chips)
477 * adheres to the PCI-PCI bridge specification. This says that the interrupts on
478 * the other side of a bridge are swizzled in the following manner:
479 *
480 * Dev Interrupt Interrupt
481 * Pin on Pin on
482 * Device Connector
483 *
484 * 4 A A
485 * B B
486 * C C
487 * D D
488 *
489 * 5 A B
490 * B C
491 * C D
492 * D A
493 *
494 * 6 A C
495 * B D
496 * C A
497 * D B
498 *
499 * 7 A D
500 * B A
501 * C B
502 * D C
503 *
504 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
505 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
506 *
507 * The following code is somewhat simplistic as it assumes only one bridge.
508 * I will fix it later (david.rusling@reo.mts.dec.com).
509 */
510 static inline unsigned char bridge_swizzle(unsigned char pin, unsigned int slot)
/* */
511 {
512 /* swizzle */
513 return (((pin-1) + slot) % 4) + 1 ;
514 }
515
516 /*
517 * Most evaluation boards share most of the fixup code, which is isolated here.
518 * This function is declared "inline" as only one platform will ever be selected
519 * in any given kernel. If that platform doesn't need this code, we don't want
520 * it around as dead code.
521 */
522 static inline void common_fixup(long min_idsel, long max_idsel, long irqs_per_slot,
/* */
523 char irq_tab[max_idsel - min_idsel + 1][irqs_per_slot],
524 long ide_base)
525 {
526 struct pci_dev *dev;
527 unsigned char pin;
528 unsigned char slot ;
529
530 /*
531 * Go through all devices, fixing up irqs as we see fit:
532 */
533 for (dev = pci_devices; dev; dev = dev->next) {
534 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
535 dev->irq = 0;
536 /*
537 * This device is not on the primary bus, we need to figure out which
538 * interrupt pin it will come in on. We know which slot it will come
539 * in on 'cos that slot is where the bridge is. Each time the interrupt
540 * line passes through a PCI-PCI bridge we must apply the swizzle function
541 * (see the inline static routine above).
542 */
543 if (dev->bus->number != 0) {
544 struct pci_dev *curr = dev ;
545 /* read the pin and do the PCI-PCI bridge interrupt pin swizzle */
546 pcibios_read_config_byte(dev->bus->number, dev->devfn,
547 PCI_INTERRUPT_PIN, &pin);
548 /* cope with 0 */
549 if (pin == 0) pin = 1 ;
550 /* follow the chain of bridges, swizzling as we go */
551 do {
552 /* swizzle */
553 pin = bridge_swizzle(pin, PCI_SLOT(curr->devfn)) ;
554 /* move up the chain of bridges */
555 curr = curr->bus->self ;
556 } while (curr->bus->self) ;
557 /* The slot is the slot of the last bridge. */
558 slot = PCI_SLOT(curr->devfn) ;
559 } else {
560 /* work out the slot */
561 slot = PCI_SLOT(dev->devfn) ;
562 /* read the pin */
563 pcibios_read_config_byte(dev->bus->number, dev->devfn,
564 PCI_INTERRUPT_PIN, &pin);
565 }
566 if (irq_tab[slot - min_idsel][pin] != -1)
567 dev->irq = irq_tab[slot - min_idsel][pin];
568 #if PCI_MODIFY
569 /* tell the device: */
570 pcibios_write_config_byte(dev->bus->number, dev->devfn,
571 PCI_INTERRUPT_LINE, dev->irq);
572 #endif
573 /*
574 * if its a VGA, enable its BIOS ROM at C0000
575 */
576 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
577 pcibios_write_config_dword(dev->bus->number, dev->devfn,
578 PCI_ROM_ADDRESS,
579 0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
580 }
581 }
582
583 }
584 if (ide_base) {
585 enable_ide(ide_base);
586 }
587 }
588
589 /*
590 * The EB66+ is very similar to the EB66 except that it does not have
591 * the on-board NCR and Tulip chips. In the code below, I have used
592 * slot number to refer to the id select line and *not* the slot
593 * number used in the EB66+ documentation. However, in the table,
594 * I've given the slot number, the id select line and the Jxx number
595 * that's printed on the board. The interrupt pins from the PCI slots
596 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
597 * 0x806 ISA.
598 *
599 * In the table, -1 means don't assign an IRQ number. This is usually
600 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
601 */
602 static inline void eb66p_fixup(void)
/* */
603 {
604 char irq_tab[5][5] = {
605 {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
606 {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
607 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
608 {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
609 {16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
610 };
611 common_fixup(6, 10, 5, irq_tab, 0x398);
612 }
613
614
615 /*
616 * The AlphaPC64 is very similar to the EB66+ except that its slots
617 * are numbered differently. In the code below, I have used slot
618 * number to refer to the id select line and *not* the slot number
619 * used in the AlphaPC64 documentation. However, in the table, I've
620 * given the slot number, the id select line and the Jxx number that's
621 * printed on the board. The interrupt pins from the PCI slots are
622 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
623 * ISA.
624 *
625 * In the table, -1 means don't assign an IRQ number. This is usually
626 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
627 */
628 static inline void cabriolet_fixup(void)
/* */
629 {
630 char irq_tab[5][5] = {
631 { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
632 { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
633 { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
634 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
635 { 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
636 };
637
638 common_fixup(5, 9, 5, irq_tab, 0x398);
639 }
640
641
642 /*
643 * Fixup configuration for EB66/EB64+ boards.
644 *
645 * Both these boards use the same interrupt summary scheme. There are
646 * two 8 bit external summary registers as follows:
647 *
648 * Summary @ 0x26:
649 * Bit Meaning
650 * 0 Interrupt Line A from slot 0
651 * 1 Interrupt Line A from slot 1
652 * 2 Interrupt Line B from slot 0
653 * 3 Interrupt Line B from slot 1
654 * 4 Interrupt Line C from slot 0
655 * 5 Interrupt line from the two ISA PICs
656 * 6 Tulip (slot
657 * 7 NCR SCSI
658 *
659 * Summary @ 0x27
660 * Bit Meaning
661 * 0 Interrupt Line C from slot 1
662 * 1 Interrupt Line D from slot 0
663 * 2 Interrupt Line D from slot 1
664 * 3 RAZ
665 * 4 RAZ
666 * 5 RAZ
667 * 6 RAZ
668 * 7 RAZ
669 *
670 * The device to slot mapping looks like:
671 *
672 * Slot Device
673 * 5 NCR SCSI controller
674 * 6 PCI on board slot 0
675 * 7 PCI on board slot 1
676 * 8 Intel SIO PCI-ISA bridge chip
677 * 9 Tulip - DECchip 21040 ethernet controller
678 *
679 *
680 * This two layered interrupt approach means that we allocate IRQ 16 and
681 * above for PCI interrupts. The IRQ relates to which bit the interrupt
682 * comes in on. This makes interrupt processing much easier.
683 */
684 static inline void eb66_and_eb64p_fixup(void)
/* */
685 {
686 char irq_tab[5][5] = {
687 {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */
688 {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */
689 {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */
690 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
691 {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */
692 };
693 common_fixup(5, 9, 5, irq_tab, 0);
694 }
695
696
697 /*
698 * Fixup configuration for all boards that route the PCI interrupts
699 * through the SIO PCI/ISA bridge. This includes Noname (AXPpci33),
700 * Avanti (AlphaStation) and Kenetics's Platform 2000.
701 */
702 static inline void sio_fixup(void)
/* */
703 {
704 struct pci_dev *dev;
705 /*
706 * The Noname board has 5 PCI slots with each of the 4
707 * interrupt pins routed to different pins on the PCI/ISA
708 * bridge (PIRQ0-PIRQ3). The table below is based on
709 * information available at:
710 *
711 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
712 *
713 * I have no information on the Avanti interrupt routing, but
714 * the routing seems to be identical to the Noname except
715 * that the Avanti has an additional slot whose routing I'm
716 * unsure of.
717 *
718 * pirq_tab[0] is a fake entry to deal with old PCI boards
719 * that have the interrupt pin number hardwired to 0 (meaning
720 * that they use the default INTA line, if they are interrupt
721 * driven at all).
722 */
723 static const char pirq_tab[][5] = {
724 #ifdef CONFIG_ALPHA_P2K
725 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
726 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
727 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
728 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
729 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
730 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
731 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
732 #else
733 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
734 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
735 { 2, 2, -1, -1, -1}, /* idsel 8 (Noname hack: slot closest to ISA) */
736 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
737 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
738 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
739 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
740 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
741 #endif
742 };
743 /*
744 * route_tab selects irq routing in PCI/ISA bridge so that:
745 * PIRQ0 -> irq 15
746 * PIRQ1 -> irq 9
747 * PIRQ2 -> irq 10
748 * PIRQ3 -> irq 11
749 *
750 * This probably ought to be configurable via MILO. For
751 * example, sound boards seem to like using IRQ 9.
752 */
753 const unsigned int route_tab = 0x0b0a090f;
754 unsigned int level_bits;
755 unsigned char pin, slot;
756 int pirq;
757
758 pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
759
760 /*
761 * Go through all devices, fixing up irqs as we see fit:
762 */
763 level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
764 for (dev = pci_devices; dev; dev = dev->next) {
765 if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE)
766 continue;
767 dev->irq = 0;
768 if (dev->bus->number != 0) {
769 struct pci_dev *curr = dev ;
770 /* read the pin and do the PCI-PCI bridge
771 interrupt pin swizzle */
772 pcibios_read_config_byte(dev->bus->number, dev->devfn,
773 PCI_INTERRUPT_PIN, &pin);
774 /* cope with 0 */
775 if (pin == 0) pin = 1 ;
776 /* follow the chain of bridges, swizzling as we go */
777 do {
778 /* swizzle */
779 pin = bridge_swizzle(pin, PCI_SLOT(curr->devfn)) ;
780 /* move up the chain of bridges */
781 curr = curr->bus->self ;
782 } while (curr->bus->self) ;
783 /* The slot is the slot of the last bridge. */
784 slot = PCI_SLOT(curr->devfn) ;
785 } else {
786 /* work out the slot */
787 slot = PCI_SLOT(dev->devfn) ;
788 /* read the pin */
789 pcibios_read_config_byte(dev->bus->number, dev->devfn,
790 PCI_INTERRUPT_PIN, &pin);
791 }
792
793 pirq = pirq_tab[slot - 6][pin];
794
795 #if DEBUG_PRINT_DEVS
796 printk("sio_fixup: bus %d slot 0x%x VID 0x%x DID 0x%x int_slot 0x%x int_pin 0x%x, pirq 0x%x\n",
797 dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device, slot, pin, pirq);
798 #endif
799
800 if (pirq < 0) {
801 continue;
802 }
803
804 /*
805 * if its a VGA, enable its BIOS ROM at C0000
806 */
807 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
808 pcibios_write_config_dword(dev->bus->number, dev->devfn,
809 PCI_ROM_ADDRESS,
810 0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
811 }
812 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
813 continue; /* for now, displays get no IRQ */
814 }
815 dev->irq = (route_tab >> (8 * pirq)) & 0xff;
816
817 /* must set the PCI IRQs to level triggered */
818 level_bits |= (1 << dev->irq);
819
820 #if PCI_MODIFY
821 /* tell the device: */
822 pcibios_write_config_byte(dev->bus->number, dev->devfn,
823 PCI_INTERRUPT_LINE, dev->irq);
824 #endif
825 }
826 /*
827 * Now, make all PCI interrupts level sensitive. Notice:
828 * these registers must be accessed byte-wise. outw() doesn't
829 * work.
830 */
831 level_bits |= (inb(0x4d0) | (inb(0x4d1) << 8));
832 outb((level_bits >> 0) & 0xff, 0x4d0);
833 outb((level_bits >> 8) & 0xff, 0x4d1);
834 enable_ide(0x26e);
835 }
836
837
838 #ifdef CONFIG_TGA_CONSOLE
839 extern void tga_console_init(void);
840 #endif /* CONFIG_TGA_CONSOLE */
841
842 unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
/* */
843 {
844 #if PCI_MODIFY
845 /*
846 * Scan the tree, allocating PCI memory and I/O space.
847 */
848 layout_bus(&pci_root);
849 #endif
850
851 /*
852 * Now is the time to do all those dirty little deeds...
853 */
854 #if defined(CONFIG_ALPHA_NONAME) || defined(CONFIG_ALPHA_AVANTI) || defined(CONFIG_ALPHA_P2K)
855 sio_fixup();
856 #elif defined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB164)
857 cabriolet_fixup();
858 #elif defined(CONFIG_ALPHA_EB66P)
859 eb66p_fixup();
860 #elif defined(CONFIG_ALPHA_EB66)
861 eb66_and_eb64p_fixup();
862 #elif defined(CONFIG_ALPHA_EB64P)
863 eb66_and_eb64p_fixup();
864 #else
865 # error You must tell me what kind of platform you want.
866 #endif
867
868 #ifdef CONFIG_TGA_CONSOLE
869 tga_console_init();
870 #endif /* CONFIG_TGA_CONSOLE */
871
872 return mem_start;
873 }
874
875
876 const char *pcibios_strerror (int error)
/* ![[last]](../icons/n_last.png)
*/
877 {
878 static char buf[80];
879
880 switch (error) {
881 case PCIBIOS_SUCCESSFUL:
882 return "SUCCESSFUL";
883
884 case PCIBIOS_FUNC_NOT_SUPPORTED:
885 return "FUNC_NOT_SUPPORTED";
886
887 case PCIBIOS_BAD_VENDOR_ID:
888 return "SUCCESSFUL";
889
890 case PCIBIOS_DEVICE_NOT_FOUND:
891 return "DEVICE_NOT_FOUND";
892
893 case PCIBIOS_BAD_REGISTER_NUMBER:
894 return "BAD_REGISTER_NUMBER";
895
896 default:
897 sprintf (buf, "UNKNOWN RETURN 0x%x", error);
898 return buf;
899 }
900 }
901
902 #endif /* CONFIG_PCI */
![[bottom]](../icons/n_bottom.png){kind=icon}
*/