root/arch/mips/kernel/head.S

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   1 /*
   2  *  arch/mips/kernel/head.S
   3  *
   4  *  Copyright (C) 1994, 1995 Waldorf Electronics
   5  *  Written by Ralf Baechle and Andreas Busse
   6  *
   7  *  Head.S contains the MIPS exception handler and startup code.
   8  */
   9 #include <linux/tasks.h>
  10 
  11 #include <asm/asm.h>
  12 #include <asm/segment.h>
  13 #include <asm/cachectl.h>
  14 #include <asm/mipsregs.h>
  15 #include <asm/mipsconfig.h>
  16 #include <asm/stackframe.h>
  17 #include <asm/bootinfo.h>
  18 
  19 #define PAGE_SIZE       0x1000
  20 
  21 #define MODE_GLOBAL     0x0001  /* shared for all processes */
  22 #define MODE_ALIAS      0x0016  /* uncachable */
  23 
  24                 .text
  25                 .set    mips3
  26 /*
  27  * This is space for the interrupt handlers.
  28  * They are located at virtual address KSEG[01] (physical 0x0)
  29  */
  30                 /*
  31                  * TLB refill, EXL == 0
  32                  */
  33                 .set    noreorder
  34                 .set    noat
  35                 LEAF(except_vec0)
  36                 dmfc0   k1,CP0_CONTEXT
  37                 dsra    k1,1
  38                 lwu     k0,(k1)                 # May cause another exception
  39                 lwu     k1,4(k1)
  40                 dsrl    k0,6                    # Convert to EntryLo format
  41                 dsrl    k1,6                    # Convert to EntryLo format
  42                 dmtc0   k0,CP0_ENTRYLO0
  43                 dmtc0   k1,CP0_ENTRYLO1
  44                 nop                             # Needed for R4[04]00 pipeline
  45                 tlbwr
  46                 nop                             # Needed for R4[04]00 pipeline
  47                 nop
  48                 nop
  49                 eret
  50                 /*
  51                  * Workaround for R4000 bug.  For explanation see MIPS
  52                  * docs.  Note that this that obscure that it wont almost
  53                  * never happen.  Well, but Mips writes about it's bugs.
  54                  */
  55                 nop
  56                 eret
  57                 END(except_vec0)
  58 
  59                 /*
  60                  * XTLB refill, EXL == 0
  61                  * Should never be reached
  62                  */
  63                 .org    except_vec0+0x80
  64                 LEAF(except_vec1)
  65                 PANIC("XTLB Refill exception.\n")
  66 1:              j       1b
  67                 nop
  68                 END(except_vec1)
  69 
  70                 /*
  71                  * Cache Error
  72                  */
  73                 .org    except_vec1+0x80
  74                 LEAF(except_vec2)
  75                 /*
  76                  * Famous last words: unreached
  77                  */
  78                 mfc0    a1,CP0_ERROREPC
  79                 PRINT("Cache error exception: c0_errorepc == %08x\n")
  80 1:              j       1b
  81                 nop
  82                 END(except_vec2)
  83 
  84                 /*
  85                  * General exception vector.
  86                  */
  87                 .org    except_vec2+0x80
  88                 NESTED(except_vec3, 0, sp)
  89                 .set    noat
  90                 /*
  91                  * Register saving is delayed as long as we don't know
  92                  * which registers really need to be saved.
  93                  */
  94                 mfc0    k1,CP0_CAUSE
  95                 la      k0,exception_handlers
  96                 /*
  97                  * Next lines assumes that the used CPU type has max.
  98                  * 32 different types of exceptions. We might use this
  99                  * to implement software exceptions in the future.
 100                  */
 101                 andi    k1,0x7c
 102                 addu    k0,k1
 103                 lw      k0,(k0)
 104                 NOP
 105                 jr      k0
 106                 nop
 107                 END(except_vec3)
 108                 .set    at
 109 
 110 /******************************************************************************/
 111 
 112 /*
 113  * Kernel entry
 114  */
 115                 .set    noreorder
 116                 NESTED(kernel_entry, 16, sp)
 117                 /*
 118                  * The following two symbols are used for kernel profiling.
 119                  */
 120                 EXPORT(stext)
 121                 EXPORT(_stext)
 122 
 123 #ifdef CONF_DISABLE_KSEG0_CACHING
 124                 /*
 125                  * Disable all caching for KSEG0.  This option is useful
 126                  * when cache trouble with drivers is suspected
 127                  */
 128                 mfc0    t0,CP0_CONFIG
 129                 ori     t0,7
 130                 xori    t0,5
 131                 mtc0    t0,CP0_CONFIG
 132 #endif
 133                 /*
 134                  * Clear BSS first so that there are no surprises...
 135                  */
 136                 la      t0,_edata
 137                 la      t1,_end
 138                 sw      zero,(t0)
 139 1:              addiu   t0,4
 140                 bnel    t0,t1,1b
 141                 sw      zero,(t0)
 142 
 143                 /*
 144                  * Initialize low level part of memory management
 145                  * First flush the TLB to make sure that we don't get a
 146                  * TLB shutdown during wire_mappings.
 147                  */
 148                 jal     tlbflush
 149                 mtc0    zero,CP0_WIRED                  # delay slot
 150                 jal     wire_mappings
 151                 nop
 152 
 153                 /*
 154                  * Stack for kernel and init
 155                  */
 156                 la      sp,init_user_stack+PAGE_SIZE-24
 157                 la      t0,init_kernel_stack+PAGE_SIZE
 158                 sw      t0,kernelsp
 159 
 160                 /*
 161                  * Disable coprocessors; set ST0_CU0 to indicate that
 162                  * we're running on the kernel stack
 163                  */
 164                 mfc0    t0,CP0_STATUS
 165                 li      t1,~(ST0_CU1|ST0_CU2|ST0_CU3)
 166                 and     t0,t1
 167                 li      t1,ST0_CU0
 168                 or      t0,ST0_CU0
 169                 mtc0    t0,CP0_STATUS
 170 
 171 1:              jal     start_kernel
 172                 nop                                     # delay slot
 173                 /*
 174                  * Main should never return here, but
 175                  * just in case, we know what happens.
 176                  */
 177                 b       1b
 178                 nop                                     # delay slot
 179                 END(kernel_entry)
 180 
 181 /*
 182  * wire_mappings - used to map hardware registers
 183  */
 184                 LEAF(wire_mappings)
 185                 /*
 186                  * Get base address of map0 table for the
 187                  * the board we're running on
 188                  */
 189                 la      t0,boot_info
 190                 lw      t1,OFFSET_BOOTINFO_MACHTYPE(t0)
 191                 la      t0,map0table
 192                 sll     t1,PTRLOG               # machtype used as index
 193                 addu    t0,t1
 194                 lw      t0,(t0)                 # get base address
 195 
 196                 /*
 197                  * Get number of wired TLB entries and
 198                  * loop over selected map0 table.
 199                  */
 200                 lw      t1,(t0)                 # number of wired TLB entries
 201                 move    t2,zero                 # TLB entry counter
 202                 addiu   t3,t1,1                 # wire one additional entry
 203                 beqz    t1,2f                   # null, exit
 204                 mtc0    t3,CP0_WIRED            # delay slot
 205                 addiu   t0,8
 206 1:              lw      t4,24(t0)               # PageMask
 207                 ld      t5,0(t0)                # entryHi
 208                 ld      t6,8(t0)                # entryLo0
 209                 ld      t7,16(t0)               # entryLo1
 210                 addiu   t2,1                    # increment ctr
 211                 mtc0    t2,CP0_INDEX            # set TLB entry
 212                 mtc0    t4,CP0_PAGEMASK
 213                 dmtc0   t5,CP0_ENTRYHI
 214                 dmtc0   t6,CP0_ENTRYLO0
 215                 dmtc0   t7,CP0_ENTRYLO1
 216                 addiu   t0,32
 217                 bne     t1,t2,1b                # next TLB entry
 218                 tlbwi                           # delay slot
 219 
 220                 /*
 221                  * We use only 4k pages. Therefore the PageMask register
 222                  * is expected to be setup for 4k pages.
 223                  */
 224 2:              li      t0,PM_4K
 225                 mtc0    t0,CP0_PAGEMASK
 226 
 227                 /*
 228                  * Now map the pagetables
 229                  */
 230                 mtc0    zero,CP0_INDEX
 231                 la      t0,TLB_ROOT
 232                 dmtc0   t0,CP0_ENTRYHI
 233                 la      t0,swapper_pg_dir-KSEG1
 234                 srl     t0,6
 235                 ori     t0,(MODE_ALIAS|MODE_GLOBAL) # uncachable, dirty, valid
 236                 dmtc0   t0,CP0_ENTRYLO0
 237                 li      t0,MODE_GLOBAL
 238                 dmtc0   t0,CP0_ENTRYLO1
 239                 nop
 240                 tlbwi                           # delayed
 241 
 242                 /*
 243                  * Load the context register with a value that allows
 244                  * it to be used as fast as possible in tlb exceptions.
 245                  * It is expected that this register's content will
 246                  * NEVER be changed.
 247                  */
 248                 li      t0,TLBMAP
 249                 dsll    t0,1
 250                 dmtc0   t0,CP0_CONTEXT
 251                 jr      ra                      # delay slot
 252                 nop
 253                 END(wire_mappings)
 254 
 255                 .data
 256 /*
 257  * Build an entry for table of wired entries
 258  */
 259 #define MAPDATA(q1,q2,q3,w1)                                    \
 260                 .quad   q1;                                     \
 261                 .quad   q2;                                     \
 262                 .quad   q3;                                     \
 263                 .word   w1;                                     \
 264                 .word   0
 265 
 266 /*
 267  * Initial mapping tables for supported Mips boards.
 268  * First item is always the number of wired TLB entries,
 269  * following by EntryHi/EntryLo pairs and page mask.
 270  * Since everything must be quad-aligned (8) we insert
 271  * some dummy zeros.
 272  */
 273 
 274 /*
 275  * Address table of mapping tables for supported Mips boards.
 276  * Add your own stuff here but don't forget to define your
 277  * target system in bootinfo.h
 278  */
 279 
 280 map0table:      PTR     map0_dummy              # machtype = unknown
 281                 PTR     map0_rpc                # Deskstation rPC44
 282                 PTR     map0_tyne               # Deskstation Tyne
 283                 PTR     map0_pica61             # Acer Pica-61
 284                 PTR     map0_magnum4000         # MIPS Magnum 4000PC (RC4030)
 285 
 286 map0_dummy:     .word   0                       # 0 entries
 287 
 288                 .align  3
 289 /*
 290  * Initial mappings for Deskstation rPC boards.
 291  * RB: Untested goodie - I don't have such a board.
 292  */
 293 map0_rpc:       .word   2                       # no. of wired TLB entries
 294                 .word   0                       # pad for alignment
 295 
 296 MAPDATA(0xffffffffe0000000, 0x04020017, 0x00000001, PM_1M)      # VESA DMA cache
 297 MAPDATA(0xffffffffe2000000, 0x24000017, 0x04000017, PM_16M)     # VESA I/O and memory space
 298 
 299 /*
 300  * Initial mappings for Deskstation Tyne boards.
 301  */
 302 map0_tyne:      .word   2                       # no. of wired TLB entries
 303                 .word   0                       # pad for alignment
 304 
 305 MAPDATA(0xffffffffe0000000, 0x04020017, 0x00000001, PM_1M)      # VESA DMA cache
 306 MAPDATA(0xffffffffe2000000, 0x24000017, 0x04000017, PM_16M)     # VESA I/O and memory space
 307 
 308 /*
 309  * Initial mapping for ACER PICA-61 boards.
 310  * FIXME: These are rather preliminary since many drivers, such as serial,
 311  * parallel, scsi and ethernet need some changes to distinguish between "local"
 312  * (built-in) and "optional" (ISA/PCI) I/O hardware. Local video ram is mapped
 313  * to the same location as the bios maps it to. Console driver has been changed
 314  * accordingly (new video type: VIDEO_TYPE_PICA_S3).
 315  * FIXME: Remove or merge some of the mappings.
 316  */
 317 map0_pica61:    .word   7                       # no. wired TLB entries
 318                 .word   0                       # dummy
 319 
 320 MAPDATA(0xffffffffe0000000, 0x02000017, 0x00000001, PM_64K)     # Local I/O space
 321 MAPDATA(0xffffffffe0100000, 0x03c00017, 0x00000001, PM_4K)      # Interrupt source register
 322 MAPDATA(0xffffffffe0200000, 0x01800017, 0x01804017, PM_1M)      # Local video control
 323 MAPDATA(0xffffffffe0400000, 0x01808017, 0x0180c017, PM_1M)      # Extended video control
 324 MAPDATA(0xffffffffe0800000, 0x01000017, 0x01010017, PM_4M)      # Local video memory (BIOS mapping)
 325 MAPDATA(0xffffffffe2000000, 0x02400017, 0x02440017, PM_16M)     # ISA I/O and ISA memory space (both 16M)
 326 MAPDATA(0xffffffffffffe000, 0x00000001, 0x0001ffd7, PM_4K)      # PCR (???)
 327 
 328 /*
 329  * Initial mapping for Mips Magnum 4000PC systems.
 330  * Do you believe me now that the Acer and Mips boxes are nearly the same ? :-)
 331  * FIXME: Remove or merge some of the mappings.
 332  */
 333 
 334 map0_magnum4000:
 335                 .word   8                       # no. wired TLB entries
 336                 .word   0                       # dummy
 337 
 338 MAPDATA(0xffffffffe1000000, 0x03ffc013, 0x00000001, 0x7e000)    # 0
 339 MAPDATA(0xffffffffe0000000, 0x02000017, 0x00000001, 0x1e000)    # 1 local I/O
 340 MAPDATA(0xffffffffe0100000, 0x03c00017, 0x00000001, 0)          # 2 IRQ source
 341 MAPDATA(0xffffffffe0200000, 0x01800017, 0x01804017, 0x1fe000)   # 3 local video ctrl
 342 MAPDATA(0xffffffffe0400000, 0x01808017, 0x0180c017, 0x1fe000)   # 4 ext. video ctrl
 343 MAPDATA(0xffffffffe0800000, 0x01000017, 0x01010017, 0x7fe000)   # 5 local video mem.
 344 MAPDATA(0xffffffffe2000000, 0x02400017, 0x02440017, 0x1ffe000)  # 6 ISA I/O and mem.
 345 MAPDATA(0xffffffffffffe000, 0x00000001, 0x0001ffd7, 0)          # 7 PCR
 346 
 347 
 348                         .text
 349 
 350                         .org    0x1000
 351                         .globl  swapper_pg_dir
 352 swapper_pg_dir          =       . + (KSEG1-KSEG0)
 353 
 354 /*
 355  * The page tables are initialized to only 4MB here - the final page
 356  * tables are set up later depending on memory size.
 357  */
 358                         .org    0x2000
 359                         EXPORT(pg0)
 360 
 361                         .org    0x3000
 362                         EXPORT(empty_bad_page)
 363 
 364                         .org    0x4000
 365                         EXPORT(empty_bad_page_table)
 366 
 367                         .org    0x5000
 368                         EXPORT(empty_zero_page)
 369 
 370                         .org    0x6000
 371                         EXPORT(invalid_pte_table)
 372 
 373                         .org    0x7000
 374 
 375                         EXPORT(cache_error_buffer)
 376                         .fill   32*4,1,0
 377 
 378                         .data
 379                         EXPORT(kernelsp)
 380                         PTR     0

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