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*/
1 /*
2 * Intel MP v1.1/v1.4 specification support routines for multi-pentium
3 * hosts.
4 *
5 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
6 * Supported by Caldera http://www.caldera.com.
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium and
11 * Pentium Pro MP machines.
12 *
13 * This code is released under the GNU public license version 2 or
14 * later.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIP report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/string.h>
26 #include <linux/timer.h>
27 #include <linux/sched.h>
28 #include <linux/mm.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/delay.h>
31 #include <linux/mc146818rtc.h>
32 #include <asm/i82489.h>
33 #include <linux/smp.h>
34 #include <asm/pgtable.h>
35 #include <asm/bitops.h>
36 #include <asm/pgtable.h>
37 #include <asm/smp.h>
38
39 /*
40 * Why isn't this somewhere standard ??
41 */
42
43 extern __inline int max(int a,int b)
/* ![[next]](../icons/right.png)
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*/
44 {
45 if(a>b)
46 return a;
47 return b;
48 }
49
50
51 int smp_found_config=0; /* Have we found an SMP box */
52
53 unsigned long cpu_present_map = 0; /* Bitmask of existing CPU's */
54 int smp_num_cpus = 1; /* Total count of live CPU's */
55 int smp_threads_ready=0; /* Set when the idlers are all forked */
56 volatile int cpu_number_map[NR_CPUS]; /* which CPU maps to which logical number */
57 volatile int cpu_logical_map[NR_CPUS]; /* which logical number maps to which CPU */
58 volatile unsigned long cpu_callin_map[NR_CPUS] = {0,}; /* We always use 0 the rest is ready for parallel delivery */
59 volatile unsigned long smp_invalidate_needed; /* Used for the invalidate map thats also checked in the spinlock */
60 struct cpuinfo_x86 cpu_data[NR_CPUS]; /* Per cpu bogomips and other parameters */
61 static unsigned int num_processors = 1; /* Internal processor count */
62 static unsigned long io_apic_addr = 0xFEC00000; /* Address of the I/O apic (not yet used) */
63 unsigned char boot_cpu_id = 0; /* Processor that is doing the boot up */
64 static unsigned char *kstack_base,*kstack_end; /* Kernel stack list pointers */
65 static int smp_activated = 0; /* Tripped once we need to start cross invalidating */
66 int apic_version[NR_CPUS]; /* APIC version number */
67 static volatile int smp_commenced=0; /* Tripped when we start scheduling */
68 unsigned long apic_addr=0xFEE00000; /* Address of APIC (defaults to 0xFEE00000) */
69 unsigned long nlong = 0; /* dummy used for apic_reg address + 0x20 */
70 unsigned char *apic_reg=((unsigned char *)(&nlong))-0x20;/* Later set to the vremap() of the APIC */
71 unsigned long apic_retval; /* Just debugging the assembler.. */
72 unsigned char *kernel_stacks[NR_CPUS]; /* Kernel stack pointers for CPU's (debugging) */
73
74 static volatile unsigned char smp_cpu_in_msg[NR_CPUS]; /* True if this processor is sending an IPI */
75 static volatile unsigned long smp_msg_data; /* IPI data pointer */
76 static volatile int smp_src_cpu; /* IPI sender processor */
77 static volatile int smp_msg_id; /* Message being sent */
78
79 volatile unsigned long kernel_flag=0; /* Kernel spinlock */
80 volatile unsigned char active_kernel_processor = NO_PROC_ID; /* Processor holding kernel spinlock */
81 volatile unsigned long kernel_counter=0; /* Number of times the processor holds the lock */
82 volatile unsigned long syscall_count=0; /* Number of times the processor holds the syscall lock */
83
84 volatile unsigned long ipi_count; /* Number of IPI's delivered */
85 #ifdef __SMP_PROF__
86 volatile unsigned long smp_spins[NR_CPUS]={0}; /* Count interrupt spins */
87 volatile unsigned long smp_spins_syscall[NR_CPUS]={0}; /* Count syscall spins */
88 volatile unsigned long smp_spins_syscall_cur[NR_CPUS]={0};/* Count spins for the actual syscall */
89 volatile unsigned long smp_spins_sys_idle[NR_CPUS]={0}; /* Count spins for sys_idle */
90 volatile unsigned long smp_idle_count[1+NR_CPUS]={0,}; /* Count idle ticks */
91 #endif
92 #if defined (__SMP_PROF__)
93 volatile unsigned long smp_idle_map=0; /* Map for idle processors */
94 #endif
95
96 volatile unsigned long smp_proc_in_lock[NR_CPUS] = {0,};/* for computing process time */
97 volatile unsigned long smp_process_available=0;
98
99 /*#define SMP_DEBUG*/
100
101 #ifdef SMP_DEBUG
102 #define SMP_PRINTK(x) printk x
103 #else
104 #define SMP_PRINTK(x)
105 #endif
106
107
108 /*
109 * Checksum an MP configuration block.
110 */
111
112 static int mpf_checksum(unsigned char *mp, int len)
/* ![[previous]](../icons/left.png)
*/
113 {
114 int sum=0;
115 while(len--)
116 sum+=*mp++;
117 return sum&0xFF;
118 }
119
120 /*
121 * Processor encoding in an MP configuration block
122 */
123
124 static char *mpc_family(int family,int model)
/* */
125 {
126 static char n[32];
127 static char *model_defs[]=
128 {
129 "80486DX","80486DX",
130 "80486SX","80486DX/2 or 80487",
131 "80486SL","Intel5X2(tm)",
132 "Unknown","Unknown",
133 "80486DX/4"
134 };
135 if(family==0x6)
136 return("Pentium(tm) Pro");
137 if(family==0x5)
138 return("Pentium(tm)");
139 if(family==0x0F && model==0x0F)
140 return("Special controller");
141 if(family==0x04 && model<9)
142 return model_defs[model];
143 sprintf(n,"Unknown CPU [%d:%d]",family, model);
144 return n;
145 }
146
147 /*
148 * Read the MPC
149 */
150
151 static int smp_read_mpc(struct mp_config_table *mpc)
/* */
152 {
153 char str[16];
154 int count=sizeof(*mpc);
155 int apics=0;
156 unsigned char *mpt=((unsigned char *)mpc)+count;
157
158 if(memcmp(mpc->mpc_signature,MPC_SIGNATURE,4))
159 {
160 printk("Bad signature [%c%c%c%c].\n",
161 mpc->mpc_signature[0],
162 mpc->mpc_signature[1],
163 mpc->mpc_signature[2],
164 mpc->mpc_signature[3]);
165 return 1;
166 }
167 if(mpf_checksum((unsigned char *)mpc,mpc->mpc_length))
168 {
169 printk("Checksum error.\n");
170 return 1;
171 }
172 if(mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04)
173 {
174 printk("Bad Config Table version (%d)!!\n",mpc->mpc_spec);
175 return 1;
176 }
177 memcpy(str,mpc->mpc_oem,8);
178 str[8]=0;
179 printk("OEM ID: %s ",str);
180 memcpy(str,mpc->mpc_productid,12);
181 str[12]=0;
182 printk("Product ID: %s ",str);
183 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
184
185 /* set the local APIC address */
186 apic_addr = mpc->mpc_lapic;
187
188 /*
189 * Now process the configuration blocks.
190 */
191
192 while(count<mpc->mpc_length)
193 {
194 switch(*mpt)
195 {
196 case MP_PROCESSOR:
197 {
198 struct mpc_config_processor *m=
199 (struct mpc_config_processor *)mpt;
200 if(m->mpc_cpuflag&CPU_ENABLED)
201 {
202 printk("Processor #%d %s APIC version %d\n",
203 m->mpc_apicid,
204 mpc_family((m->mpc_cpufeature&
205 CPU_FAMILY_MASK)>>8,
206 (m->mpc_cpufeature&
207 CPU_MODEL_MASK)>>4),
208 m->mpc_apicver);
209 #ifdef SMP_DEBUG
210 if(m->mpc_featureflag&(1<<0))
211 printk(" Floating point unit present.\n");
212 if(m->mpc_featureflag&(1<<7))
213 printk(" Machine Exception supported.\n");
214 if(m->mpc_featureflag&(1<<8))
215 printk(" 64 bit compare & exchange supported.\n");
216 if(m->mpc_featureflag&(1<<9))
217 printk(" Internal APIC present.\n");
218 #endif
219 if(m->mpc_cpuflag&CPU_BOOTPROCESSOR)
220 {
221 SMP_PRINTK((" Bootup CPU\n"));
222 boot_cpu_id=m->mpc_apicid;
223 }
224 else /* Boot CPU already counted */
225 num_processors++;
226
227 if(m->mpc_apicid>NR_CPUS)
228 printk("Processor #%d unused. (Max %d processors).\n",m->mpc_apicid, NR_CPUS);
229 else
230 {
231 cpu_present_map|=(1<<m->mpc_apicid);
232 apic_version[m->mpc_apicid]=m->mpc_apicver;
233 }
234 }
235 mpt+=sizeof(*m);
236 count+=sizeof(*m);
237 break;
238 }
239 case MP_BUS:
240 {
241 struct mpc_config_bus *m=
242 (struct mpc_config_bus *)mpt;
243 memcpy(str,m->mpc_bustype,6);
244 str[6]=0;
245 SMP_PRINTK(("Bus #%d is %s\n",
246 m->mpc_busid,
247 str));
248 mpt+=sizeof(*m);
249 count+=sizeof(*m);
250 break;
251 }
252 case MP_IOAPIC:
253 {
254 struct mpc_config_ioapic *m=
255 (struct mpc_config_ioapic *)mpt;
256 if(m->mpc_flags&MPC_APIC_USABLE)
257 {
258 apics++;
259 printk("I/O APIC #%d Version %d at 0x%lX.\n",
260 m->mpc_apicid,m->mpc_apicver,
261 m->mpc_apicaddr);
262 io_apic_addr = m->mpc_apicaddr;
263 }
264 mpt+=sizeof(*m);
265 count+=sizeof(*m);
266 break;
267 }
268 case MP_INTSRC:
269 {
270 struct mpc_config_intsrc *m=
271 (struct mpc_config_intsrc *)mpt;
272
273 mpt+=sizeof(*m);
274 count+=sizeof(*m);
275 break;
276 }
277 case MP_LINTSRC:
278 {
279 struct mpc_config_intlocal *m=
280 (struct mpc_config_intlocal *)mpt;
281 mpt+=sizeof(*m);
282 count+=sizeof(*m);
283 break;
284 }
285 }
286 }
287 if(apics>1)
288 printk("Warning: Multiple APIC's not supported.\n");
289 return num_processors;
290 }
291
292 /*
293 * Scan the memory blocks for an SMP configuration block.
294 */
295
296 int smp_scan_config(unsigned long base, unsigned long length)
/* */
297 {
298 unsigned long *bp=(unsigned long *)base;
299 struct intel_mp_floating *mpf;
300
301 SMP_PRINTK(("Scan SMP from %p for %ld bytes.\n",
302 bp,length));
303 if(sizeof(*mpf)!=16)
304 printk("Error: MPF size\n");
305
306 while(length>0)
307 {
308 if(*bp==SMP_MAGIC_IDENT)
309 {
310 mpf=(struct intel_mp_floating *)bp;
311 if(mpf->mpf_length==1 &&
312 !mpf_checksum((unsigned char *)bp,16) &&
313 (mpf->mpf_specification == 1
314 || mpf->mpf_specification == 4) )
315 {
316 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
317 if(mpf->mpf_feature2&(1<<7))
318 printk(" IMCR and PIC compatibility mode.\n");
319 else
320 printk(" Virtual Wire compatibility mode.\n");
321 smp_found_config=1;
322 /*
323 * Now see if we need to read further.
324 */
325 if(mpf->mpf_feature1!=0)
326 {
327 unsigned long cfg;
328
329 /*
330 * We need to know what the local
331 * APIC id of the boot CPU is!
332 */
333
334 /*
335 *
336 * HACK HACK HACK HACK HACK HACK HACK HACK HACK HACK HACK HACK HACK
337 *
338 * It's not just a crazy hack... ;-)
339 */
340 /*
341 * Standard page mapping
342 * functions don't work yet.
343 * We know that page 0 is not
344 * used. Steal it for now!
345 */
346
347 cfg=pg0[0];
348 pg0[0] = (apic_addr | 7);
349 local_flush_tlb();
350
351 boot_cpu_id = GET_APIC_ID(*((volatile unsigned long *) APIC_ID));
352
353 /*
354 * Give it back
355 */
356
357 pg0[0]= cfg;
358 local_flush_tlb();
359
360 /*
361 *
362 * END OF HACK END OF HACK END OF HACK END OF HACK END OF HACK
363 *
364 */
365 /*
366 * 2 CPUs, numbered 0 & 1.
367 */
368 cpu_present_map=3;
369 num_processors=2;
370 printk("I/O APIC at 0xFEC00000.\n");
371 printk("Bus#0 is ");
372 }
373 switch(mpf->mpf_feature1)
374 {
375 case 1:
376 case 5:
377 printk("ISA\n");
378 break;
379 case 2:
380 printk("EISA with no IRQ8 chaining\n");
381 break;
382 case 6:
383 case 3:
384 printk("EISA\n");
385 break;
386 case 4:
387 case 7:
388 printk("MCA\n");
389 break;
390 case 0:
391 break;
392 default:
393 printk("???\nUnknown standard configuration %d\n",
394 mpf->mpf_feature1);
395 return 1;
396 }
397 if(mpf->mpf_feature1>4)
398 {
399 printk("Bus #1 is PCI\n");
400
401 /*
402 * Set local APIC version to
403 * the integrated form.
404 * It's initialized to zero
405 * otherwise, representing
406 * a discrete 82489DX.
407 */
408 apic_version[0] = 0x10;
409 apic_version[1] = 0x10;
410 }
411 /*
412 * Read the physical hardware table.
413 * Anything here will override the
414 * defaults.
415 */
416 if(mpf->mpf_physptr)
417 smp_read_mpc((void *)mpf->mpf_physptr);
418
419 /*
420 * Now that the boot CPU id is known,
421 * set some other information about it.
422 */
423 nlong = boot_cpu_id<<24; /* Dummy 'self' for bootup */
424 cpu_logical_map[0] = boot_cpu_id;
425
426 printk("Processors: %d\n", num_processors);
427 /*
428 * Only use the first configuration found.
429 */
430 return 1;
431 }
432 }
433 bp+=4;
434 length-=16;
435 }
436
437 return 0;
438 }
439
440 /*
441 * Trampoline 80x86 program as an array.
442 */
443
444 static unsigned char trampoline_data[]={
445 #include "trampoline.hex"
446 };
447
448 /*
449 * Currently trivial. Write the real->protected mode
450 * bootstrap into the page concerned. The caller
451 * has made sure its suitably aligned.
452 */
453
454 static void install_trampoline(unsigned char *mp)
/* */
455 {
456 memcpy(mp,trampoline_data,sizeof(trampoline_data));
457 }
458
459 /*
460 * We are called very early to get the low memory for the trampoline/kernel stacks
461 * This has to be done by mm/init.c to parcel us out nice low memory. We allocate
462 * the kernel stacks at 4K, 8K, 12K... currently (0-03FF is preserved for SMM and
463 * other things).
464 */
465
466 unsigned long smp_alloc_memory(unsigned long mem_base)
/* */
467 {
468 int size=(num_processors-1)*PAGE_SIZE; /* Number of stacks needed */
469 /*
470 * Our stacks have to be below the 1Mb line, and mem_base on entry
471 * is 4K aligned.
472 */
473
474 if(mem_base+size>=0x9F000)
475 panic("smp_alloc_memory: Insufficient low memory for kernel stacks.\n");
476 kstack_base=(void *)mem_base;
477 mem_base+=size;
478 kstack_end=(void *)mem_base;
479 return mem_base;
480 }
481
482 /*
483 * Hand out stacks one at a time.
484 */
485
486 static void *get_kernel_stack(void)
/* */
487 {
488 void *stack=kstack_base;
489 if(kstack_base>=kstack_end)
490 return NULL;
491 kstack_base+=PAGE_SIZE;
492 return stack;
493 }
494
495
496 /*
497 * The bootstrap kernel entry code has set these up. Save them for
498 * a given CPU
499 */
500
501 void smp_store_cpu_info(int id)
/* */
502 {
503 struct cpuinfo_x86 *c=&cpu_data[id];
504 c->hard_math=hard_math; /* Always assumed same currently */
505 c->x86=x86;
506 c->x86_model=x86_model;
507 c->x86_mask=x86_mask;
508 c->x86_capability=x86_capability;
509 c->fdiv_bug=fdiv_bug;
510 c->wp_works_ok=wp_works_ok; /* Always assumed the same currently */
511 c->hlt_works_ok=hlt_works_ok;
512 c->have_cpuid=have_cpuid;
513 c->udelay_val=loops_per_sec;
514 strcpy(c->x86_vendor_id, x86_vendor_id);
515 }
516
517 /*
518 * Architecture specific routine called by the kernel just before init is
519 * fired off. This allows the BP to have everything in order [we hope].
520 * At the end of this all the AP's will hit the system scheduling and off
521 * we go. Each AP will load the system gdt's and jump through the kernel
522 * init into idle(). At this point the scheduler will one day take over
523 * and give them jobs to do. smp_callin is a standard routine
524 * we use to track CPU's as they power up.
525 */
526
527 void smp_commence(void)
/* */
528 {
529 /*
530 * Lets the callin's below out of their loop.
531 */
532 smp_commenced=1;
533 }
534
535 void smp_callin(void)
/* */
536 {
537 int cpuid=GET_APIC_ID(apic_read(APIC_ID));
538 unsigned long l;
539 /*
540 * Activate our APIC
541 */
542
543 SMP_PRINTK(("CALLIN %d\n",smp_processor_id()));
544 l=apic_read(APIC_SPIV);
545 l|=(1<<8); /* Enable */
546 apic_write(APIC_SPIV,l);
547 sti();
548 /*
549 * Get our bogomips.
550 */
551 calibrate_delay();
552 /*
553 * Save our processor parameters
554 */
555 smp_store_cpu_info(cpuid);
556 /*
557 * Allow the master to continue.
558 */
559 set_bit(cpuid, (unsigned long *)&cpu_callin_map[0]);
560 /*
561 * Until we are ready for SMP scheduling
562 */
563 load_ldt(0);
564 /* printk("Testing faulting...\n");
565 *(long *)0=1; OOPS... */
566 local_flush_tlb();
567 while(!smp_commenced);
568 if (cpu_number_map[cpuid] == -1)
569 while(1);
570 local_flush_tlb();
571 SMP_PRINTK(("Commenced..\n"));
572
573 load_TR(cpu_number_map[cpuid]);
574 /* while(1);*/
575 }
576
577 /*
578 * Cycle through the processors sending pentium IPI's to boot each.
579 */
580
581 void smp_boot_cpus(void)
/* */
582 {
583 int i;
584 int cpucount=0;
585 unsigned long cfg;
586 void *stack;
587 extern unsigned long init_user_stack[];
588
589 /*
590 * Initialize the logical to physical cpu number mapping
591 */
592
593 for (i = 0; i < NR_CPUS; i++)
594 cpu_number_map[i] = -1;
595
596 /*
597 * Setup boot CPU information
598 */
599
600 kernel_stacks[boot_cpu_id]=(void *)init_user_stack; /* Set up for boot processor first */
601
602 smp_store_cpu_info(boot_cpu_id); /* Final full version of the data */
603
604 cpu_present_map |= (1 << smp_processor_id());
605 cpu_number_map[boot_cpu_id] = 0;
606 active_kernel_processor=boot_cpu_id;
607
608 /*
609 * If we don't conform to the Intel MPS standard, get out
610 * of here now!
611 */
612
613 if (!smp_found_config)
614 return;
615
616 /*
617 * Map the local APIC into kernel space
618 */
619
620 apic_reg = vremap(apic_addr,4096);
621
622 if(apic_reg == NULL)
623 panic("Unable to map local apic.\n");
624
625 #ifdef SMP_DEBUG
626 {
627 int reg;
628
629 /*
630 * This is to verify that we're looking at
631 * a real local APIC. Check these against
632 * your board if the CPUs aren't getting
633 * started for no apparent reason.
634 */
635
636 reg = apic_read(APIC_VERSION);
637 SMP_PRINTK(("Getting VERSION: %x\n", reg));
638
639 apic_write(APIC_VERSION, 0);
640 reg = apic_read(APIC_VERSION);
641 SMP_PRINTK(("Getting VERSION: %x\n", reg));
642
643 /*
644 * The two version reads above should print the same
645 * NON-ZERO!!! numbers. If the second one is zero,
646 * there is a problem with the APIC write/read
647 * definitions.
648 *
649 * The next two are just to see if we have sane values.
650 * They're only really relevant if we're in Virtual Wire
651 * compatibility mode, but most boxes are anymore.
652 */
653
654
655 reg = apic_read(APIC_LVT0);
656 SMP_PRINTK(("Getting LVT0: %x\n", reg));
657
658 reg = apic_read(APIC_LVT1);
659 SMP_PRINTK(("Getting LVT1: %x\n", reg));
660 }
661 #endif
662
663 /*
664 * Enable the local APIC
665 */
666
667 cfg=apic_read(APIC_SPIV);
668 cfg|=(1<<8); /* Enable APIC */
669 apic_write(APIC_SPIV,cfg);
670
671 udelay(10);
672
673 /*
674 * Now scan the cpu present map and fire up the other CPUs.
675 */
676
677 SMP_PRINTK(("CPU map: %lx\n", cpu_present_map));
678
679 for(i=0;i<NR_CPUS;i++)
680 {
681 /*
682 * Don't even attempt to start the boot CPU!
683 */
684 if (i == boot_cpu_id)
685 continue;
686
687 if (cpu_present_map & (1 << i))
688 {
689 unsigned long send_status, accept_status;
690 int timeout, num_starts, j;
691
692 /*
693 * We need a kernel stack for each processor.
694 */
695
696 stack=get_kernel_stack(); /* We allocated these earlier */
697 if(stack==NULL)
698 panic("No memory for processor stacks.\n");
699 kernel_stacks[i]=stack;
700 install_trampoline(stack);
701
702 printk("Booting processor %d stack %p: ",i,stack); /* So we set what's up */
703
704 /*
705 * This grunge runs the startup process for
706 * the targeted processor.
707 */
708
709 SMP_PRINTK(("Setting warm reset code and vector.\n"));
710
711 /*
712 * Install a writable page 0 entry.
713 */
714
715 cfg=pg0[0];
716
717 CMOS_WRITE(0xa, 0xf);
718 pg0[0]=7;
719 local_flush_tlb();
720 *((volatile unsigned short *) 0x469) = ((unsigned long)stack)>>4;
721 *((volatile unsigned short *) 0x467) = 0;
722
723 /*
724 * Protect it again
725 */
726
727 pg0[0]= cfg;
728 local_flush_tlb();
729
730 /*
731 * Be paranoid about clearing APIC errors.
732 */
733
734 if ( apic_version[i] & 0xF0 )
735 {
736 apic_write(APIC_ESR, 0);
737 accept_status = (apic_read(APIC_ESR) & 0xEF);
738 }
739
740 /*
741 * Status is now clean
742 */
743
744 send_status = 0;
745 accept_status = 0;
746
747 /*
748 * Starting actual IPI sequence...
749 */
750
751 SMP_PRINTK(("Asserting INIT.\n"));
752
753 /*
754 * Turn INIT on
755 */
756
757 cfg=apic_read(APIC_ICR2);
758 cfg&=0x00FFFFFF;
759 apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(i)); /* Target chip */
760 cfg=apic_read(APIC_ICR);
761 cfg&=~0xCDFFF; /* Clear bits */
762 cfg |= (APIC_DEST_FIELD | APIC_DEST_LEVELTRIG
763 | APIC_DEST_ASSERT | APIC_DEST_DM_INIT);
764 apic_write(APIC_ICR, cfg); /* Send IPI */
765
766 udelay(200);
767 SMP_PRINTK(("Deasserting INIT.\n"));
768
769 cfg=apic_read(APIC_ICR2);
770 cfg&=0x00FFFFFF;
771 apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(i)); /* Target chip */
772 cfg=apic_read(APIC_ICR);
773 cfg&=~0xCDFFF; /* Clear bits */
774 cfg |= (APIC_DEST_FIELD | APIC_DEST_LEVELTRIG
775 | APIC_DEST_DM_INIT);
776 apic_write(APIC_ICR, cfg); /* Send IPI */
777
778 /*
779 * Should we send STARTUP IPIs ?
780 *
781 * Determine this based on the APIC version.
782 * If we don't have an integrated APIC, don't
783 * send the STARTUP IPIs.
784 */
785
786 if ( apic_version[i] & 0xF0 )
787 num_starts = 2;
788 else
789 num_starts = 0;
790
791 /*
792 * Run STARTUP IPI loop.
793 */
794
795 for (j = 1; !(send_status || accept_status)
796 && (j <= num_starts) ; j++)
797 {
798 SMP_PRINTK(("Sending STARTUP #%d.\n",j));
799
800 apic_write(APIC_ESR, 0);
801
802 /*
803 * STARTUP IPI
804 */
805
806 cfg=apic_read(APIC_ICR2);
807 cfg&=0x00FFFFFF;
808 apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(i)); /* Target chip */
809 cfg=apic_read(APIC_ICR);
810 cfg&=~0xCDFFF; /* Clear bits */
811 cfg |= (APIC_DEST_FIELD
812 | APIC_DEST_DM_STARTUP
813 | (((int) stack) >> 12) ); /* Boot on the stack */
814 apic_write(APIC_ICR, cfg); /* Kick the second */
815
816 timeout = 0;
817 do {
818 udelay(10);
819 } while ( (send_status = (apic_read(APIC_ICR) & 0x1000))
820 && (timeout++ < 1000));
821 udelay(200);
822
823 accept_status = (apic_read(APIC_ESR) & 0xEF);
824 }
825
826 if (send_status) /* APIC never delivered?? */
827 printk("APIC never delivered???\n");
828 if (accept_status) /* Send accept error */
829 printk("APIC delivery error (%lx).\n", accept_status);
830
831 if( !(send_status || accept_status) )
832 {
833 for(timeout=0;timeout<50000;timeout++)
834 {
835 if(cpu_callin_map[0]&(1<<i))
836 break; /* It has booted */
837 udelay(100); /* Wait 5s total for a response */
838 }
839 if(cpu_callin_map[0]&(1<<i))
840 {
841 cpucount++;
842 /* number CPUs logically, starting from 1 (BSP is 0) */
843 cpu_number_map[i] = cpucount;
844 cpu_logical_map[cpucount] = i;
845 }
846 else
847 {
848 if(*((volatile unsigned char *)8192)==0xA5)
849 printk("Stuck ??\n");
850 else
851 printk("Not responding.\n");
852 }
853 }
854
855 /* mark "stuck" area as not stuck */
856 *((volatile unsigned long *)8192) = 0;
857 }
858
859 /*
860 * Make sure we unmap all failed CPUs
861 */
862
863 if (cpu_number_map[i] == -1)
864 cpu_present_map &= ~(1 << i);
865 }
866
867 /*
868 * Cleanup possible dangling ends...
869 */
870
871 /*
872 * Install writable page 0 entry.
873 */
874
875 cfg = pg0[0];
876 pg0[0] = 3; /* writeable, present, addr 0 */
877 local_flush_tlb();
878
879 /*
880 * Paranoid: Set warm reset code and vector here back
881 * to default values.
882 */
883
884 CMOS_WRITE(0, 0xf);
885
886 *((volatile long *) 0x467) = 0;
887
888 /*
889 * Restore old page 0 entry.
890 */
891
892 pg0[0] = cfg;
893 local_flush_tlb();
894
895 /*
896 * Allow the user to impress friends.
897 */
898
899 if(cpucount==0)
900 {
901 printk("Error: only one processor found.\n");
902 cpu_present_map=(1<<smp_processor_id());
903 }
904 else
905 {
906 unsigned long bogosum=0;
907 for(i=0;i<32;i++)
908 {
909 if(cpu_present_map&(1<<i))
910 bogosum+=cpu_data[i].udelay_val;
911 }
912 printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
913 cpucount+1,
914 (bogosum+2500)/500000,
915 ((bogosum+2500)/5000)%100);
916 smp_activated=1;
917 smp_num_cpus=cpucount+1;
918 }
919 }
920
921
922 /*
923 * A non wait message cannot pass data or cpu source info. This current setup
924 * is only safe because the kernel lock owner is the only person who can send a message.
925 *
926 * Wrapping this whole block in a spinlock is not the safe answer either. A processor may
927 * get stuck with irq's off waiting to send a message and thus not replying to the person
928 * spinning for a reply....
929 *
930 * In the end flush tlb ought to be the NMI and a very very short function (to avoid the old
931 * IDE disk problems), and other messages sent with IRQ's enabled in a civilised fashion. That
932 * will also boost performance.
933 */
934
935 void smp_message_pass(int target, int msg, unsigned long data, int wait)
/* */
936 {
937 unsigned long cfg;
938 unsigned long target_map;
939 int p=smp_processor_id();
940 int irq=0x2d; /* IRQ 13 */
941 int ct=0;
942 static volatile int message_cpu = NO_PROC_ID;
943
944 /*
945 * During boot up send no messages
946 */
947
948 if(!smp_activated || !smp_commenced)
949 return;
950
951
952 /*
953 * Skip the reschedule if we are waiting to clear a
954 * message at this time. The reschedule cannot wait
955 * but is not critical.
956 */
957
958 if(msg==MSG_RESCHEDULE) /* Reschedules we do via trap 0x30 */
959 {
960 irq=0x30;
961 if(smp_cpu_in_msg[p])
962 return;
963 }
964
965 /*
966 * Sanity check we don't re-enter this across CPU's. Only the kernel
967 * lock holder may send messages. For a STOP_CPU we are bringing the
968 * entire box to the fastest halt we can.. A reschedule carries
969 * no data and can occur during a flush.. guess what panic
970 * I got to notice this bug...
971 */
972
973 if(message_cpu!=NO_PROC_ID && msg!=MSG_STOP_CPU && msg!=MSG_RESCHEDULE)
974 {
975 panic("CPU #%d: Message pass %d but pass in progress by %d of %d\n",
976 smp_processor_id(),msg,message_cpu, smp_msg_id);
977 }
978 message_cpu=smp_processor_id();
979
980
981 /*
982 * We are busy
983 */
984
985 smp_cpu_in_msg[p]++;
986
987 /*
988 * Reschedule is currently special
989 */
990
991 if(msg!=MSG_RESCHEDULE)
992 {
993 smp_src_cpu=p;
994 smp_msg_id=msg;
995 smp_msg_data=data;
996 }
997
998 /* printk("SMP message pass #%d to %d of %d\n",
999 p, msg, target);*/
1000
1001 /*
1002 * Wait for the APIC to become ready - this should never occur. Its
1003 * a debugging check really.
1004 */
1005
1006 while(ct<1000)
1007 {
1008 cfg=apic_read(APIC_ICR);
1009 if(!(cfg&(1<<12)))
1010 break;
1011 ct++;
1012 udelay(10);
1013 }
1014
1015 /*
1016 * Just pray... there is nothing more we can do
1017 */
1018
1019 if(ct==1000)
1020 printk("CPU #%d: previous IPI still not cleared after 10mS", smp_processor_id());
1021
1022 /*
1023 * Program the APIC to deliver the IPI
1024 */
1025
1026 cfg=apic_read(APIC_ICR2);
1027 cfg&=0x00FFFFFF;
1028 apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(target)); /* Target chip */
1029 cfg=apic_read(APIC_ICR);
1030 cfg&=~0xFDFFF; /* Clear bits */
1031 cfg|=APIC_DEST_FIELD|APIC_DEST_DM_FIXED|irq; /* Send an IRQ 13 */
1032
1033 /*
1034 * Set the target requirement
1035 */
1036
1037 if(target==MSG_ALL_BUT_SELF)
1038 {
1039 cfg|=APIC_DEST_ALLBUT;
1040 target_map=cpu_present_map;
1041 cpu_callin_map[0]=(1<<smp_src_cpu);
1042 }
1043 else if(target==MSG_ALL)
1044 {
1045 cfg|=APIC_DEST_ALLINC;
1046 target_map=cpu_present_map;
1047 cpu_callin_map[0]=0;
1048 }
1049 else
1050 {
1051 target_map=(1<<target);
1052 cpu_callin_map[0]=0;
1053 }
1054
1055 /*
1056 * Send the IPI. The write to APIC_ICR fires this off.
1057 */
1058
1059 apic_write(APIC_ICR, cfg);
1060
1061 /*
1062 * Spin waiting for completion
1063 */
1064
1065 switch(wait)
1066 {
1067 case 1:
1068 while(cpu_callin_map[0]!=target_map); /* Spin on the pass */
1069 break;
1070 case 2:
1071 while(smp_invalidate_needed); /* Wait for invalidate map to clear */
1072 break;
1073 }
1074
1075 /*
1076 * Record our completion
1077 */
1078
1079 smp_cpu_in_msg[p]--;
1080 message_cpu=NO_PROC_ID;
1081 }
1082
1083 /*
1084 * This is fraught with deadlocks. Linus does a flush tlb at a whim
1085 * even with IRQ's off. We have to avoid a pair of crossing flushes
1086 * or we are doomed. See the notes about smp_message_pass.
1087 */
1088
1089 void smp_flush_tlb(void)
/* */
1090 {
1091 unsigned long flags;
1092 if(smp_activated && smp_processor_id()!=active_kernel_processor)
1093 panic("CPU #%d:Attempted flush tlb IPI when not AKP(=%d)\n",smp_processor_id(),active_kernel_processor);
1094 /* printk("SMI-");*/
1095
1096 /*
1097 * The assignment is safe because its volatile so the compiler cannot reorder it,
1098 * because the i586 has strict memory ordering and because only the kernel lock holder
1099 * may issue a tlb flush. If you break any one of those three change this to an atomic
1100 * bus locked or.
1101 */
1102
1103 smp_invalidate_needed=cpu_present_map&~(1<<smp_processor_id());
1104
1105 /*
1106 * Processors spinning on the lock will see this IRQ late. The smp_invalidate_needed map will
1107 * ensure they dont do a spurious flush tlb or miss one.
1108 */
1109
1110 save_flags(flags);
1111 cli();
1112 smp_message_pass(MSG_ALL_BUT_SELF, MSG_INVALIDATE_TLB, 0L, 2);
1113
1114 /*
1115 * Flush the local TLB
1116 */
1117
1118 local_flush_tlb();
1119
1120 restore_flags(flags);
1121
1122 /*
1123 * Completed.
1124 */
1125
1126 /* printk("SMID\n");*/
1127 }
1128
1129 /*
1130 * Reschedule call back
1131 */
1132
1133 void smp_reschedule_irq(int cpl, struct pt_regs *regs)
/* */
1134 {
1135 #ifdef DEBUGGING_SMP_RESCHED
1136 static int ct=0;
1137 if(ct==0)
1138 {
1139 printk("Beginning scheduling on CPU#%d\n",smp_processor_id());
1140 ct=1;
1141 }
1142 #endif
1143 if(smp_processor_id()!=active_kernel_processor)
1144 panic("SMP Reschedule on CPU #%d, but #%d is active.\n",
1145 smp_processor_id(), active_kernel_processor);
1146
1147 need_resched=1;
1148
1149 /*
1150 * Clear the IPI
1151 */
1152 apic_read(APIC_SPIV); /* Dummy read */
1153 apic_write(APIC_EOI, 0); /* Docs say use 0 for future compatibility */
1154 }
1155
1156 /*
1157 * Message call back.
1158 */
1159
1160 void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs)
/* ![[last]](../icons/n_last.png)
*/
1161 {
1162 int i=smp_processor_id();
1163 /* static int n=0;
1164 if(n++<NR_CPUS)
1165 printk("IPI %d->%d(%d,%ld)\n",smp_src_cpu,i,smp_msg_id,smp_msg_data);*/
1166 switch(smp_msg_id)
1167 {
1168 case 0: /* IRQ 13 testing - boring */
1169 return;
1170
1171 /*
1172 * A TLB flush is needed.
1173 */
1174
1175 case MSG_INVALIDATE_TLB:
1176 if(clear_bit(i,(unsigned long *)&smp_invalidate_needed))
1177 local_flush_tlb();
1178 set_bit(i, (unsigned long *)&cpu_callin_map[0]);
1179 /* cpu_callin_map[0]|=1<<smp_processor_id();*/
1180 break;
1181
1182 /*
1183 * Halt other CPU's for a panic or reboot
1184 */
1185 case MSG_STOP_CPU:
1186 while(1)
1187 {
1188 if(cpu_data[smp_processor_id()].hlt_works_ok)
1189 __asm__("hlt");
1190 }
1191 default:
1192 printk("CPU #%d sent invalid cross CPU message to CPU #%d: %X(%lX).\n",
1193 smp_src_cpu,smp_processor_id(),smp_msg_id,smp_msg_data);
1194 break;
1195 }
1196 /*
1197 * Clear the IPI, so we can receive future IPI's
1198 */
1199
1200 apic_read(APIC_SPIV); /* Dummy read */
1201 apic_write(APIC_EOI, 0); /* Docs say use 0 for future compatibility */
1202 }
![[bottom]](../icons/n_bottom.png){kind=icon}
*/