drivers/net/a2065.h

/* */
   1 /*
   2  * Amiga Linux/68k A2065 Ethernet Driver
   3  *
   4  * (C) Copyright 1995 by Geert Uytterhoeven
   5  *                      (Geert.Uytterhoeven@cs.kuleuven.ac.be)
   6  *
   7  * ---------------------------------------------------------------------------
   8  *
   9  * This program is based on
  10  *
  11  *      ariadne.?:      Amiga Linux/68k Ariadne Ethernet Driver
  12  *                      (C) Copyright 1995 by Geert Uytterhoeven,
  13  *                      Peter De Schrijver
  14  *
  15  *      lance.c:        An AMD LANCE ethernet driver for linux.
  16  *                      Written 1993-94 by Donald Becker.
  17  *
  18  *      Am79C960:       PCnet(tm)-ISA Single-Chip Ethernet Controller
  19  *                      Advanced Micro Devices
  20  *                      Publication #16907, Rev. B, Amendment/0, May 1994
  21  *
  22  * ---------------------------------------------------------------------------
  23  *
  24  * This file is subject to the terms and conditions of the GNU General Public
  25  * License.  See the file README.legal in the main directory of the Linux/68k
  26  * distribution for more details.
  27  *
  28  * ---------------------------------------------------------------------------
  29  *
  30  * The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains:
  31  *
  32  *      - an Am7990 Local Area Network Controller for Ethernet (LANCE) with
  33  *        both 10BASE-2 (thin coax) and AUI (DB-15) connectors
  34  */
  35 
  36 
  37 /*
  38  *              Am7990 Local Area Network Controller for Ethernet (LANCE)
  39  */
  40 
  41 struct Am7990 {
  42         volatile u_short RDP;           /* Register Data Port */
  43         volatile u_short RAP;           /* Register Address Port */
  44 };
  45 
  46 
  47 /*
  48  *              Am7990 Control and Status Registers
  49  */
  50 
  51 #define CSR0            0x0000          /* LANCE Controller Status */
  52 #define CSR1            0x0001          /* IADR[15:0] */
  53 #define CSR2            0x0002          /* IADR[23:16] */
  54 #define CSR3            0x0003          /* Misc */
  55 
  56 
  57 /*
  58  *              Bit definitions for CSR0 (LANCE Controller Status)
  59  */
  60 
  61 #define ERR             0x8000          /* Error */
  62 #define BABL            0x4000          /* Babble: Transmitted too many bits */
  63 #define CERR            0x2000          /* No Heartbeat (10BASE-T) */
  64 #define MISS            0x1000          /* Missed Frame */
  65 #define MERR            0x0800          /* Memory Error */
  66 #define RINT            0x0400          /* Receive Interrupt */
  67 #define TINT            0x0200          /* Transmit Interrupt */
  68 #define IDON            0x0100          /* Initialization Done */
  69 #define INTR            0x0080          /* Interrupt Flag */
  70 #define INEA            0x0040          /* Interrupt Enable */
  71 #define RXON            0x0020          /* Receive On */
  72 #define TXON            0x0010          /* Transmit On */
  73 #define TDMD            0x0008          /* Transmit Demand */
  74 #define STOP            0x0004          /* Stop */
  75 #define STRT            0x0002          /* Start */
  76 #define INIT            0x0001          /* Initialize */
  77 
  78 
  79 /*
  80  *              Bit definitions for CSR3
  81  */
  82 
  83 #define BSWP            0x0004          /* Byte Swap
  84                                            (on for big endian byte order) */
  85 #define ACON            0x0002          /* ALE Control
  86                                            (on for active low ALE) */
  87 #define BCON            0x0001          /* Byte Control */
  88 
  89 
  90 /*
  91  *              Initialization Block
  92  */
  93 
  94 struct InitBlock {
  95         u_short Mode;                   /* Mode */
  96         u_char PADR[6];                 /* Physical Address */
  97         u_long LADRF[2];                /* Logical Address Filter */
  98         u_short RDRA;                   /* Receive Descriptor Ring Address */
  99         u_short RLEN;                   /* Receive Descriptor Ring Length */
 100         u_short TDRA;                   /* Transmit Descriptor Ring Address */
 101         u_short TLEN;                   /* Transmit Descriptor Ring Length */
 102 };
 103 
 104 
 105 /*
 106  *              Mode Flags
 107  */
 108 
 109 #define PROM            0x8000          /* Promiscuous Mode */
 110 #define INTL            0x0040          /* Internal Loopback */
 111 #define DRTY            0x0020          /* Disable Retry */
 112 #define FCOLL           0x0010          /* Force Collision */
 113 #define DXMTFCS         0x0008          /* Disable Transmit CRC */
 114 #define LOOP            0x0004          /* Loopback Enable */
 115 #define DTX             0x0002          /* Disable Transmitter */
 116 #define DRX             0x0001          /* Disable Receiver */
 117 
 118 
 119 /*
 120  *              Receive Descriptor Ring Entry
 121  */
 122 
 123 struct RDRE {
 124         volatile u_short RMD0;          /* LADR[15:0] */
 125         volatile u_short RMD1;          /* HADR[23:16] | Receive Flags */
 126         volatile u_short RMD2;          /* Buffer Byte Count
 127                                            (two's complement) */
 128         volatile u_short RMD3;          /* Message Byte Count */
 129 };
 130 
 131 
 132 /*
 133  *              Transmit Descriptor Ring Entry
 134  */
 135 
 136 struct TDRE {
 137         volatile u_short TMD0;          /* LADR[15:0] */
 138         volatile u_short TMD1;          /* HADR[23:16] | Transmit Flags */
 139         volatile u_short TMD2;          /* Buffer Byte Count
 140                                            (two's complement) */
 141         volatile u_short TMD3;          /* Error Flags */
 142 };
 143 
 144 
 145 /*
 146  *              Receive Flags
 147  */
 148 
 149 #define RF_OWN          0x8000          /* LANCE owns the descriptor */
 150 #define RF_ERR          0x4000          /* Error */
 151 #define RF_FRAM         0x2000          /* Framing Error */
 152 #define RF_OFLO         0x1000          /* Overflow Error */
 153 #define RF_CRC          0x0800          /* CRC Error */
 154 #define RF_BUFF         0x0400          /* Buffer Error */
 155 #define RF_STP          0x0200          /* Start of Packet */
 156 #define RF_ENP          0x0100          /* End of Packet */
 157 
 158 
 159 /*
 160  *              Transmit Flags
 161  */
 162 
 163 #define TF_OWN          0x8000          /* LANCE owns the descriptor */
 164 #define TF_ERR          0x4000          /* Error */
 165 #define TF_RES          0x2000          /* Reserved,
 166                                            LANCE writes this with a zero */
 167 #define TF_MORE         0x1000          /* More than one retry needed */
 168 #define TF_ONE          0x0800          /* One retry needed */
 169 #define TF_DEF          0x0400          /* Deferred */
 170 #define TF_STP          0x0200          /* Start of Packet */
 171 #define TF_ENP          0x0100          /* End of Packet */
 172 
 173 
 174 /*
 175  *              Error Flags
 176  */
 177 
 178 #define EF_BUFF         0x8000          /* Buffer Error */
 179 #define EF_UFLO         0x4000          /* Underflow Error */
 180 #define EF_LCOL         0x1000          /* Late Collision */
 181 #define EF_LCAR         0x0800          /* Loss of Carrier */
 182 #define EF_RTRY         0x0400          /* Retry Error */
 183 #define EF_TDR          0x003f          /* Time Domain Reflectometry */
 184 
 185 
 186 /*
 187  *              A2065 Expansion Board Structure
 188  */
 189 
 190 struct A2065Board {
 191         u_char Pad1[0x4000];
 192         struct Am7990 Lance;
 193         u_char Pad2[0x3ffc];
 194         volatile u_char RAM[0x8000];
 195 };
/* */
root/drivers/net/a2065.h

INCLUDED FROM
