root/drivers/scsi/wd33c93.h

/* */

INCLUDED FROM

   1 #ifndef WD33C93_H
   2 #define WD33C93_H
   3 
   4 /*
   5  *    wd33c93.h -  Linux device driver definitions for the
   6  *                 Commodore Amiga A2091/590 SCSI controller card
   7  *
   8  * Copyright (c) 1996 John Shifflett, GeoLog Consulting
   9  *    john@geolog.com
  10  *    jshiffle@netcom.com
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2, or (at your option)
  15  * any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  */
  23 
  24 
  25 
  26 #define uchar unsigned char
  27 
  28 
  29 /* wd register names */
  30 #define WD_OWN_ID    0x00
  31 #define WD_CONTROL      0x01
  32 #define WD_TIMEOUT_PERIOD  0x02
  33 #define WD_CDB_1     0x03
  34 #define WD_CDB_2     0x04
  35 #define WD_CDB_3     0x05
  36 #define WD_CDB_4     0x06
  37 #define WD_CDB_5     0x07
  38 #define WD_CDB_6     0x08
  39 #define WD_CDB_7     0x09
  40 #define WD_CDB_8     0x0a
  41 #define WD_CDB_9     0x0b
  42 #define WD_CDB_10    0x0c
  43 #define WD_CDB_11    0x0d
  44 #define WD_CDB_12    0x0e
  45 #define WD_TARGET_LUN      0x0f
  46 #define WD_COMMAND_PHASE   0x10
  47 #define WD_SYNCHRONOUS_TRANSFER 0x11
  48 #define WD_TRANSFER_COUNT_MSB 0x12
  49 #define WD_TRANSFER_COUNT  0x13
  50 #define WD_TRANSFER_COUNT_LSB 0x14
  51 #define WD_DESTINATION_ID  0x15
  52 #define WD_SOURCE_ID    0x16
  53 #define WD_SCSI_STATUS     0x17
  54 #define WD_COMMAND      0x18
  55 #define WD_DATA      0x19
  56 #define WD_QUEUE_TAG    0x1a
  57 #define WD_AUXILIARY_STATUS   0x1f
  58 
  59 /* WD commands */
  60 #define WD_CMD_RESET    0x00
  61 #define WD_CMD_ABORT    0x01
  62 #define WD_CMD_ASSERT_ATN  0x02
  63 #define WD_CMD_NEGATE_ACK  0x03
  64 #define WD_CMD_DISCONNECT  0x04
  65 #define WD_CMD_RESELECT    0x05
  66 #define WD_CMD_SEL_ATN     0x06
  67 #define WD_CMD_SEL      0x07
  68 #define WD_CMD_SEL_ATN_XFER   0x08
  69 #define WD_CMD_SEL_XFER    0x09
  70 #define WD_CMD_RESEL_RECEIVE  0x0a
  71 #define WD_CMD_RESEL_SEND  0x0b
  72 #define WD_CMD_WAIT_SEL_RECEIVE 0x0c
  73 #define WD_CMD_TRANS_ADDR  0x18
  74 #define WD_CMD_TRANS_INFO  0x20
  75 #define WD_CMD_TRANSFER_PAD   0x21
  76 #define WD_CMD_SBT_MODE    0x80
  77 
  78 /* ASR register */
  79 #define ASR_INT         (0x80)
  80 #define ASR_LCI         (0x40)
  81 #define ASR_BSY         (0x20)
  82 #define ASR_CIP         (0x10)
  83 #define ASR_PE          (0x02)
  84 #define ASR_DBR         (0x01)
  85 
  86 /* SCSI Bus Phases */
  87 #define PHS_DATA_OUT    0x00
  88 #define PHS_DATA_IN     0x01
  89 #define PHS_COMMAND     0x02
  90 #define PHS_STATUS      0x03
  91 #define PHS_MESS_OUT    0x06
  92 #define PHS_MESS_IN     0x07
  93 
  94 /* Command Status Register definitions */
  95 
  96   /* reset state interrupts */
  97 #define CSR_RESET    0x00
  98 #define CSR_RESET_AF    0x01
  99 
 100   /* successful completion interrupts */
 101 #define CSR_RESELECT    0x10
 102 #define CSR_SELECT      0x11
 103 #define CSR_SEL_XFER_DONE  0x16
 104 #define CSR_XFER_DONE      0x18
 105 
 106   /* paused or aborted interrupts */
 107 #define CSR_MSGIN    0x20
 108 #define CSR_SDP         0x21
 109 #define CSR_SEL_ABORT      0x22
 110 #define CSR_RESEL_ABORT    0x25
 111 #define CSR_RESEL_ABORT_AM 0x27
 112 #define CSR_ABORT    0x28
 113 
 114   /* terminated interrupts */
 115 #define CSR_INVALID     0x40
 116 #define CSR_UNEXP_DISC     0x41
 117 #define CSR_TIMEOUT     0x42
 118 #define CSR_PARITY      0x43
 119 #define CSR_PARITY_ATN     0x44
 120 #define CSR_BAD_STATUS     0x45
 121 #define CSR_UNEXP    0x48
 122 
 123   /* service required interrupts */
 124 #define CSR_RESEL    0x80
 125 #define CSR_RESEL_AM    0x81
 126 #define CSR_DISC     0x85
 127 #define CSR_SRV_REQ     0x88
 128 
 129    /* Own ID/CDB Size register */
 130 #define OWNID_EAF    0x08
 131 #define OWNID_EHP    0x10
 132 #define OWNID_RAF    0x20
 133 #define OWNID_FS_8   0x00
 134 #define OWNID_FS_12  0x40
 135 #define OWNID_FS_16  0x80
 136 
 137    /* define these so we don't have to change a2091.c, etc. */
 138 #define WD33C93_FS_8_10  OWNID_FS_8
 139 #define WD33C93_FS_12_15 OWNID_FS_12
 140 #define WD33C93_FS_16_20 OWNID_FS_16
 141 
 142    /* Control register */
 143 #define CTRL_HSP     0x01
 144 #define CTRL_HA      0x02
 145 #define CTRL_IDI     0x04
 146 #define CTRL_EDI     0x08
 147 #define CTRL_HHP     0x10
 148 #define CTRL_POLLED  0x00
 149 #define CTRL_BURST   0x20
 150 #define CTRL_BUS     0x40
 151 #define CTRL_DMA     0x80
 152 
 153    /* Timeout Period register */
 154 #define TIMEOUT_PERIOD_VALUE  20    /* results in 200 ms. */
 155 
 156    /* Synchronous Transfer Register */
 157 #define STR_FSS      0x80
 158 
 159    /* Destination ID register */
 160 #define DSTID_DPD    0x40
 161 #define DATA_OUT_DIR 0
 162 #define DATA_IN_DIR  1
 163 #define DSTID_SCC    0x80
 164 
 165    /* Source ID register */
 166 #define SRCID_MASK   0x07
 167 #define SRCID_SIV    0x08
 168 #define SRCID_DSP    0x20
 169 #define SRCID_ES     0x40
 170 #define SRCID_ER     0x80
 171 
 172    /* This is what the 3393 chip looks like to us */
 173 typedef struct {
 174    volatile unsigned char   SASR;
 175    char                     pad;
 176    volatile unsigned char   SCMD;
 177 } wd33c93_regs;
 178 
 179 
 180 typedef int (*dma_setup_t) (Scsi_Cmnd *SCpnt, int dir_in);
 181 typedef void (*dma_stop_t) (struct Scsi_Host *instance, Scsi_Cmnd *SCpnt,
 182              int status);
 183 
 184 
 185 #define DEFAULT_SX_PER   500     /* (ns) fairly safe */
 186 #define DEFAULT_SX_OFF   0       /* aka async */
 187 
 188 #define OPTIMUM_SX_PER   252     /* (ns) best we can do (mult-of-4) */
 189 #define OPTIMUM_SX_OFF   12      /* size of wd3393 fifo */
 190 
 191 struct sx_period {
 192    unsigned int   period_ns;
 193    uchar          reg_value;
 194    };
 195 
 196 
 197 struct WD33C93_hostdata {
 198     struct Scsi_Host *next;
 199     wd33c93_regs     *regp;
 200     uchar            clock_freq;
 201     uchar            chip;             /* what kind of wd33c93? */
 202     uchar            microcode;        /* microcode rev if 'B' */
 203     int              dma_dir;          /* data transfer dir. */
 204     dma_setup_t      dma_setup;
 205     dma_stop_t       dma_stop;
 206     uchar            *dma_bounce_buffer;
 207     unsigned int     dma_bounce_len;
 208     volatile uchar   busy[8];          /* index = target, bit = lun */
 209     volatile Scsi_Cmnd *input_Q;       /* commands waiting to be started */
 210     volatile Scsi_Cmnd *selecting;     /* trying to select this command */
 211     volatile Scsi_Cmnd *connected;     /* currently connected command */
 212     volatile Scsi_Cmnd *disconnected_Q;/* commands waiting for reconnect */
 213     uchar            state;            /* what we are currently doing */
 214     uchar            dma;              /* current state of DMA (on/off) */
 215     uchar            level2;           /* extent to which Level-2 commands are used */
 216     unsigned int     args;             /* set from command-line argument */
 217     uchar            incoming_msg[8];  /* filled during message_in phase */
 218     int              incoming_ptr;     /* mainly used with EXTENDED messages */
 219     uchar            outgoing_msg[8];  /* send this during next message_out */
 220     int              outgoing_len;     /* length of outgoing message */
 221     uchar            sync_xfer[8];     /* sync_xfer reg settings per target */
 222     uchar            sync_stat[8];     /* status of sync negotiation per target */
 223     };
 224 
 225 
 226 /* defines for hostdata->chip */
 227 
 228 #define C_WD33C93       0
 229 #define C_WD33C93A      1
 230 #define C_WD33C93B      2
 231 #define C_UNKNOWN_CHIP  100
 232 
 233 /* defines for hostdata->state */
 234 
 235 #define S_UNCONNECTED         0
 236 #define S_SELECTING           1
 237 #define S_RUNNING_LEVEL2      2
 238 #define S_CONNECTED           3
 239 #define S_PRE_TMP_DISC        4
 240 #define S_PRE_CMP_DISC        5
 241 
 242 /* defines for hostdata->dma */
 243 
 244 #define D_DMA_OFF          0
 245 #define D_DMA_RUNNING      1
 246 
 247 /* defines for hostdata->level2 */
 248 /* NOTE: only the first 3 are implemented so far - having trouble
 249  * when more than 1 device is reading/writing at the same time...
 250  */
 251 
 252 #define L2_NONE      1  /* no combination commands - we get lots of ints */
 253 #define L2_SELECT    2  /* start with SEL_ATN_XFER, but never resume it */
 254 #define L2_BASIC     3  /* resume after STATUS ints & RDP messages */
 255 #define L2_DATA      4  /* resume after DATA_IN/OUT ints */
 256 #define L2_MOST      5  /* resume after anything except a RESELECT int */
 257 #define L2_RESELECT  6  /* resume after everything, including RESELECT ints */
 258 #define L2_ALL       7  /* always resume */
 259 #define L2_DEFAULT   L2_BASIC
 260 
 261 /* defines for hostdata->args */
 262 /*  (The first 8 bits are reserved for compatability. They function
 263  *   as they did in the old driver - note that turning off sync_xfer
 264  *   on a target affects all LUNs at that SCSI id.)
 265  */
 266 
 267 #define A_LEVEL2_0            1<<8
 268 #define A_LEVEL2_1            1<<9
 269 #define A_LEVEL2_2            1<<10
 270 #define A_NO_DISCONNECT       1<<11
 271 
 272 #define DB_QUEUE_COMMAND      1<<12
 273 #define DB_EXECUTE            1<<13
 274 #define DB_INTR               1<<14
 275 #define DB_TRANSFER_DATA      1<<15
 276 
 277 /* defines for hostdata->sync_stat[] */
 278 
 279 #define SS_UNSET     0
 280 #define SS_FIRST     1
 281 #define SS_WAITING   2
 282 #define SS_SET       3
 283 
 284 
 285 void wd33c93_init (struct Scsi_Host *instance, wd33c93_regs *regs,
 286          dma_setup_t setup, dma_stop_t stop, int clock_freq);
 287 int wd33c93_abort (Scsi_Cmnd *cmd);
 288 int wd33c93_reset (Scsi_Cmnd *);
 289 int wd33c93_queuecommand (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
 290 void wd33c93_intr (struct Scsi_Host *instance);
 291 
 292 #endif /* WD33C93_H */

/* */