arch/ppc/mm/mmu.h

/* */
   1 /*
   2  * PowerPC memory management structures
   3  */
   4 
   5 #ifndef _PPC_MMU_H_
   6 #define _PPC_MMU_H_
   7 
   8 /* Hardware Page Table Entry */
   9  
  10 typedef struct _PTE
  11    {
  12       unsigned long v:1;        /* Entry is valid */
  13       unsigned long vsid:24;    /* Virtual segment identifier */
  14       unsigned long h:1;        /* Hash algorithm indicator */
  15       unsigned long api:6;      /* Abbreviated page index */
  16       unsigned long rpn:20;     /* Real (physical) page number */
  17       unsigned long    :3;      /* Unused */
  18       unsigned long r:1;        /* Referenced */
  19       unsigned long c:1;        /* Changed */
  20       unsigned long w:1;        /* Write-thru cache mode */
  21       unsigned long i:1;        /* Cache inhibited */
  22       unsigned long m:1;        /* Memory coherence */
  23       unsigned long g:1;        /* Guarded */
  24       unsigned long    :1;      /* Unused */
  25       unsigned long pp:2;       /* Page protection */
  26    } PTE; 
  27 
  28 /* Values for PP (assumes Ks=0, Kp=1) */
  29 #define PP_RWXX 0       /* Supervisor read/write, User none */
  30 #define PP_RWRX 1       /* Supervisor read/write, User read */
  31 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  32 
  33 /* Segment Register */
  34 
  35 typedef struct _SEGREG
  36    {
  37       unsigned long t:1;        /* Normal or I/O  type */
  38       unsigned long ks:1;       /* Supervisor 'key' (normally 0) */
  39       unsigned long kp:1;       /* User 'key' (normally 1) */
  40       unsigned long n:1;        /* No-execute */
  41       unsigned long :4;         /* Unused */
  42       unsigned long vsid:24;    /* Virtual Segment Identifier */
  43    } SEGREG;
  44 
  45 /* Block Address Translation (BAT) Registers */
  46 
  47 typedef struct _BATU            /* Upper part of BAT */
  48    {
  49       unsigned long bepi:15;    /* Effective page index (virtual address) */
  50       unsigned long :4;         /* Unused */
  51       unsigned long bl:11;      /* Block size mask */
  52       unsigned long vs:1;       /* Supervisor valid */
  53       unsigned long vp:1;       /* User valid */
  54    } BATU;   
  55 
  56 typedef struct _BATL            /* Lower part of BAT */
  57    {
  58       unsigned long brpn:15;    /* Real page index (physical address) */
  59       unsigned long :10;        /* Unused */
  60       unsigned long w:1;        /* Write-thru cache */
  61       unsigned long i:1;        /* Cache inhibit */
  62       unsigned long m:1;        /* Memory coherence */
  63       unsigned long g:1;        /* Guarded (MBZ) */
  64       unsigned long :1;         /* Unused */
  65       unsigned long pp:2;       /* Page access protections */
  66    } BATL;
  67 
  68 typedef struct _BAT
  69    {
  70       BATU batu;                /* Upper register */
  71       BATL batl;                /* Lower register */
  72    } BAT;
  73 
  74 /* Block size masks */
  75 #define BL_128K 0x000
  76 #define BL_256K 0x001
  77 #define BL_512K 0x003
  78 #define BL_1M   0x007
  79 #define BL_2M   0x00F
  80 #define BL_4M   0x01F
  81 #define BL_8M   0x03F
  82 #define BL_16M  0x07F
  83 #define BL_32M  0x0FF
  84 #define BL_64M  0x1FF
  85 #define BL_128M 0x3FF
  86 #define BL_256M 0x7FF
  87 
  88 /* BAT Access Protection */
  89 #define BPP_XX  0x00            /* No access */
  90 #define BPP_RX  0x01            /* Read only */
  91 #define BPP_RW  0x02            /* Read/write */
  92 
  93 /*
  94  * Simulated two-level MMU.  This structure is used by the kernel
  95  * to keep track of MMU mappings and is used to update/maintain
  96  * the hardware HASH table which is really a cache of mappings.
  97  *
  98  * The simulated structures mimic the hardware available on other
  99  * platforms, notably the 80x86 and 680x0.
 100  */
 101 
 102 typedef struct _pte
 103    {
 104         unsigned long page_num:20;
 105         unsigned long unused:6;
 106         unsigned long acc:3;            /* Read/write/execute permissions */
 107         unsigned long r:1;              /* Page has been referenced */
 108         unsigned long m:1;              /* Page has been modified */
 109         unsigned long v:1;              /* Entry is valid */
 110    } pte;
 111 
 112 #define ACC_Rxx 0x04
 113 #define ACC_xWx 0x02
 114 #define ACC_xxX 0x01
 115 #define ACC_RWX (ACC_Rxx|ACC_xWx|ACC_xxX)
 116 
 117 #define PD_SHIFT (10+12)                /* Page directory */
 118 #define PD_MASK  0x02FF
 119 #define PT_SHIFT (12)                   /* Page Table */
 120 #define PT_MASK  0x02FF
 121 #define PG_SHIFT (12)                   /* Page Entry */
 122  
 123 
 124 /* MMU context */
 125 
 126 typedef struct _MMU_context
 127    {
 128       SEGREG    segs[16];       /* Segment registers */
 129       pte       **pmap;         /* Two-level page-map structure */
 130    } MMU_context;
 131 
 132 #if 0
 133 BAT     ibat[4];        /* Instruction BAT images */
 134 BAT     dbat[4];        /* Data BAT images */
 135 PTE     *hash_table;    /* Hardware hashed page table */
 136 int     hash_table_size;
 137 int     hash_table_mask;
 138 unsigned long sdr;      /* Hardware image of SDR */
 139 #endif   
 140 
 141 /* Used to set up SDR register */
 142 #define HASH_TABLE_SIZE_64K     0x00010000
 143 #define HASH_TABLE_SIZE_128K    0x00020000
 144 #define HASH_TABLE_SIZE_256K    0x00040000
 145 #define HASH_TABLE_SIZE_512K    0x00080000
 146 #define HASH_TABLE_SIZE_1M      0x00100000
 147 #define HASH_TABLE_SIZE_2M      0x00200000
 148 #define HASH_TABLE_SIZE_4M      0x00400000
 149 #define HASH_TABLE_MASK_64K     0x000   
 150 #define HASH_TABLE_MASK_128K    0x001   
 151 #define HASH_TABLE_MASK_256K    0x003   
 152 #define HASH_TABLE_MASK_512K    0x007
 153 #define HASH_TABLE_MASK_1M      0x00F   
 154 #define HASH_TABLE_MASK_2M      0x01F   
 155 #define HASH_TABLE_MASK_4M      0x03F   
 156 
 157 #define MMU_PAGE_SIZE   4096
 158 
 159 #endif
/* */
root/arch/ppc/mm/mmu.h

INCLUDED FROM
