include/asm-m68k/traps.h

/* */
   1 /*
   2  *  linux/include/asm/traps.h
   3  *
   4  *  Copyright (C) 1993        Hamish Macdonald
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file README.legal in the main directory of this archive
   8  * for more details.
   9  */
  10 
  11 #ifndef _M68K_TRAPS_H
  12 #define _M68K_TRAPS_H
  13 
  14 typedef void (*e_vector)(void);
  15 
  16 extern e_vector vectors[];
  17 
  18 #define VEC_BUSERR  (2)
  19 #define VEC_ADDRERR (3)
  20 #define VEC_ILLEGAL (4)
  21 #define VEC_ZERODIV (5)
  22 #define VEC_CHK     (6)
  23 #define VEC_TRAP    (7)
  24 #define VEC_PRIV    (8)
  25 #define VEC_TRACE   (9)
  26 #define VEC_LINE10  (10)
  27 #define VEC_LINE11  (11)
  28 #define VEC_RESV1   (12)
  29 #define VEC_COPROC  (13)
  30 #define VEC_FORMAT  (14)
  31 #define VEC_UNINT   (15)
  32 #define VEC_SPUR    (24)
  33 #define VEC_INT1    (25)
  34 #define VEC_INT2    (26)
  35 #define VEC_INT3    (27)
  36 #define VEC_INT4    (28)
  37 #define VEC_INT5    (29)
  38 #define VEC_INT6    (30)
  39 #define VEC_INT7    (31)
  40 #define VEC_SYS     (32)
  41 #define VEC_TRAP1   (33)
  42 #define VEC_TRAP2   (34)
  43 #define VEC_TRAP3   (35)
  44 #define VEC_TRAP4   (36)
  45 #define VEC_TRAP5   (37)
  46 #define VEC_TRAP6   (38)
  47 #define VEC_TRAP7   (39)
  48 #define VEC_TRAP8   (40)
  49 #define VEC_TRAP9   (41)
  50 #define VEC_TRAP10  (42)
  51 #define VEC_TRAP11  (43)
  52 #define VEC_TRAP12  (44)
  53 #define VEC_TRAP13  (45)
  54 #define VEC_TRAP14  (46)
  55 #define VEC_TRAP15  (47)
  56 #define VEC_FPBRUC  (48)
  57 #define VEC_FPIR    (49)
  58 #define VEC_FPDIVZ  (50)
  59 #define VEC_FPUNDER (51)
  60 #define VEC_FPOE    (52)
  61 #define VEC_FPOVER  (53)
  62 #define VEC_FPNAN   (54)
  63 #define VEC_FPUNSUP (55)
  64 #define VEC_UNIMPEA (60)
  65 #define VEC_UNIMPII (61)
  66 
  67 #define VECOFF(vec) ((vec)<<2)
  68 
  69 /* Status register bits */
  70 #define PS_T  (0x8000)
  71 #define PS_S  (0x2000)
  72 #define PS_M  (0x1000)
  73 #define PS_C  (0x0001)
  74 
  75 /* bits for 68020/68030 special status word */
  76 
  77 #define FC    (0x8000)
  78 #define FB    (0x4000)
  79 #define RC    (0x2000)
  80 #define RB    (0x1000)
  81 #define DF    (0x0100)
  82 #define RM    (0x0080)
  83 #define RW    (0x0040)
  84 #define SZ    (0x0030)
  85 #define DFC   (0x0007)
  86 
  87 /* bits for 68030 MMU status register (mmusr,psr) */
  88 
  89 #define MMU_B        (0x8000)    /* bus error */
  90 #define MMU_L        (0x4000)    /* limit violation */
  91 #define MMU_S        (0x2000)    /* supervisor violation */
  92 #define MMU_WP       (0x0800)    /* write-protected */
  93 #define MMU_I        (0x0400)    /* invalid descriptor */
  94 #define MMU_M        (0x0200)    /* ATC entry modified */
  95 #define MMU_T        (0x0040)    /* transparent translation */
  96 #define MMU_NUM      (0x0007)    /* number of levels traversed */
  97 
  98 
  99 /* bits for 68040 special status word */
 100 #define CP_040  (0x8000)
 101 #define CU_040  (0x4000)
 102 #define CT_040  (0x2000)
 103 #define CM_040  (0x1000)
 104 #define MA_040  (0x0800)
 105 #define ATC_040 (0x0400)
 106 #define LK_040  (0x0200)
 107 #define RW_040  (0x0100)
 108 #define SIZ_040 (0x0060)
 109 #define TT_040  (0x0018)
 110 #define TM_040  (0x0007)
 111 
 112 /* bits for 68040 write back status word */
 113 #define WBV_040   (0x80)
 114 #define WBSIZ_040 (0x60)
 115 #define WBBYT_040 (0x20)
 116 #define WBWRD_040 (0x40)
 117 #define WBLNG_040 (0x00)
 118 #define WBTT_040  (0x18)
 119 #define WBTM_040  (0x07)
 120 
 121 /* bus access size codes */
 122 #define BA_SIZE_BYTE    (0x20)
 123 #define BA_SIZE_WORD    (0x40)
 124 #define BA_SIZE_LONG    (0x00)
 125 #define BA_SIZE_LINE    (0x60)
 126 
 127 /* bus access transfer type codes */
 128 #define BA_TT_MOVE16    (0x08)
 129 
 130 /* bits for 68040 MMU status register (mmusr) */
 131 #define MMU_B_040   (0x0800)
 132 #define MMU_G_040   (0x0400)
 133 #define MMU_S_040   (0x0080)
 134 #define MMU_CM_040  (0x0060)
 135 #define MMU_M_040   (0x0010)
 136 #define MMU_WP_040  (0x0004)
 137 #define MMU_T_040   (0x0002)
 138 #define MMU_R_040   (0x0001)
 139 
 140 /* bits in the 68060 fault status long word (FSLW) */
 141 #define MMU060_MA       (0x08000000)    /* misaligned */
 142 #define MMU060_LK       (0x02000000)    /* locked transfer */
 143 #define MMU060_RW       (0x01800000)    /* read/write */
 144 # define MMU060_RW_W    (0x00800000)    /* write */
 145 # define MMU060_RW_R    (0x01000000)    /* read */
 146 # define MMU060_RW_RMW  (0x01800000)    /* read/modify/write */
 147 # define MMU060_W               (0x00800000)    /* general write, includes rmw */
 148 #define MMU060_SIZ      (0x00600000)    /* transfer size */
 149 #define MMU060_TT       (0x00180000)    /* transfer type (TT) bits */
 150 #define MMU060_TM       (0x00070000)    /* transfer modifier (TM) bits */
 151 #define MMU060_IO       (0x00008000)    /* intruction or operand */
 152 #define MMU060_PBE      (0x00004000)    /* push buffer bus error */
 153 #define MMU060_SBE      (0x00002000)    /* store buffer bus error */
 154 #define MMU060_PTA      (0x00001000)    /* pointer A fault */
 155 #define MMU060_PTB      (0x00000800)    /* pointer B fault */
 156 #define MMU060_IL       (0x00000400)    /* double indirect descr fault */
 157 #define MMU060_PF       (0x00000200)    /* page fault (invalid descr) */
 158 #define MMU060_SP       (0x00000100)    /* supervisor protection */
 159 #define MMU060_WP       (0x00000080)    /* write protection */
 160 #define MMU060_TWE      (0x00000040)    /* bus error on table search */
 161 #define MMU060_RE       (0x00000020)    /* bus error on read */
 162 #define MMU060_WE       (0x00000010)    /* bus error on write */
 163 #define MMU060_TTR      (0x00000008)    /* error caused by TTR translation */
 164 #define MMU060_BPE      (0x00000004)    /* branch prediction error */
 165 #define MMU060_SEE      (0x00000001)    /* software emulated error */
 166 
 167 /* cases of missing or invalid descriptors */
 168 #define MMU060_DESC_ERR (MMU060_TWE | MMU060_PTA | MMU060_PTB | \
 169                                                  MMU060_IL  | MMU060_PF)
 170 /* bits that indicate real errors */
 171 #define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | \
 172                                                  MMU060_SP  | MMU060_WP  | MMU060_RE | \
 173                                                  MMU060_WE)
 174 
 175 /* structure for stack frames */
 176 
 177 struct frame {
 178     struct pt_regs ptregs;
 179     union {
 180             struct {
 181                     unsigned long  iaddr;    /* instruction address */
 182             } fmt2;
 183             struct {
 184                     unsigned long  effaddr;  /* effective address */
 185             } fmt3;
 186             struct {
 187                     unsigned long  effaddr;  /* effective address */
 188                     unsigned long  pc;       /* pc of faulted instr */
 189             } fmt4;
 190             struct {
 191                     unsigned long  effaddr;  /* effective address */
 192                     unsigned short ssw;      /* special status word */
 193                     unsigned short wb3s;     /* write back 3 status */
 194                     unsigned short wb2s;     /* write back 2 status */
 195                     unsigned short wb1s;     /* write back 1 status */
 196                     unsigned long  faddr;    /* fault address */
 197                     unsigned long  wb3a;     /* write back 3 address */
 198                     unsigned long  wb3d;     /* write back 3 data */
 199                     unsigned long  wb2a;     /* write back 2 address */
 200                     unsigned long  wb2d;     /* write back 2 data */
 201                     unsigned long  wb1a;     /* write back 1 address */
 202                     unsigned long  wb1dpd0;  /* write back 1 data/push data 0*/
 203                     unsigned long  pd1;      /* push data 1*/
 204                     unsigned long  pd2;      /* push data 2*/
 205                     unsigned long  pd3;      /* push data 3*/
 206             } fmt7;
 207             struct {
 208                     unsigned long  iaddr;    /* instruction address */
 209                     unsigned short int1[4];  /* internal registers */
 210             } fmt9;
 211             struct {
 212                     unsigned short int1;
 213                     unsigned short ssw;      /* special status word */
 214                     unsigned short isc;      /* instruction stage c */
 215                     unsigned short isb;      /* instruction stage b */
 216                     unsigned long  daddr;    /* data cycle fault address */
 217                     unsigned short int2[2];
 218                     unsigned long  dobuf;    /* data cycle output buffer */
 219                     unsigned short int3[2];
 220             } fmta;
 221             struct {
 222                     unsigned short int1;
 223                     unsigned short ssw;     /* special status word */
 224                     unsigned short isc;     /* instruction stage c */
 225                     unsigned short isb;     /* instruction stage b */
 226                     unsigned long  daddr;   /* data cycle fault address */
 227                     unsigned short int2[2];
 228                     unsigned long  dobuf;   /* data cycle output buffer */
 229                     unsigned short int3[4];
 230                     unsigned long  baddr;   /* stage B address */
 231                     unsigned short int4[2];
 232                     unsigned long  dibuf;   /* data cycle input buffer */
 233                     unsigned short int5[3];
 234                     unsigned       ver : 4; /* stack frame version # */
 235                     unsigned       int6:12;
 236                     unsigned short int7[18];
 237             } fmtb;
 238     } un;
 239 };
 240 
 241 #endif /* _M68K_TRAPS_H */
/* */
root/include/asm-m68k/traps.h

INCLUDED FROM
