root/drivers/net/dgrs_driver.c

/* [previous][next][first][last][top][bottom][index][help] */

DEFINITIONS

This source file includes following definitions.
  1. proc_reset
  2. check_board_dma
  3. do_plx_dma
  4. dgrs_rcv_frame
  5. dgrs_start_xmit
  6. dgrs_open
  7. dgrs_close
  8. dgrs_get_stats
  9. dgrs_set_multicast_list
  10. dgrs_ioctl
  11. dgrs_intr
  12. dgrs_download
  13. dgrs_probe1
  14. dgrs_found_device
  15. dgrs_scan
  16. init_module
  17. cleanup_module
  18. dgrs_probe

   1 /*
   2  *      Digi RightSwitch SE-X loadable device driver for Linux
   3  *
   4  *      The RightSwitch is a 4 (EISA) or 6 (PCI) port etherswitch and
   5  *      a NIC on an internal board.
   6  *
   7  *      Author: Rick Richardson, rick@dgii.com, rick_richardson@dgii.com
   8  *      Derived from the SVR4.2 (UnixWare) driver for the same card.
   9  *
  10  *      Copyright 1995-1996 Digi International Inc.
  11  *
  12  *      This software may be used and distributed according to the terms
  13  *      of the GNU General Public License, incorporated herein by reference.
  14  *
  15  *      For information on purchasing a RightSwitch SE-4 or SE-6
  16  *      board, please contact Digi's sales department at 1-612-912-3444
  17  *      or 1-800-DIGIBRD.  Outside the U.S., please check our Web page
  18  *      at http://www.dgii.com for sales offices worldwide.
  19  *
  20  */
  21 
  22 static char *version = "$Id: dgrs.c,v 1.8 1996/04/18 03:11:14 rick Exp $";
  23 
  24 #include <linux/module.h>
  25 
  26 #include <linux/kernel.h>
  27 #include <linux/sched.h>
  28 #include <linux/string.h>
  29 #include <linux/delay.h>
  30 #include <linux/errno.h>
  31 #include <linux/ioport.h>
  32 #include <linux/malloc.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/pci.h>
  35 #include <linux/bios32.h>
  36 #include <asm/bitops.h>
  37 #include <asm/io.h>
  38 #include <asm/byteorder.h>
  39 
  40 #include <linux/netdevice.h>
  41 #include <linux/etherdevice.h>
  42 #include <linux/skbuff.h>
  43 
  44 #include <linux/types.h>
  45 
  46 /*
  47  *      DGRS include files
  48  */
  49 typedef unsigned char uchar;
  50 typedef unsigned int bool;
  51 #define vol volatile
  52 
  53 #include "dgrs.h"
  54 #include "dgrs_es4h.h"
  55 #include "dgrs_plx9060.h"
  56 #include "dgrs_i82596.h"
  57 #include "dgrs_ether.h"
  58 #include "dgrs_asstruct.h"
  59 #include "dgrs_bcomm.h"
  60 
  61 /*
  62  *      Firmware.  Compiled separately for local compilation,
  63  *      but #included for Linux distribution.
  64  */
  65 #ifndef NOFW
  66         #include "dgrs_firmware.c"
  67 #else
  68         extern int      dgrs_firmnum;
  69         extern char     dgrs_firmver[];
  70         extern char     dgrs_firmdate[];
  71         extern uchar    dgrs_code[];
  72         extern int      dgrs_ncode;
  73 #endif
  74 
  75 /*
  76  *      Linux out*() is backwards from all other operating systems
  77  */
  78 #define OUTB(ADDR, VAL) outb(VAL, ADDR)
  79 #define OUTW(ADDR, VAL) outw(VAL, ADDR)
  80 #define OUTL(ADDR, VAL) outl(VAL, ADDR)
  81 
  82 /*
  83  *      Macros to convert switch to host and host to switch addresses
  84  *      (assumes a local variable priv points to board dependent struct)
  85  */
  86 #define S2H(A)  ( ((unsigned long)(A)&0x00ffffff) + priv->vmem )
  87 #define H2S(A)  ( ((char *) (A) - priv->vmem) + 0xA3000000 )
  88 
  89 /*
  90  *      Convert a switch address to a "safe" address for use with the
  91  *      PLX 9060 DMA registers and the associated HW kludge that allows
  92  *      for host access of the DMA registers.
  93  */
  94 #define S2DMA(A)        ( (unsigned long)(A) & 0x00ffffff)
  95 
  96 /*
  97  *      "Space.c" variables, now settable from module interface
  98  *      Use the name below, minus the "dgrs_" prefix.  See init_module().
  99  */
 100 int     dgrs_debug = 1;
 101 int     dgrs_dma = 1;
 102 int     dgrs_spantree = -1;
 103 int     dgrs_hashexpire = -1;
 104 uchar   dgrs_ipaddr[4] = { 0xff, 0xff, 0xff, 0xff};
 105 long    dgrs_ipxnet = -1;
 106 
 107 /*
 108  *      Chain of device structures
 109  */
 110 #ifdef MODULE
 111         static struct device *dgrs_root_dev = NULL;
 112 #endif
 113 
 114 /*
 115  *      Private per-board data structure (dev->priv)
 116  */
 117 typedef struct
 118 {
 119         /*
 120          *      Stuff for generic ethercard I/F
 121          */
 122         char                    devname[8];     /* "ethN" string */
 123         struct device           *next_dev;
 124         struct enet_statistics  stats;
 125 
 126         /*
 127          *      DGRS specific data
 128          */
 129         char            *vmem;
 130 
 131         struct bios_comm *bcomm;        /* Firmware BIOS comm structure */
 132         PORT            *port;          /* Ptr to PORT[0] struct in VM */
 133         I596_SCB        *scbp;          /* Ptr to SCB struct in VM */
 134         I596_RFD        *rfdp;          /* Current RFD list */
 135         I596_RBD        *rbdp;          /* Current RBD list */
 136 
 137         int             intrcnt;        /* Count of interrupts */
 138 
 139         /*
 140          *      SE-4 (EISA) board variables
 141          */
 142         uchar           is_reg;         /* EISA: Value for ES4H_IS reg */
 143 
 144         /*
 145          *      SE-6 (PCI) board variables
 146          *
 147          *      The PLX "expansion rom" space is used for DMA register
 148          *      access from the host on the SE-6.  These are the physical
 149          *      and virtual addresses of that space.
 150          */
 151         ulong           plxreg;         /* Phys address of PLX chip */
 152         char            *vplxreg;       /* Virtual address of PLX chip */
 153         ulong           plxdma;         /* Phys addr of PLX "expansion rom" */
 154         ulong volatile  *vplxdma;       /* Virtual addr of "expansion rom" */
 155         int             use_dma;        /* Flag: use DMA */
 156         DMACHAIN        *dmadesc_s;     /* area for DMA chains (SW addr.) */
 157         DMACHAIN        *dmadesc_h;     /* area for DMA chains (Host Virtual) */
 158 
 159 } DGRS_PRIV;
 160 
 161 
 162 /*
 163  *      reset or un-reset the IDT processor
 164  */
 165 static void
 166 proc_reset(struct device *dev, int reset)
     /* [previous][next][first][last][top][bottom][index][help] */
 167 {
 168         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 169 
 170         if (priv->plxreg)
 171         {
 172                 ulong           val;
 173                 val = inl(dev->base_addr + PLX_MISC_CSR);
 174                 if (reset)
 175                         val |= SE6_RESET;
 176                 else
 177                         val &= ~SE6_RESET;
 178                 OUTL(dev->base_addr + PLX_MISC_CSR, val);
 179         }
 180         else
 181         {
 182                 OUTB(dev->base_addr + ES4H_PC, reset ? ES4H_PC_RESET : 0);
 183         }
 184 }
 185 
 186 /*
 187  *      See if the board supports bus master DMA
 188  */
 189 static int
 190 check_board_dma(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
 191 {
 192         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 193         ulong   x;
 194 
 195         /*
 196          *      If Space.c says not to use DMA, or if its not a PLX based
 197          *      PCI board, or if the expansion ROM space is not PCI
 198          *      configured, then return false.
 199          */
 200         if (!dgrs_dma || !priv->plxreg || !priv->plxdma)
 201                 return (0);
 202 
 203         /*
 204          *      Set the local address remap register of the "expansion rom"
 205          *      area to 0x80000000 so that we can use it to access the DMA
 206          *      registers from the host side.
 207          */
 208         OUTL(dev->base_addr + PLX_ROM_BASE_ADDR, 0x80000000);
 209 
 210         /*
 211          * Set the PCI region descriptor to:
 212          *      Space 0:
 213          *              disable read-prefetch
 214          *              enable READY
 215          *              enable BURST
 216          *              0 internal wait states
 217          *      Expansion ROM: (used for host DMA register access)
 218          *              disable read-prefetch
 219          *              enable READY
 220          *              disable BURST
 221          *              0 internal wait states
 222          */
 223         OUTL(dev->base_addr + PLX_BUS_REGION, 0x49430343);
 224 
 225         /*
 226          *      Now map the DMA registers into our virtual space
 227          */
 228         priv->vplxdma = (ulong *) vremap (priv->plxdma, 256);
 229         if (!priv->vplxdma)
 230         {
 231                 printk("%s: can't vremap() the DMA regs", dev->name);
 232                 return (0);
 233         }
 234 
 235         /*
 236          *      Now test to see if we can access the DMA registers
 237          *      If we write -1 and get back 1FFF, then we accessed the
 238          *      DMA register.  Otherwise, we probably have an old board
 239          *      and wrote into regular RAM.
 240          */
 241         priv->vplxdma[PLX_DMA0_MODE/4] = 0xFFFFFFFF;
 242         x = priv->vplxdma[PLX_DMA0_MODE/4];
 243         if (x != 0x00001FFF)
 244                 return (0);
 245 
 246         return (1);
 247 }
 248 
 249 /*
 250  *      Initiate DMA using PLX part on PCI board.  Spin the
 251  *      processor until completed.  All addresses are physical!
 252  *
 253  *      If pciaddr is NULL, then its a chaining DMA, and lcladdr is
 254  *      the address of the first DMA descriptor in the chain.
 255  *
 256  *      If pciaddr is not NULL, then its a single DMA.
 257  *
 258  *      In either case, "lcladdr" must have been fixed up to make
 259  *      sure the MSB isn't set using the S2DMA macro before passing
 260  *      the address to this routine.
 261  */
 262 static int
 263 do_plx_dma(
     /* [previous][next][first][last][top][bottom][index][help] */
 264         struct device *dev,
 265         ulong pciaddr,
 266         ulong lcladdr,
 267         int len,
 268         int to_host
 269 )
 270 {
 271         int             i;
 272         ulong           csr;
 273         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 274 
 275         if (pciaddr)
 276         {
 277                 /*
 278                  *      Do a single, non-chain DMA
 279                  */
 280                 priv->vplxdma[PLX_DMA0_PCI_ADDR/4] = pciaddr;
 281                 priv->vplxdma[PLX_DMA0_LCL_ADDR/4] = lcladdr;
 282                 priv->vplxdma[PLX_DMA0_SIZE/4] = len;
 283                 priv->vplxdma[PLX_DMA0_DESCRIPTOR/4] = to_host
 284                                         ? PLX_DMA_DESC_TO_HOST
 285                                         : PLX_DMA_DESC_TO_BOARD;
 286                 priv->vplxdma[PLX_DMA0_MODE/4] =
 287                                           PLX_DMA_MODE_WIDTH32
 288                                         | PLX_DMA_MODE_WAITSTATES(0)
 289                                         | PLX_DMA_MODE_READY
 290                                         | PLX_DMA_MODE_NOBTERM
 291                                         | PLX_DMA_MODE_BURST
 292                                         | PLX_DMA_MODE_NOCHAIN;
 293         }
 294         else
 295         {
 296                 /*
 297                  *      Do a chaining DMA
 298                  */
 299                 priv->vplxdma[PLX_DMA0_MODE/4] =
 300                                           PLX_DMA_MODE_WIDTH32
 301                                         | PLX_DMA_MODE_WAITSTATES(0)
 302                                         | PLX_DMA_MODE_READY
 303                                         | PLX_DMA_MODE_NOBTERM
 304                                         | PLX_DMA_MODE_BURST
 305                                         | PLX_DMA_MODE_CHAIN;
 306                 priv->vplxdma[PLX_DMA0_DESCRIPTOR/4] = lcladdr;
 307         }
 308 
 309         priv->vplxdma[PLX_DMA_CSR/4] =
 310                                 PLX_DMA_CSR_0_ENABLE | PLX_DMA_CSR_0_START;
 311 
 312         /*
 313          *      Wait for DMA to complete
 314          */
 315         for (i = 0; i < 1000000; ++i)
 316         {
 317                 /*
 318                  *      Spin the host CPU for 1 usec, so we don't thrash
 319                  *      the PCI bus while the PLX 9060 is doing DMA.
 320                  */
 321                 udelay(1);
 322 
 323                 csr = (volatile) priv->vplxdma[PLX_DMA_CSR/4];
 324 
 325                 if (csr & PLX_DMA_CSR_0_DONE)
 326                         break;
 327         }
 328 
 329         if ( ! (csr & PLX_DMA_CSR_0_DONE) )
 330         {
 331                 printk("%s: DMA done never occurred. DMA disabled.", dev->name);
 332                 priv->use_dma = 0;
 333                 return 1;
 334         }
 335         return 0;
 336 }
 337 
 338 /*
 339  *      Process a received frame
 340  */
 341 void
 342 dgrs_rcv_frame(
     /* [previous][next][first][last][top][bottom][index][help] */
 343         struct device   *dev,
 344         DGRS_PRIV       *priv,
 345         I596_CB         *cbp
 346 )
 347 {
 348         int             len;
 349         I596_TBD        *tbdp;
 350         struct sk_buff  *skb;
 351         uchar           *putp;
 352         uchar           *p;
 353 
 354         if (0) printk("%s: rcv len=%ld", dev->name, cbp->xmit.count);
 355 
 356         /*
 357          *      Allocate a message block big enough to hold the whole frame
 358          */
 359         len = cbp->xmit.count;
 360         if ((skb = dev_alloc_skb(len+5)) == NULL)
 361         {
 362                 printk("%s: dev_alloc_skb failed for rcv buffer", dev->name);
 363                 ++priv->stats.rx_dropped;
 364                 /* discarding the frame */
 365                 goto out;
 366         }
 367         skb->dev = dev;
 368         skb_reserve(skb, 2);    /* Align IP header */
 369 
 370 again:
 371         putp = p = skb_put(skb, len);
 372 
 373         /*
 374          *      There are three modes here for doing the packet copy.
 375          *      If we have DMA, and the packet is "long", we use the
 376          *      chaining mode of DMA.  If its shorter, we use single
 377          *      DMA's.  Otherwise, we use memcpy().
 378          */
 379         if (priv->use_dma && priv->dmadesc_h && len > 64)
 380         {
 381                 /*
 382                  *      If we can use DMA and its a long frame, copy it using
 383                  *      DMA chaining.
 384                  */
 385                 DMACHAIN        *ddp_h; /* Host virtual DMA desc. pointer */
 386                 DMACHAIN        *ddp_s; /* Switch physical DMA desc. pointer */
 387                 uchar           *phys_p;
 388 
 389                 /*
 390                  *      Get the physical address of the STREAMS buffer.
 391                  *      NOTE: allocb() guarantees that the whole buffer
 392                  *      is in a single page if the length < 4096.
 393                  */
 394                 phys_p = (uchar *) virt_to_phys(putp);
 395 
 396                 ddp_h = priv->dmadesc_h;
 397                 ddp_s = priv->dmadesc_s;
 398                 tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
 399                 for (;;)
 400                 {
 401                         int     count;
 402                         int     amt;
 403 
 404                         count = tbdp->count;
 405                         amt = count & 0x3fff;
 406                         if (amt == 0)
 407                                 break; /* For safety */
 408                         if ( (p-putp) >= len)
 409                         {
 410                                 printk("%s: cbp = %x", dev->name, H2S(cbp));
 411                                 proc_reset(dev, 1);     /* Freeze IDT */
 412                                 break; /* For Safety */
 413                         }
 414 
 415                         ddp_h->pciaddr = (ulong) phys_p;
 416                         ddp_h->lcladdr = S2DMA(tbdp->buf);
 417                         ddp_h->len = amt;
 418 
 419                         phys_p += amt;
 420                         p += amt;
 421 
 422                         if (count & I596_TBD_EOF)
 423                         {
 424                                 ddp_h->next = PLX_DMA_DESC_TO_HOST
 425                                                 | PLX_DMA_DESC_EOC;
 426                                 ++ddp_h;
 427                                 break;
 428                         }
 429                         else
 430                         {
 431                                 ++ddp_s;
 432                                 ddp_h->next = PLX_DMA_DESC_TO_HOST
 433                                                 | (ulong) ddp_s;
 434                                 tbdp = (I596_TBD *) S2H(tbdp->next);
 435                                 ++ddp_h;
 436                         }
 437                 }
 438                 if (ddp_h - priv->dmadesc_h)
 439                 {
 440                         int     rc;
 441 
 442                         rc = do_plx_dma(dev,
 443                                 0, (ulong) priv->dmadesc_s, len, 0);
 444                         if (rc)
 445                         {
 446                                 printk("%s: Chained DMA failure\n", dev->name);
 447                                 goto again;
 448                         }
 449                 }
 450         }
 451         else if (priv->use_dma)
 452         {
 453                 /*
 454                  *      If we can use DMA and its a shorter frame, copy it
 455                  *      using single DMA transfers.
 456                  */
 457                 uchar           *phys_p;
 458 
 459                 /*
 460                  *      Get the physical address of the STREAMS buffer.
 461                  *      NOTE: allocb() guarantees that the whole buffer
 462                  *      is in a single page if the length < 4096.
 463                  */
 464                 phys_p = (uchar *) virt_to_phys(putp);
 465 
 466                 tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
 467                 for (;;)
 468                 {
 469                         int     count;
 470                         int     amt;
 471                         int     rc;
 472 
 473                         count = tbdp->count;
 474                         amt = count & 0x3fff;
 475                         if (amt == 0)
 476                                 break; /* For safety */
 477                         if ( (p-putp) >= len)
 478                         {
 479                                 printk("%s: cbp = %x", dev->name, H2S(cbp));
 480                                 proc_reset(dev, 1);     /* Freeze IDT */
 481                                 break; /* For Safety */
 482                         }
 483                         rc = do_plx_dma(dev, (ulong) phys_p,
 484                                                 S2DMA(tbdp->buf), amt, 1);
 485                         if (rc)
 486                         {
 487                                 memcpy(p, S2H(tbdp->buf), amt);
 488                                 printk("%s: Single DMA failed\n", dev->name);
 489                         }
 490                         phys_p += amt;
 491                         p += amt;
 492                         if (count & I596_TBD_EOF)
 493                                 break;
 494                         tbdp = (I596_TBD *) S2H(tbdp->next);
 495                 }
 496         }
 497         else
 498         {
 499                 /*
 500                  *      Otherwise, copy it piece by piece using memcpy()
 501                  */
 502                 tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
 503                 for (;;)
 504                 {
 505                         int     count;
 506                         int     amt;
 507 
 508                         count = tbdp->count;
 509                         amt = count & 0x3fff;
 510                         if (amt == 0)
 511                                 break; /* For safety */
 512                         if ( (p-putp) >= len)
 513                         {
 514                                 printk("%s: cbp = %x", dev->name, H2S(cbp));
 515                                 proc_reset(dev, 1);     /* Freeze IDT */
 516                                 break; /* For Safety */
 517                         }
 518                         memcpy(p, S2H(tbdp->buf), amt);
 519                         p += amt;
 520                         if (count & I596_TBD_EOF)
 521                                 break;
 522                         tbdp = (I596_TBD *) S2H(tbdp->next);
 523                 }
 524         }
 525 
 526         /*
 527          *      Pass the frame to upper half
 528          */
 529         skb->protocol = eth_type_trans(skb, dev);
 530         netif_rx(skb);
 531         ++priv->stats.rx_packets;
 532 
 533 out:
 534         cbp->xmit.status = I596_CB_STATUS_C | I596_CB_STATUS_OK;
 535 }
 536 
 537 /*
 538  *      Start transmission of a frame
 539  *
 540  *      The interface to the board is simple: we pretend that we are
 541  *      a fifth 82596 ethernet controller 'receiving' data, and copy the
 542  *      data into the same structures that a real 82596 would.  This way,
 543  *      the board firmware handles the host 'port' the same as any other.
 544  *
 545  *      NOTE: we do not use Bus master DMA for this routine.  Turns out
 546  *      that it is not needed.  Slave writes over the PCI bus are about
 547  *      as fast as DMA, due to the fact that the PLX part can do burst
 548  *      writes.  The same is not true for data being read from the board.
 549  */
 550 static int
 551 dgrs_start_xmit(struct sk_buff *skb, struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
 552 {
 553         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 554         I596_RBD        *rbdp;
 555         int             count;
 556         int             i, len, amt;
 557 #       define          mymin(A,B)      ( (A) < (B) ? (A) : (B) )
 558 
 559         if (dgrs_debug > 1) printk("%s: xmit len=%ld\n", dev->name, skb->len);
 560 
 561         dev->trans_start = jiffies;
 562         dev->tbusy = 0;
 563 
 564         if (priv->rfdp->cmd & I596_RFD_EL)
 565         {       /* Out of RFD's */
 566                 if (0) printk("%s: NO RFD's", dev->name);
 567                 goto no_resources;
 568         }
 569 
 570         rbdp = priv->rbdp;
 571         count = 0;
 572         priv->rfdp->rbdp = (I596_RBD *) H2S(rbdp);
 573 
 574         i = 0; len = skb->len;
 575         for (;;)
 576         {
 577                 if (rbdp->size & I596_RBD_EL)
 578                 {       /* Out of RBD's */
 579                         if (0) printk("%s: NO RBD's", dev->name);
 580                         goto no_resources;
 581                 }
 582 
 583                 amt = mymin(len, rbdp->size - count);
 584                 memcpy( (char *) S2H(rbdp->buf) + count, skb->data + i, amt);
 585                 i += amt;
 586                 count += amt;
 587                 len -= amt;
 588                 if (len == 0)
 589                 {
 590                         if (skb->len < 60)
 591                                 rbdp->count = 60 | I596_RBD_EOF;
 592                         else
 593                                 rbdp->count = count | I596_RBD_EOF;
 594                         rbdp = (I596_RBD *) S2H(rbdp->next);
 595                         goto frame_done;
 596                 }
 597                 else if (count < 32)
 598                 {
 599                         /* More data to come, but we used less than 32
 600                          * bytes of this RBD.  Keep filling this RBD.
 601                          */
 602                         {}      /* Yes, we do nothing here */
 603                 }
 604                 else
 605                 {
 606                         rbdp->count = count;
 607                         rbdp = (I596_RBD *) S2H(rbdp->next);
 608                         count = 0;
 609                 }
 610         }
 611 
 612 frame_done:
 613         priv->rbdp = rbdp;
 614         priv->rfdp->status = I596_RFD_C | I596_RFD_OK;
 615         priv->rfdp = (I596_RFD *) S2H(priv->rfdp->next);
 616 
 617         ++priv->stats.tx_packets;
 618 
 619         dev_kfree_skb (skb, FREE_WRITE);
 620         return (0);
 621 
 622 no_resources:
 623         priv->scbp->status |= I596_SCB_RNR;     /* simulate I82596 */
 624         return (-EAGAIN);
 625 }
 626 
 627 /*
 628  *      Open the interface
 629  */
 630 static int
 631 dgrs_open( struct device *dev )
     /* [previous][next][first][last][top][bottom][index][help] */
 632 {
 633         dev->tbusy = 0;
 634         dev->interrupt = 0;
 635         dev->start = 1;
 636 
 637         #ifdef MODULE
 638                 MOD_INC_USE_COUNT;
 639         #endif
 640 
 641         return (0);
 642 }
 643 
 644 /*
 645  *      Close the interface
 646  */
 647 static int
 648 dgrs_close( struct device *dev )
     /* [previous][next][first][last][top][bottom][index][help] */
 649 {
 650         dev->start = 0;
 651         dev->tbusy = 1;
 652 
 653         #ifdef MODULE
 654                 MOD_DEC_USE_COUNT;
 655         #endif
 656 
 657         return (0);
 658 }
 659 
 660 /*
 661  *      Get statistics
 662  */
 663 static struct enet_statistics *
 664 dgrs_get_stats( struct device *dev )
     /* [previous][next][first][last][top][bottom][index][help] */
 665 {
 666         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 667 
 668         return (&priv->stats);
 669 }
 670 
 671 /*
 672  *      Set multicast list and/or promiscuous mode
 673  */
 674 static void
 675 dgrs_set_multicast_list( struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
 676 {
 677         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 678 
 679         priv->port->is_promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
 680 }
 681 
 682 /*
 683  *      Unique ioctl's
 684  */
 685 static int
 686 dgrs_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
     /* [previous][next][first][last][top][bottom][index][help] */
 687 {
 688         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 689         DGRS_IOCTL      ioc;
 690         int             i, rc;
 691 
 692         rc = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(DGRS_IOCTL));
 693         if (rc) return (rc);
 694         if (cmd != DGRSIOCTL) return -EINVAL;
 695 
 696         memcpy_fromfs(&ioc, ifr->ifr_data, sizeof(DGRS_IOCTL));
 697 
 698         switch (ioc.cmd)
 699         {
 700         case DGRS_GETMEM:
 701                 if (ioc.len != sizeof(ulong))
 702                         return -EINVAL;
 703                 rc = verify_area(VERIFY_WRITE, (void *) ioc.data, ioc.len);
 704                 if (rc) return (rc);
 705                 memcpy_tofs(ioc.data, &dev->mem_start, ioc.len);
 706                 return (0);
 707         case DGRS_SETFILTER:
 708                 rc = verify_area(VERIFY_READ, (void *) ioc.data, ioc.len);
 709                 if (rc) return (rc);
 710                 if (ioc.port > priv->bcomm->bc_nports)
 711                         return -EINVAL;
 712                 if (ioc.filter >= NFILTERS)
 713                         return -EINVAL;
 714                 if (ioc.len > priv->bcomm->bc_filter_area_len)
 715                         return -EINVAL;
 716 
 717                 /* Wait for old command to finish */
 718                 for (i = 0; i < 1000; ++i)
 719                 {
 720                         if ( (volatile) priv->bcomm->bc_filter_cmd <= 0 )
 721                                 break;
 722                         udelay(1);
 723                 }
 724                 if (i >= 1000)
 725                         return -EIO;
 726 
 727                 priv->bcomm->bc_filter_port = ioc.port;
 728                 priv->bcomm->bc_filter_num = ioc.filter;
 729                 priv->bcomm->bc_filter_len = ioc.len;
 730                 
 731                 if (ioc.len)
 732                 {
 733                         memcpy_fromfs(S2H(priv->bcomm->bc_filter_area),
 734                                         ioc.data, ioc.len);
 735                         priv->bcomm->bc_filter_cmd = BC_FILTER_SET;
 736                 }
 737                 else
 738                         priv->bcomm->bc_filter_cmd = BC_FILTER_CLR;
 739                 return(0);
 740         default:
 741                 return -EOPNOTSUPP;
 742         }
 743 }
 744 
 745 /*
 746  *      Process interrupts
 747  */
 748 static void
 749 dgrs_intr(int irq, void *dev_id, struct pt_regs *regs)
     /* [previous][next][first][last][top][bottom][index][help] */
 750 {
 751         struct device   *dev = (struct device *) dev_id;
 752         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 753         I596_CB         *cbp;
 754         int             cmd;
 755         
 756         ++priv->intrcnt;
 757         if (1) ++priv->bcomm->bc_cnt[4];
 758         if (0) printk("%s: interrupt: irq %d", dev->name, irq);
 759 
 760         /*
 761          *      Get 596 command
 762          */
 763         cmd = priv->scbp->cmd;
 764 
 765         /*
 766          *      See if RU has been restarted
 767          */
 768         if ( (cmd & I596_SCB_RUC) == I596_SCB_RUC_START)
 769         {
 770                 if (0) printk("%s: RUC start", dev->name);
 771                 priv->rfdp = (I596_RFD *) S2H(priv->scbp->rfdp);
 772                 priv->rbdp = (I596_RBD *) S2H(priv->rfdp->rbdp);
 773                 dev->tbusy = 0; /* tell upper half */
 774                 priv->scbp->status &= ~(I596_SCB_RNR|I596_SCB_RUS);
 775                 /* if (bd->flags & TX_QUEUED)
 776                         DL_sched(bd, bdd); */
 777         }
 778 
 779         /*
 780          *      See if any CU commands to process
 781          */
 782         if ( (cmd & I596_SCB_CUC) != I596_SCB_CUC_START)
 783         {
 784                 priv->scbp->cmd = 0;    /* Ignore all other commands */
 785                 goto ack_intr;
 786         }
 787         priv->scbp->status &= ~(I596_SCB_CNA|I596_SCB_CUS);
 788 
 789         /*
 790          *      Process a command
 791          */
 792         cbp = (I596_CB *) S2H(priv->scbp->cbp);
 793         priv->scbp->cmd = 0;    /* Safe to clear the command */
 794         for (;;)
 795         {
 796                 switch (cbp->nop.cmd & I596_CB_CMD)
 797                 {
 798                 case I596_CB_CMD_XMIT:
 799                         dgrs_rcv_frame(dev, priv, cbp);
 800                         break;
 801                 default:
 802                         cbp->nop.status = I596_CB_STATUS_C | I596_CB_STATUS_OK;
 803                         break;
 804                 }
 805                 if (cbp->nop.cmd & I596_CB_CMD_EL)
 806                         break;
 807                 cbp = (I596_CB *) S2H(cbp->nop.next);
 808         }
 809         priv->scbp->status |= I596_SCB_CNA;
 810 
 811         /*
 812          * Ack the interrupt
 813          */
 814 ack_intr:
 815         if (priv->plxreg)
 816                 OUTL(dev->base_addr + PLX_LCL2PCI_DOORBELL, 1);
 817 }
 818 
 819 /*
 820  *      Download the board firmware
 821  */
 822 static int
 823 dgrs_download(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
 824 {
 825         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 826         int             is;
 827         int             i;
 828 
 829         static int      iv2is[16] = {
 830                                 0, 0, 0, ES4H_IS_INT3,
 831                                 0, ES4H_IS_INT5, 0, ES4H_IS_INT7,
 832                                 0, 0, ES4H_IS_INT10, ES4H_IS_INT11,
 833                                 ES4H_IS_INT12, 0, 0, ES4H_IS_INT15 };
 834 
 835         /*
 836          * Map in the dual port memory
 837          */
 838         priv->vmem = vremap(dev->mem_start, 2048*1024);
 839         if (!priv->vmem)
 840         {
 841                 printk("%s: cannot map in board memory\n", dev->name);
 842                 return -ENXIO;
 843         }
 844 
 845         /*
 846          *      Hold the processor and configure the board addresses
 847          */
 848         if (priv->plxreg)
 849         {       /* PCI bus */
 850                 proc_reset(dev, 1);
 851         }
 852         else
 853         {       /* EISA bus */
 854                 is = iv2is[dev->irq & 0x0f];
 855                 if (!is)
 856                 {
 857                         printk("%s: Illegal IRQ %d\n", dev->name, dev->irq);
 858                         return -ENXIO;
 859                 }
 860                 OUTB(dev->base_addr + ES4H_AS_31_24,
 861                         (uchar) (dev->mem_start >> 24) );
 862                 OUTB(dev->base_addr + ES4H_AS_23_16,
 863                         (uchar) (dev->mem_start >> 16) );
 864                 priv->is_reg = ES4H_IS_LINEAR | is |
 865                         ((uchar) (dev->mem_start >> 8) & ES4H_IS_AS15);
 866                 OUTB(dev->base_addr + ES4H_IS, priv->is_reg);
 867                 OUTB(dev->base_addr + ES4H_EC, ES4H_EC_ENABLE);
 868                 OUTB(dev->base_addr + ES4H_PC, ES4H_PC_RESET);
 869                 OUTB(dev->base_addr + ES4H_MW, ES4H_MW_ENABLE | 0x00);
 870         }
 871 
 872         /*
 873          *      See if we can do DMA on the SE-6
 874          */
 875         priv->use_dma = check_board_dma(dev);
 876         if (priv->use_dma)
 877                 printk("%s: Bus Master DMA is enabled.\n", dev->name);
 878 
 879         /*
 880          * Load and verify the code at the desired address
 881          */
 882         memcpy(priv->vmem, dgrs_code, dgrs_ncode);      /* Load code */
 883         if (memcmp(priv->vmem, dgrs_code, dgrs_ncode))
 884         {
 885                 vfree(priv->vmem);
 886                 priv->vmem = NULL;
 887                 printk("%s: download compare failed\n", dev->name);
 888                 return -ENXIO;
 889         }
 890 
 891         /*
 892          * Configurables
 893          */
 894         priv->bcomm = (struct bios_comm *) (priv->vmem + 0x0100);
 895         priv->bcomm->bc_nowait = 1;     /* Tell board to make printf not wait */
 896         priv->bcomm->bc_host = 1;       /* Tell board there is a host port */
 897         priv->bcomm->bc_squelch = 0;    /* Flag from Space.c */
 898         priv->bcomm->bc_150ohm = 0;     /* Flag from Space.c */
 899 
 900         priv->bcomm->bc_spew = 0;       /* Debug flag from Space.c */
 901         priv->bcomm->bc_maxrfd = 0;     /* Debug flag from Space.c */
 902         priv->bcomm->bc_maxrbd = 0;     /* Debug flag from Space.c */
 903 
 904         /*
 905          * Request memory space on board for DMA chains
 906          */
 907         if (priv->use_dma)
 908                 priv->bcomm->bc_hostarea_len = (2048/64) * 16;
 909 
 910         /*
 911          * NVRAM configurables from Space.c
 912          */
 913         priv->bcomm->bc_spantree = dgrs_spantree;
 914         priv->bcomm->bc_hashexpire = dgrs_hashexpire;
 915         memcpy(priv->bcomm->bc_ipaddr, dgrs_ipaddr, 4);
 916         memcpy(priv->bcomm->bc_ipxnet, &dgrs_ipxnet, 4);
 917 
 918         /*
 919          * Release processor, wait 5 seconds for board to initialize
 920          */
 921         proc_reset(dev, 0);
 922 
 923         for (i = jiffies + 5 * HZ; i > jiffies; )
 924         {
 925                 if (priv->bcomm->bc_status >= BC_RUN)
 926                         break;
 927         }
 928 
 929         if (priv->bcomm->bc_status < BC_RUN)
 930         {
 931                 printk("%s: board not operating", dev->name);
 932                 return -ENXIO;
 933         }
 934 
 935         priv->port = (PORT *) S2H(priv->bcomm->bc_port);
 936         priv->scbp = (I596_SCB *) S2H(priv->port->scbp);
 937         #if 0   /* These two methods are identical, but the 2nd is better */
 938                 priv->rfdp = (I596_RFD *) S2H(priv->port->rfd_head);
 939                 priv->rbdp = (I596_RBD *) S2H(priv->port->rbd_head);
 940         #else
 941                 priv->rfdp = (I596_RFD *) S2H(priv->scbp->rfdp);
 942                 priv->rbdp = (I596_RBD *) S2H(priv->rfdp->rbdp);
 943         #endif
 944 
 945         priv->scbp->status = I596_SCB_CNA;      /* CU is idle */
 946 
 947         /*
 948          *      Get switch physical and host virtual pointers to DMA
 949          *      chaining area.  NOTE: the MSB of the switch physical
 950          *      address *must* be turned off.  Otherwise, the HW kludge
 951          *      that allows host access of the PLX DMA registers will
 952          *      erroneously select the PLX registers.
 953          */
 954         priv->dmadesc_s = (DMACHAIN *) S2DMA(priv->bcomm->bc_hostarea);
 955         if (priv->dmadesc_s)
 956                 priv->dmadesc_h = (DMACHAIN *) S2H(priv->dmadesc_s);
 957         else
 958                 priv->dmadesc_h = NULL;
 959 
 960         /*
 961          *      Enable board interrupts
 962          */
 963         if (priv->plxreg)
 964         {       /* PCI bus */
 965                 OUTL(dev->base_addr + PLX_INT_CSR,
 966                         inl(dev->base_addr + PLX_INT_CSR)
 967                         | PLX_PCI_DOORBELL_IE); /* Enable intr to host */
 968                 OUTL(dev->base_addr + PLX_LCL2PCI_DOORBELL, 1);
 969         }
 970         else
 971         {       /* EISA bus */
 972         }
 973 
 974         return (0);
 975 }
 976 
 977 /*
 978  *      Probe (init) a board
 979  */
 980 int
 981 dgrs_probe1(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
 982 {
 983         DGRS_PRIV       *priv = (DGRS_PRIV *) dev->priv;
 984         int             i;
 985         int             rc;
 986 
 987         printk("%s: Digi RightSwitch at io=%lx mem=%lx irq=%d plx=%lx dma=%lx ",
 988                 dev->name, dev->base_addr, dev->mem_start, dev->irq,
 989                 priv->plxreg, priv->plxdma);
 990 
 991         /*
 992          *      Download the firmware and light the processor
 993          */
 994         rc = dgrs_download(dev);
 995         if (rc)
 996         {
 997                 printk("\n");
 998                 return rc;
 999         }
1000 
1001         /*
1002          * Get ether address of board
1003          */
1004         memcpy(dev->dev_addr, priv->port->ethaddr, 6);
1005         for (i = 0; i < 6; ++i)
1006                 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1007         printk("\n");
1008 
1009         if (dev->dev_addr[0] & 1)
1010         {
1011                 printk("%s: Illegal Ethernet Address", dev->name);
1012                 return (-ENXIO);
1013         }
1014 
1015         /*
1016          *      ACK outstanding interrupts, hook the interrupt,
1017          *      and verify that we are getting interrupts from the board.
1018          */
1019         if (priv->plxreg)
1020                 OUTL(dev->base_addr + PLX_LCL2PCI_DOORBELL, 1);
1021         rc = request_irq(dev->irq, &dgrs_intr, 0, "RightSwitch", dev);
1022         if (rc)
1023                 return (rc);
1024 
1025         priv->intrcnt = 0;
1026         for (i = jiffies + 2*HZ + HZ/2; i > jiffies; )
1027                 if (priv->intrcnt >= 2)
1028                         break;
1029         if (priv->intrcnt < 2)
1030         {
1031                 printk("%s: Not interrupting on IRQ %d (%d)",
1032                                 dev->name, dev->irq, priv->intrcnt);
1033                 return (-ENXIO);
1034         }
1035 
1036         /*
1037          *      Register the /proc/ioports information...
1038          */
1039         request_region(dev->base_addr, 256, "RightSwitch");
1040 
1041         /*
1042          *      Entry points...
1043          */
1044         dev->open = &dgrs_open;
1045         dev->stop = &dgrs_close;
1046         dev->get_stats = &dgrs_get_stats;
1047         dev->hard_start_xmit = &dgrs_start_xmit;
1048         dev->set_multicast_list = &dgrs_set_multicast_list;
1049         dev->do_ioctl = &dgrs_ioctl;
1050 
1051         return (0);
1052 }
1053 
1054 static int
1055 dgrs_found_device(
     /* [previous][next][first][last][top][bottom][index][help] */
1056         struct device   *dev,
1057         int             io,
1058         ulong           mem,
1059         int             irq,
1060         ulong           plxreg,
1061         ulong           plxdma
1062 )
1063 {
1064         DGRS_PRIV       *priv;
1065 
1066         #ifdef MODULE
1067         {
1068                 /* Allocate and fill new device structure. */
1069                 int dev_size = sizeof(struct device) + sizeof(DGRS_PRIV);
1070 
1071                 dev = (struct device *) kmalloc(dev_size, GFP_KERNEL);
1072                 memset(dev, 0, dev_size);
1073                 dev->priv = ((void *)dev) + sizeof(struct device);
1074                 priv = (DGRS_PRIV *)dev->priv;
1075 
1076                 dev->name = priv->devname; /* An empty string. */
1077                 dev->base_addr = io;
1078                 dev->mem_start = mem;
1079                 dev->mem_end = mem + 2048 * 1024 - 1;
1080                 dev->irq = irq;
1081                 priv->plxreg = plxreg;
1082                 priv->plxdma = plxdma;
1083                 priv->vplxdma = NULL;
1084 
1085                 dev->init = dgrs_probe1;
1086 
1087                 ether_setup(dev);
1088                 priv->next_dev = dgrs_root_dev;
1089                 dgrs_root_dev = dev;
1090                 if (register_netdev(dev) != 0)
1091                         return -EIO;
1092         }
1093         #else
1094         {
1095                 if (dev)
1096                 {
1097                         dev->priv = kmalloc(sizeof (DGRS_PRIV), GFP_KERNEL);
1098                         memset(dev->priv, 0, sizeof (DGRS_PRIV));
1099                 }
1100                 dev = init_etherdev(dev, sizeof(DGRS_PRIV));
1101                 priv = (DGRS_PRIV *)dev->priv;
1102 
1103                 dev->base_addr = io;
1104                 dev->mem_start = mem;
1105                 dev->mem_end = mem + 2048 * 1024;
1106                 dev->irq = irq;
1107                 priv->plxreg = plxreg;
1108                 priv->plxdma = plxdma;
1109                 priv->vplxdma = NULL;
1110 
1111                 dgrs_probe1(dev);
1112         }
1113         #endif
1114 
1115         return (0);
1116 }
1117 
1118 /*
1119  *      Scan for all boards
1120  */
1121 static int
1122 dgrs_scan(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1123 {
1124         int     cards_found = 0;
1125         uint    io;
1126         uint    mem;
1127         uint    irq;
1128         uint    plxreg;
1129         uint    plxdma;
1130 
1131         /*
1132          *      First, check for PCI boards
1133          */
1134         if (pcibios_present())
1135         {
1136                 int pci_index = 0;
1137 
1138                 for (; pci_index < 8; pci_index++)
1139                 {
1140                         uchar   pci_bus, pci_device_fn;
1141                         uchar   pci_irq;
1142                         uchar   pci_latency;
1143                         ushort  pci_command;
1144 
1145                         if (pcibios_find_device(SE6_PCI_VENDOR_ID,
1146                                                         SE6_PCI_DEVICE_ID,
1147                                                         pci_index, &pci_bus,
1148                                                         &pci_device_fn))
1149                                         break;
1150 
1151                         pcibios_read_config_byte(pci_bus, pci_device_fn,
1152                                         PCI_INTERRUPT_LINE, &pci_irq);
1153                         pcibios_read_config_dword(pci_bus, pci_device_fn,
1154                                         PCI_BASE_ADDRESS_0, &plxreg);
1155                         pcibios_read_config_dword(pci_bus, pci_device_fn,
1156                                         PCI_BASE_ADDRESS_1, &io);
1157                         pcibios_read_config_dword(pci_bus, pci_device_fn,
1158                                         PCI_BASE_ADDRESS_2, &mem);
1159                         pcibios_read_config_dword(pci_bus, pci_device_fn,
1160                                         0x30, &plxdma);
1161                         irq = pci_irq;
1162                         plxreg &= ~15;
1163                         io &= ~3;
1164                         mem &= ~15;
1165                         plxdma &= ~15;
1166 
1167                         /*
1168                          * On some BIOSES, the PLX "expansion rom" (used for DMA)
1169                          * address comes up as "0".  This is probably because
1170                          * the BIOS doesn't see a valid 55 AA ROM signature at
1171                          * the "ROM" start and zeroes the address.  To get
1172                          * around this problem the SE-6 is configured to ask
1173                          * for 4 MB of space for the dual port memory.  We then
1174                          * must set its range back to 2 MB, and use the upper
1175                          * half for DMA register access
1176                          */
1177                         OUTL(io + PLX_SPACE0_RANGE, 0xFFE00000L);
1178                         if (plxdma == 0)
1179                                 plxdma = mem + (2048L * 1024L);
1180                         pcibios_write_config_dword(pci_bus, pci_device_fn,
1181                                         0x30, plxdma + 1);
1182                         pcibios_read_config_dword(pci_bus, pci_device_fn,
1183                                         0x30, &plxdma);
1184                         plxdma &= ~15;
1185 
1186                         /*
1187                          * Get and check the bus-master and latency values.
1188                          * Some PCI BIOSes fail to set the master-enable bit,
1189                          * and the latency timer must be set to the maximum
1190                          * value to avoid data corruption that occurs when the
1191                          * timer expires during a transfer.  Yes, it's a bug.
1192                          */
1193                         pcibios_read_config_word(pci_bus, pci_device_fn,
1194                                                  PCI_COMMAND, &pci_command);
1195                         if ( ! (pci_command & PCI_COMMAND_MASTER))
1196                         {
1197                                 printk("  Setting the PCI Master Bit!\n");
1198                                 pci_command |= PCI_COMMAND_MASTER;
1199                                 pcibios_write_config_word(pci_bus,
1200                                                 pci_device_fn,
1201                                                 PCI_COMMAND, pci_command);
1202                         }
1203                         pcibios_read_config_byte(pci_bus, pci_device_fn,
1204                                          PCI_LATENCY_TIMER, &pci_latency);
1205                         if (pci_latency != 255)
1206                         {
1207                                 printk("  Overriding PCI latency timer: "
1208                                         "was %d, now is 255.\n", pci_latency);
1209                                 pcibios_write_config_byte(pci_bus,
1210                                                 pci_device_fn,
1211                                                 PCI_LATENCY_TIMER, 255);
1212                         }
1213 
1214                         dgrs_found_device(dev, io, mem, irq, plxreg, plxdma);
1215 
1216                         dev = 0;
1217                         cards_found++;
1218                 }
1219         }
1220 
1221         /*
1222          *      Second, check for EISA boards
1223          */
1224         if (EISA_bus)
1225         {
1226                 static int      is2iv[8] = { 0, 3, 5, 7, 10, 11, 12, 15 };
1227 
1228                 for (io = 0x1000; io < 0x9000; io += 0x1000)
1229                 {
1230                         if (inb(io+ES4H_MANUFmsb) != 0x10
1231                                 || inb(io+ES4H_MANUFlsb) != 0x49
1232                                 || inb(io+ES4H_PRODUCT) != ES4H_PRODUCT_CODE)
1233                                 continue;
1234 
1235                         if ( ! (inb(io+ES4H_EC) & ES4H_EC_ENABLE) )
1236                                 continue; /* Not EISA configured */
1237 
1238                         mem = (inb(io+ES4H_AS_31_24) << 24)
1239                                 + (inb(io+ES4H_AS_23_16) << 16);
1240 
1241                         irq = is2iv[ inb(io+ES4H_IS) & ES4H_IS_INTMASK ];
1242                         
1243                         dgrs_found_device(dev, io, mem, irq, 0L, 0L);
1244 
1245                         dev = 0;
1246                         ++cards_found;
1247                 }
1248         }
1249 
1250         return cards_found;
1251 }
1252 
1253 /*
1254  *      Module/driver initialization points.  Two ways, depending on
1255  *      whether we are a module or statically linked, ala Don Becker's
1256  *      3c59x driver.
1257  */
1258 
1259 #ifdef MODULE
1260 
1261 /*
1262  *      Variables that can be overridden from command line
1263  */
1264 static int      debug = -1;
1265 static int      dma = -1;
1266 static int      hashexpire = -1;
1267 static int      spantree = -1;
1268 static int      ipaddr[4] = { -1 };
1269 static long     ipxnet = -1;
1270 
1271 int
1272 init_module(void)
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1273 {
1274         int     cards_found;
1275 
1276         /*
1277          *      Command line variable overrides
1278          *              debug=NNN
1279          *              dma=0/1
1280          *              spantree=0/1
1281          *              hashexpire=NNN
1282          *              ipaddr=A,B,C,D
1283          *              ipxnet=NNN
1284          */
1285         if (debug >= 0)
1286                 dgrs_debug = debug;
1287         if (dma >= 0)
1288                 dgrs_dma = dma;
1289         if (hashexpire >= 0)
1290                 dgrs_hashexpire = hashexpire;
1291         if (spantree >= 0)
1292                 dgrs_spantree = spantree;
1293         if (ipaddr[0] != -1)
1294         {
1295                 int     i;
1296 
1297                 for (i = 0; i < 4; ++i)
1298                         dgrs_ipaddr[i] = ipaddr[i];
1299         }
1300         if (ipxnet != -1)
1301                 dgrs_ipxnet = htonl( ipxnet );
1302                 
1303         if (dgrs_debug)
1304         {
1305                 printk("dgrs: SW=%s FW=Build %d %s\n",
1306                         version, dgrs_firmnum, dgrs_firmdate);
1307         }
1308         
1309         /*
1310          *      Find and configure all the cards
1311          */
1312         dgrs_root_dev = NULL;
1313         cards_found = dgrs_scan(0);
1314 
1315         return cards_found ? 0 : -ENODEV;
1316 }
1317 
1318 void
1319 cleanup_module(void)
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1320 {
1321         while (dgrs_root_dev)
1322         {
1323                 struct device   *next_dev;
1324                 DGRS_PRIV       *priv;
1325 
1326                 priv = (DGRS_PRIV *) dgrs_root_dev->priv;
1327                 next_dev = priv->next_dev;
1328                 unregister_netdev(dgrs_root_dev);
1329 
1330                 proc_reset(dgrs_root_dev, 1);
1331 
1332                 if (priv->vmem)
1333                         vfree(priv->vmem);
1334                 if (priv->vplxdma)
1335                         vfree((uchar *) priv->vplxdma);
1336 
1337                 release_region(dgrs_root_dev->base_addr, 256);
1338 
1339                 free_irq(dgrs_root_dev->irq, dgrs_root_dev);
1340 
1341                 kfree(dgrs_root_dev);
1342                 dgrs_root_dev = next_dev;
1343         }
1344 }
1345 
1346 #else
1347 
1348 int
1349 dgrs_probe(struct device *dev)
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1350 {
1351         int     cards_found;
1352 
1353         cards_found = dgrs_scan(dev);
1354         if (dgrs_debug && cards_found)
1355                 printk("dgrs: SW=%s FW=Build %d %s\n",
1356                         version, dgrs_firmnum, dgrs_firmdate);
1357         return cards_found ? 0 : -ENODEV;
1358 }
1359 #endif

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