root/drivers/scsi/wd33c93.h

/* */

INCLUDED FROM

   1 /*
   2  *    wd33c93.h -  Linux device driver definitions for the
   3  *                 Commodore Amiga A2091/590 SCSI controller card
   4  *
   5  *    IMPORTANT: This file is for version 1.21 - 20/Mar/1996
   6  *
   7  * Copyright (c) 1996 John Shifflett, GeoLog Consulting
   8  *    john@geolog.com
   9  *    jshiffle@netcom.com
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2, or (at your option)
  14  * any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  */
  22 
  23 #ifndef WD33C93_H
  24 #define WD33C93_H
  25 
  26 
  27 #define uchar unsigned char
  28 
  29 
  30 /* wd register names */
  31 #define WD_OWN_ID    0x00
  32 #define WD_CONTROL      0x01
  33 #define WD_TIMEOUT_PERIOD  0x02
  34 #define WD_CDB_1     0x03
  35 #define WD_CDB_2     0x04
  36 #define WD_CDB_3     0x05
  37 #define WD_CDB_4     0x06
  38 #define WD_CDB_5     0x07
  39 #define WD_CDB_6     0x08
  40 #define WD_CDB_7     0x09
  41 #define WD_CDB_8     0x0a
  42 #define WD_CDB_9     0x0b
  43 #define WD_CDB_10    0x0c
  44 #define WD_CDB_11    0x0d
  45 #define WD_CDB_12    0x0e
  46 #define WD_TARGET_LUN      0x0f
  47 #define WD_COMMAND_PHASE   0x10
  48 #define WD_SYNCHRONOUS_TRANSFER 0x11
  49 #define WD_TRANSFER_COUNT_MSB 0x12
  50 #define WD_TRANSFER_COUNT  0x13
  51 #define WD_TRANSFER_COUNT_LSB 0x14
  52 #define WD_DESTINATION_ID  0x15
  53 #define WD_SOURCE_ID    0x16
  54 #define WD_SCSI_STATUS     0x17
  55 #define WD_COMMAND      0x18
  56 #define WD_DATA      0x19
  57 #define WD_QUEUE_TAG    0x1a
  58 #define WD_AUXILIARY_STATUS   0x1f
  59 
  60 /* WD commands */
  61 #define WD_CMD_RESET    0x00
  62 #define WD_CMD_ABORT    0x01
  63 #define WD_CMD_ASSERT_ATN  0x02
  64 #define WD_CMD_NEGATE_ACK  0x03
  65 #define WD_CMD_DISCONNECT  0x04
  66 #define WD_CMD_RESELECT    0x05
  67 #define WD_CMD_SEL_ATN     0x06
  68 #define WD_CMD_SEL      0x07
  69 #define WD_CMD_SEL_ATN_XFER   0x08
  70 #define WD_CMD_SEL_XFER    0x09
  71 #define WD_CMD_RESEL_RECEIVE  0x0a
  72 #define WD_CMD_RESEL_SEND  0x0b
  73 #define WD_CMD_WAIT_SEL_RECEIVE 0x0c
  74 #define WD_CMD_TRANS_ADDR  0x18
  75 #define WD_CMD_TRANS_INFO  0x20
  76 #define WD_CMD_TRANSFER_PAD   0x21
  77 #define WD_CMD_SBT_MODE    0x80
  78 
  79 /* ASR register */
  80 #define ASR_INT         (0x80)
  81 #define ASR_LCI         (0x40)
  82 #define ASR_BSY         (0x20)
  83 #define ASR_CIP         (0x10)
  84 #define ASR_PE          (0x02)
  85 #define ASR_DBR         (0x01)
  86 
  87 /* SCSI Bus Phases */
  88 #define PHS_DATA_OUT    0x00
  89 #define PHS_DATA_IN     0x01
  90 #define PHS_COMMAND     0x02
  91 #define PHS_STATUS      0x03
  92 #define PHS_MESS_OUT    0x06
  93 #define PHS_MESS_IN     0x07
  94 
  95 /* Command Status Register definitions */
  96 
  97   /* reset state interrupts */
  98 #define CSR_RESET    0x00
  99 #define CSR_RESET_AF    0x01
 100 
 101   /* successful completion interrupts */
 102 #define CSR_RESELECT    0x10
 103 #define CSR_SELECT      0x11
 104 #define CSR_SEL_XFER_DONE  0x16
 105 #define CSR_XFER_DONE      0x18
 106 
 107   /* paused or aborted interrupts */
 108 #define CSR_MSGIN    0x20
 109 #define CSR_SDP         0x21
 110 #define CSR_SEL_ABORT      0x22
 111 #define CSR_RESEL_ABORT    0x25
 112 #define CSR_RESEL_ABORT_AM 0x27
 113 #define CSR_ABORT    0x28
 114 
 115   /* terminated interrupts */
 116 #define CSR_INVALID     0x40
 117 #define CSR_UNEXP_DISC     0x41
 118 #define CSR_TIMEOUT     0x42
 119 #define CSR_PARITY      0x43
 120 #define CSR_PARITY_ATN     0x44
 121 #define CSR_BAD_STATUS     0x45
 122 #define CSR_UNEXP    0x48
 123 
 124   /* service required interrupts */
 125 #define CSR_RESEL    0x80
 126 #define CSR_RESEL_AM    0x81
 127 #define CSR_DISC     0x85
 128 #define CSR_SRV_REQ     0x88
 129 
 130    /* Own ID/CDB Size register */
 131 #define OWNID_EAF    0x08
 132 #define OWNID_EHP    0x10
 133 #define OWNID_RAF    0x20
 134 #define OWNID_FS_8   0x00
 135 #define OWNID_FS_12  0x40
 136 #define OWNID_FS_16  0x80
 137 
 138    /* define these so we don't have to change a2091.c, etc. */
 139 #define WD33C93_FS_8_10  OWNID_FS_8
 140 #define WD33C93_FS_12_15 OWNID_FS_12
 141 #define WD33C93_FS_16_20 OWNID_FS_16
 142 
 143    /* Control register */
 144 #define CTRL_HSP     0x01
 145 #define CTRL_HA      0x02
 146 #define CTRL_IDI     0x04
 147 #define CTRL_EDI     0x08
 148 #define CTRL_HHP     0x10
 149 #define CTRL_POLLED  0x00
 150 #define CTRL_BURST   0x20
 151 #define CTRL_BUS     0x40
 152 #define CTRL_DMA     0x80
 153 
 154    /* Timeout Period register */
 155 #define TIMEOUT_PERIOD_VALUE  20    /* 20 = 200 ms */
 156 
 157    /* Synchronous Transfer Register */
 158 #define STR_FSS      0x80
 159 
 160    /* Destination ID register */
 161 #define DSTID_DPD    0x40
 162 #define DATA_OUT_DIR 0
 163 #define DATA_IN_DIR  1
 164 #define DSTID_SCC    0x80
 165 
 166    /* Source ID register */
 167 #define SRCID_MASK   0x07
 168 #define SRCID_SIV    0x08
 169 #define SRCID_DSP    0x20
 170 #define SRCID_ES     0x40
 171 #define SRCID_ER     0x80
 172 
 173    /* This is what the 3393 chip looks like to us */
 174 typedef struct {
 175    volatile unsigned char   SASR;
 176    char                     pad;
 177    volatile unsigned char   SCMD;
 178 } wd33c93_regs;
 179 
 180 
 181 typedef int (*dma_setup_t) (Scsi_Cmnd *SCpnt, int dir_in);
 182 typedef void (*dma_stop_t) (struct Scsi_Host *instance, Scsi_Cmnd *SCpnt,
 183              int status);
 184 
 185 
 186 #define DEFAULT_SX_PER   500     /* (ns) fairly safe */
 187 #define DEFAULT_SX_OFF   0       /* aka async */
 188 
 189 #define OPTIMUM_SX_PER   252     /* (ns) best we can do (mult-of-4) */
 190 #define OPTIMUM_SX_OFF   12      /* size of wd3393 fifo */
 191 
 192 struct sx_period {
 193    unsigned int   period_ns;
 194    uchar          reg_value;
 195    };
 196 
 197 /* FEF: defines for hostdata->dma_buffer_pool */
 198 
 199 #define BUF_CHIP_ALLOCED 0
 200 #define BUF_SCSI_ALLOCED 1
 201 
 202 struct WD33C93_hostdata {
 203     struct Scsi_Host *next;
 204     wd33c93_regs     *regp;
 205     uchar            clock_freq;
 206     uchar            chip;             /* what kind of wd33c93? */
 207     uchar            microcode;        /* microcode rev */
 208     int              dma_dir;          /* data transfer dir. */
 209     dma_setup_t      dma_setup;
 210     dma_stop_t       dma_stop;
 211     uchar            *dma_bounce_buffer;
 212     unsigned int     dma_bounce_len;
 213     uchar            dma_buffer_pool;  /* FEF: buffer from chip_ram? */
 214     volatile uchar   busy[8];          /* index = target, bit = lun */
 215     volatile Scsi_Cmnd *input_Q;       /* commands waiting to be started */
 216     volatile Scsi_Cmnd *selecting;     /* trying to select this command */
 217     volatile Scsi_Cmnd *connected;     /* currently connected command */
 218     volatile Scsi_Cmnd *disconnected_Q;/* commands waiting for reconnect */
 219     uchar            state;            /* what we are currently doing */
 220     uchar            dma;              /* current state of DMA (on/off) */
 221     uchar            level2;           /* extent to which Level-2 commands are used */
 222     uchar            disconnect;       /* disconnect/reselect policy */
 223     unsigned int     args;             /* set from command-line argument */
 224     uchar            incoming_msg[8];  /* filled during message_in phase */
 225     int              incoming_ptr;     /* mainly used with EXTENDED messages */
 226     uchar            outgoing_msg[8];  /* send this during next message_out */
 227     int              outgoing_len;     /* length of outgoing message */
 228     unsigned int     default_sx_per;   /* default transfer period for SCSI bus */
 229     uchar            sync_xfer[8];     /* sync_xfer reg settings per target */
 230     uchar            sync_stat[8];     /* status of sync negotiation per target */
 231     uchar            no_sync;          /* bitmask: don't do sync on these targets */
 232 #if 0
 233     uchar            proc;             /* bitmask: what's in proc output */
 234 #endif
 235     };
 236 
 237 
 238 /* defines for hostdata->chip */
 239 
 240 #define C_WD33C93       0
 241 #define C_WD33C93A      1
 242 #define C_WD33C93B      2
 243 #define C_UNKNOWN_CHIP  100
 244 
 245 /* defines for hostdata->state */
 246 
 247 #define S_UNCONNECTED         0
 248 #define S_SELECTING           1
 249 #define S_RUNNING_LEVEL2      2
 250 #define S_CONNECTED           3
 251 #define S_PRE_TMP_DISC        4
 252 #define S_PRE_CMP_DISC        5
 253 
 254 /* defines for hostdata->dma */
 255 
 256 #define D_DMA_OFF          0
 257 #define D_DMA_RUNNING      1
 258 
 259 /* defines for hostdata->level2 */
 260 /* NOTE: only the first 3 are implemented so far */
 261 
 262 /*  (The first 8 bits are reserved for compatibility. They function
 263 #define L2_SELECT    2  /* start with SEL_ATN_XFER, but never resume it */
 264 #define L2_BASIC     3  /* resume after STATUS ints & RDP messages */
 265 #define L2_DATA      4  /* resume after DATA_IN/OUT ints */
 266 #define L2_MOST      5  /* resume after anything except a RESELECT int */
 267 #define L2_RESELECT  6  /* resume after everything, including RESELECT ints */
 268 #define L2_ALL       7  /* always resume */
 269 
 270 /* defines for hostdata->disconnect */
 271 
 272 #define DIS_NEVER    0
 273 #define DIS_ADAPTIVE 1
 274 #define DIS_ALWAYS   2
 275 
 276 /* defines for hostdata->args */
 277 
 278 #define DB_TEST1              1<<0
 279 #define DB_TEST2              1<<1
 280 #define DB_QUEUE_COMMAND      1<<2
 281 #define DB_EXECUTE            1<<3
 282 #define DB_INTR               1<<4
 283 #define DB_TRANSFER           1<<5
 284 #define DB_MASK               0x3f
 285 
 286 /* defines for hostdata->sync_stat[] */
 287 
 288 #define SS_UNSET     0
 289 #define SS_FIRST     1
 290 #define SS_WAITING   2
 291 #define SS_SET       3
 292 
 293 /* defines for hostdata->proc */
 294 
 295 #define PR_VERSION   1<<0
 296 #define PR_INFO      1<<1
 297 #define PR_TOTALS    1<<2
 298 #define PR_CONNECTED 1<<3
 299 #define PR_INPUTQ    1<<4
 300 #define PR_DISCQ     1<<5
 301 #define PR_TEST      1<<6
 302 #define PR_STOP      1<<7
 303 
 304 
 305 void wd33c93_init (struct Scsi_Host *instance, wd33c93_regs *regs,
 306          dma_setup_t setup, dma_stop_t stop, int clock_freq);
 307 int wd33c93_abort (Scsi_Cmnd *cmd);
 308 int wd33c93_queuecommand (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
 309 void wd33c93_intr (struct Scsi_Host *instance);
 310 int wd33c93_proc_info(char *, char **, off_t, int, int, int);
 311 
 312 #if LINUX_VERSION_CODE >= 0x010300
 313 int wd33c93_reset (Scsi_Cmnd *, unsigned int);
 314 #else
 315 int wd33c93_reset (Scsi_Cmnd *);
 316 #endif
 317 
 318 #if 0
 319 struct proc_dir_entry proc_scsi_wd33c93;
 320 #endif
 321 
 322 #endif /* WD33C93_H */

/* */