arch/sparc/kernel/trampoline.S

/* */
   1 /* $Id: trampoline.S,v 1.3 1996/04/03 02:15:05 davem Exp $
   2  * mp.S:  Multiprocessor low-level routines on the Sparc.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #include <asm/cprefix.h>
   8 #include <asm/head.h>
   9 #include <asm/psr.h>
  10 #include <asm/asi.h>
  11 #include <asm/ptrace.h>
  12 #include <asm/vaddrs.h>
  13 #include <asm/contregs.h>
  14 
  15 
  16         .text
  17         .align 4
  18 
  19 /* When we start up a cpu for the first time it enters this routine.
  20  * This initializes the chip from whatever state the prom left it
  21  * in and sets PIL in %psr to 15, no irqs.
  22  */
  23 
  24         .globl C_LABEL(sparc_cpu_startup)
  25 C_LABEL(sparc_cpu_startup):
  26 cpu1_startup:
  27         sethi   %hi(C_LABEL(trapbase_cpu1)), %g7
  28         or      %g7, %lo(C_LABEL(trapbase_cpu1)), %g7
  29         sethi   %hi(C_LABEL(cpu1_stack)), %g6
  30         or      %g6, %lo(C_LABEL(cpu1_stack)), %g6
  31         b       1f
  32          nop    
  33 
  34 cpu2_startup:
  35         sethi   %hi(C_LABEL(trapbase_cpu2)), %g7
  36         or      %g7, %lo(C_LABEL(trapbase_cpu2)), %g7
  37         sethi   %hi(C_LABEL(cpu2_stack)), %g6
  38         or      %g6, %lo(C_LABEL(cpu2_stack)), %g6
  39         b       1f
  40          nop    
  41 
  42 cpu3_startup:
  43         sethi   %hi(C_LABEL(trapbase_cpu3)), %g7
  44         or      %g7, %lo(C_LABEL(trapbase_cpu3)), %g7
  45         sethi   %hi(C_LABEL(cpu3_stack)), %g6
  46         or      %g6, %lo(C_LABEL(cpu3_stack)), %g6
  47         b       1f
  48          nop    
  49 
  50 1:
  51         /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
  52         set     (PSR_PIL | PSR_S | PSR_PS), %g1
  53         wr      %g1, 0x0, %psr          ! traps off though
  54         WRITE_PAUSE
  55 
  56         /* Our %wim is one behind CWP */
  57         mov     2, %g1
  58         wr      %g1, 0x0, %wim
  59         WRITE_PAUSE
  60 
  61         /* This identifies "this cpu". */
  62         wr      %g7, 0x0, %tbr
  63         WRITE_PAUSE
  64 
  65         /* Give ourselves a stack. */
  66         set     0x2000, %g5
  67         add     %g6, %g5, %g6           ! end of stack
  68         sub     %g6, REGWIN_SZ, %sp
  69         mov     0, %fp
  70 
  71         /* Turn on traps (PSR_ET). */
  72         rd      %psr, %g1
  73         wr      %g1, PSR_ET, %psr       ! traps on
  74         WRITE_PAUSE
  75 
  76         /* Init our caches, etc. */
  77         set     C_LABEL(poke_srmmu), %g5
  78         ld      [%g5], %g5
  79         call    %g5
  80          nop
  81 
  82         /* Start this processor. */
  83         call    C_LABEL(smp_callin)
  84          nop
  85 
  86         call    C_LABEL(cpu_idle)
  87          mov    0, %o0
  88 
  89         call    C_LABEL(cpu_panic)
  90          nop
/* */
root/arch/sparc/kernel/trampoline.S
