1 |
2 | bugfix.sa 3.2 1/31/91
3 |
4 |
5 | This file contains workarounds for bugs in the 040
6 | relating to the Floating-Point Software Package (FPSP)
7 |
8 | Fixes for bugs: 1238
9 |
10 | Bug: 1238
11 |
12 |
13 | /* The following dirty_bit clear should be left in 14 | * the handler permanently to improve throughput. 15 | * The dirty_bits are located at bits [23:16] in 16 | * longword $08 in the busy frame $4x60. Bit 16 17 | * corresponds to FP0, bit 17 corresponds to FP1, 18 | * and so on. 19 | */ 20 | if (E3_exception_just_serviced) { 21 | dirty_bit[cmdreg3b[9:7]] = 0;
22 | } 23 |
24 | if (fsave_format_version != $40) {goto NOFIX} 25 |
26 | if !(E3_exception_just_serviced) {goto NOFIX} 27 | if (cupc == 0000000) {goto NOFIX} 28 | if ((cmdreg1b[15:13] != 000) &&
29 | (cmdreg1b[15:10] != 010001)) {goto NOFIX} 30 | if (((cmdreg1b[15:13] != 000) || ((cmdreg1b[12:10] != cmdreg2b[9:7]) &&
31 | (cmdreg1b[12:10] != cmdreg3b[9:7])) ) &&
32 | ((cmdreg1b[ 9: 7] != cmdreg2b[9:7]) &&
33 | (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) ) {goto NOFIX} 34 |
35 | /* Note: for 6d43b or 8d43b, you may want to add the following code 36 | * to get better coverage. (If you do not insert this code, the part 37 | * won't lock up; it will simply get the wrong answer.) 38 | * Do NOT insert this code for 10d43b or later parts. 39 | * 40 | * if (fpiarcu == integer stack return address) { 41 | * cupc = 0000000; 42 | * goto NOFIX; 43 | * } 44 | */ 45 |
46 | if (cmdreg1b[15:13] != 000) {goto FIX_OPCLASS2} 47 | FIX_OPCLASS0:
48 | if (((cmdreg1b[12:10] == cmdreg2b[9:7]) ||
49 | (cmdreg1b[ 9: 7] == cmdreg2b[9:7])) &&
50 | (cmdreg1b[12:10] != cmdreg3b[9:7]) &&
51 | (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) {/* xu conflict only */ 52 | /* We execute the following code if there is an 53 | xu conflict and NOT an nu conflict */ 54 |
55 | /* first save some values on the fsave frame */ 56 | stag_temp = STAG[fsave_frame];
57 | cmdreg1b_temp = CMDREG1B[fsave_frame];
58 | dtag_temp = DTAG[fsave_frame];
59 | ete15_temp = ETE15[fsave_frame];
60 |
61 | CUPC[fsave_frame] = 0000000;
62 | FRESTORE
63 | FSAVE
64 |
65 | /* If the xu instruction is exceptional, we punt. 66 | * Otherwise, we would have to include OVFL/UNFL handler 67 | * code here to get the correct answer. 68 | */ 69 | if (fsave_frame_format == $4060) {goto KILL_PROCESS} 70 |
71 | fsave_frame = /* build a long frame of all zeros */ 72 | fsave_frame_format = $4060; /* label it as long frame */ 73 |
74 | /* load it with the temps we saved */ 75 | STAG[fsave_frame] = stag_temp;
76 | CMDREG1B[fsave_frame] = cmdreg1b_temp;
77 | DTAG[fsave_frame] = dtag_temp;
78 | ETE15[fsave_frame] = ete15_temp;
79 |
80 | /* Make sure that the cmdreg3b dest reg is not going to 81 | * be destroyed by a FMOVEM at the end of all this code. 82 | * If it is, you should move the current value of the reg 83 | * onto the stack so that the reg will loaded with that value. 84 | */ 85 |
86 | /* All done. Proceed with the code below */ 87 | } 88 |
89 | etemp = FP_reg_[cmdreg1b[12:10]];
90 | ete15 = ~ete14;
91 | cmdreg1b[15:10] = 010010;
92 | clear(bug_flag_procIDxxxx);
93 | FRESTORE and return;
94 |
95 |
96 | FIX_OPCLASS2:
97 | if ((cmdreg1b[9:7] == cmdreg2b[9:7]) &&
98 | (cmdreg1b[9:7] != cmdreg3b[9:7])) {/* xu conflict only */ 99 | /* We execute the following code if there is an 100 | xu conflict and NOT an nu conflict */ 101 |
102 | /* first save some values on the fsave frame */ 103 | stag_temp = STAG[fsave_frame];
104 | cmdreg1b_temp = CMDREG1B[fsave_frame];
105 | dtag_temp = DTAG[fsave_frame];
106 | ete15_temp = ETE15[fsave_frame];
107 | etemp_temp = ETEMP[fsave_frame];
108 |
109 | CUPC[fsave_frame] = 0000000;
110 | FRESTORE
111 | FSAVE
112 |
113 |
114 | /* If the xu instruction is exceptional, we punt. 115 | * Otherwise, we would have to include OVFL/UNFL handler 116 | * code here to get the correct answer. 117 | */ 118 | if (fsave_frame_format == $4060) {goto KILL_PROCESS} 119 |
120 | fsave_frame = /* build a long frame of all zeros */ 121 | fsave_frame_format = $4060; /* label it as long frame */ 122 |
123 | /* load it with the temps we saved */ 124 | STAG[fsave_frame] = stag_temp;
125 | CMDREG1B[fsave_frame] = cmdreg1b_temp;
126 | DTAG[fsave_frame] = dtag_temp;
127 | ETE15[fsave_frame] = ete15_temp;
128 | ETEMP[fsave_frame] = etemp_temp;
129 |
130 | /* Make sure that the cmdreg3b dest reg is not going to 131 | * be destroyed by a FMOVEM at the end of all this code. 132 | * If it is, you should move the current value of the reg 133 | * onto the stack so that the reg will loaded with that value. 134 | */ 135 |
136 | /* All done. Proceed with the code below */ 137 | } 138 |
139 | if (etemp_exponent == min_sgl) etemp_exponent = min_dbl;
140 | if (etemp_exponent == max_sgl) etemp_exponent = max_dbl;
141 | cmdreg1b[15:10] = 010101;
142 | clear(bug_flag_procIDxxxx);
143 | FRESTORE and return;
144 |
145 |
146 | NOFIX:
147 | clear(bug_flag_procIDxxxx);
148 | FRESTORE and return;
149 |
150
151
152 | Copyright (C) Motorola, Inc. 1990
153 | All Rights Reserved
154 |
155 | THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
156 | The copyright notice above does not evidence any
157 | actual or intended publication of such source code.
158
159 |BUGFIX idnt 2,1 | Motorola 040 Floating Point Software Package
160
161 |section 8
162
163 .include "fpsp.h"
164
165 |xref fpsp_fmt_error
166
167 .global b1238_fix
168 b1238_fix:
169 |
170 | This code is entered only on completion of the handling of an
171 | nu-generated ovfl, unfl, or inex exception. If the version
172 | number of the fsave is not $40, this handler is not necessary.
173 | Simply branch to fix_done and exit normally.
174 |
175 cmpib #VER_40,4(%a7)
176 bne fix_done
177 |
178 | Test for cu_savepc equal to zero. If not, this is not a bug
179 | #1238 case.
180 |
181 moveb CU_SAVEPC(%a6),%d0
182 andib #0xFE,%d0
183 beq fix_done |if zero, this is not bug #1238
184
185 |
186 | Test the register conflict aspect. If opclass0, check for
187 | cu src equal to xu dest or equal to nu dest. If so, go to
188 | op0. Else, or if opclass2, check for cu dest equal to
189 | xu dest or equal to nu dest. If so, go to tst_opcl. Else,
190 | exit, it is not the bug case.
191 |
192 | Check for opclass 0. If not, go and check for opclass 2 and sgl.
193 |
194 movew CMDREG1B(%a6),%d0
195 andiw #0xE000,%d0 |strip all but opclass
196 bne op2sgl |not opclass 0, check op2
197 |
198 | Check for cu and nu register conflict. If one exists, this takes
199 | priority over a cu and xu conflict.
200 |
201 bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
202 bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
203 cmpb %d0,%d1
204 beqs op0 |if equal, continue bugfix
205 |
206 | Check for cu dest equal to nu dest. If so, go and fix the
207 | bug condition. Otherwise, exit.
208 |
209 bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
210 cmpb %d0,%d1 |cmp 1st dest with 3rd dest
211 beqs op0 |if equal, continue bugfix
212 |
213 | Check for cu and xu register conflict.
214 |
215 bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
216 cmpb %d0,%d1 |cmp 1st dest with 2nd dest
217 beqs op0_xu |if equal, continue bugfix
218 bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
219 cmpb %d0,%d1 |cmp 1st src with 2nd dest
220 beq op0_xu
221 bne fix_done |if the reg checks fail, exit
222 |
223 | We have the opclass 0 situation.
224 |
225 op0:
226 bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no
227 movel #7,%d1
228 subl %d0,%d1
229 clrl %d0
230 bsetl %d1,%d0
231 fmovemx %d0,ETEMP(%a6) |load source to ETEMP
232
233 moveb #0x12,%d0
234 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended
235 |
236 | Set ETEMP exponent bit 15 as the opposite of ete14
237 |
238 btst #6,ETEMP_EX(%a6) |check etemp exponent bit 14
239 beq setete15
240 bclr #etemp15_bit,STAG(%a6)
241 bra finish
242 setete15:
243 bset #etemp15_bit,STAG(%a6)
244 bra finish
245
246 |
247 | We have the case in which a conflict exists between the cu src or
248 | dest and the dest of the xu. We must clear the instruction in
249 | the cu and restore the state, allowing the instruction in the
250 | xu to complete. Remember, the instruction in the nu
251 | was exceptional, and was completed by the appropriate handler.
252 | If the result of the xu instruction is not exceptional, we can
253 | restore the instruction from the cu to the frame and continue
254 | processing the original exception. If the result is also
255 | exceptional, we choose to kill the process.
256 |
257 | Items saved from the stack:
258 |
259 | $3c stag - L_SCR1
260 | $40 cmdreg1b - L_SCR2
261 | $44 dtag - L_SCR3
262 |
263 | The cu savepc is set to zero, and the frame is restored to the
264 | fpu.
265 |
266 op0_xu:
267 movel STAG(%a6),L_SCR1(%a6)
268 movel CMDREG1B(%a6),L_SCR2(%a6)
269 movel DTAG(%a6),L_SCR3(%a6)
270 andil #0xe0000000,L_SCR3(%a6)
271 moveb #0,CU_SAVEPC(%a6)
272 movel (%a7)+,%d1 |save return address from bsr
273 frestore (%a7)+
274 fsave -(%a7)
275 |
276 | Check if the instruction which just completed was exceptional.
277 |
278 cmpw #0x4060,(%a7)
279 beq op0_xb
280 |
281 | It is necessary to isolate the result of the instruction in the
282 | xu if it is to fp0 - fp3 and write that value to the USER_FPn
283 | locations on the stack. The correct destination register is in
284 | cmdreg2b.
285 |
286 bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no
287 cmpil #3,%d0
288 bgts op0_xi
289 beqs op0_fp3
290 cmpil #1,%d0
291 blts op0_fp0
292 beqs op0_fp1
293 op0_fp2:
294 fmovemx %fp2-%fp2,USER_FP2(%a6)
295 bras op0_xi
296 op0_fp1:
297 fmovemx %fp1-%fp1,USER_FP1(%a6)
298 bras op0_xi
299 op0_fp0:
300 fmovemx %fp0-%fp0,USER_FP0(%a6)
301 bras op0_xi
302 op0_fp3:
303 fmovemx %fp3-%fp3,USER_FP3(%a6)
304 |
305 | The frame returned is idle. We must build a busy frame to hold
306 | the cu state information and setup etemp.
307 |
308 op0_xi:
309 movel #22,%d0 |clear 23 lwords
310 clrl (%a7)
311 op0_loop:
312 clrl -(%a7)
313 dbf %d0,op0_loop
314 movel #0x40600000,-(%a7)
315 movel L_SCR1(%a6),STAG(%a6)
316 movel L_SCR2(%a6),CMDREG1B(%a6)
317 movel L_SCR3(%a6),DTAG(%a6)
318 moveb #0x6,CU_SAVEPC(%a6)
319 movel %d1,-(%a7) |return bsr return address
320 bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no
321 movel #7,%d1
322 subl %d0,%d1
323 clrl %d0
324 bsetl %d1,%d0
325 fmovemx %d0,ETEMP(%a6) |load source to ETEMP
326
327 moveb #0x12,%d0
328 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended
329 |
330 | Set ETEMP exponent bit 15 as the opposite of ete14
331 |
332 btst #6,ETEMP_EX(%a6) |check etemp exponent bit 14
333 beq op0_sete15
334 bclr #etemp15_bit,STAG(%a6)
335 bra finish
336 op0_sete15:
337 bset #etemp15_bit,STAG(%a6)
338 bra finish
339
340 |
341 | The frame returned is busy. It is not possible to reconstruct
342 | the code sequence to allow completion. We will jump to
343 | fpsp_fmt_error and allow the kernel to kill the process.
344 |
345 op0_xb:
346 jmp fpsp_fmt_error
347
348 |
349 | Check for opclass 2 and single size. If not both, exit.
350 |
351 op2sgl:
352 movew CMDREG1B(%a6),%d0
353 andiw #0xFC00,%d0 |strip all but opclass and size
354 cmpiw #0x4400,%d0 |test for opclass 2 and size=sgl
355 bne fix_done |if not, it is not bug 1238
356 |
357 | Check for cu dest equal to nu dest or equal to xu dest, with
358 | a cu and nu conflict taking priority an nu conflict. If either,
359 | go and fix the bug condition. Otherwise, exit.
360 |
361 bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
362 bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
363 cmpb %d0,%d1 |cmp 1st dest with 3rd dest
364 beq op2_com |if equal, continue bugfix
365 bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
366 cmpb %d0,%d1 |cmp 1st dest with 2nd dest
367 bne fix_done |if the reg checks fail, exit
368 |
369 | We have the case in which a conflict exists between the cu src or
370 | dest and the dest of the xu. We must clear the instruction in
371 | the cu and restore the state, allowing the instruction in the
372 | xu to complete. Remember, the instruction in the nu
373 | was exceptional, and was completed by the appropriate handler.
374 | If the result of the xu instruction is not exceptional, we can
375 | restore the instruction from the cu to the frame and continue
376 | processing the original exception. If the result is also
377 | exceptional, we choose to kill the process.
378 |
379 | Items saved from the stack:
380 |
381 | $3c stag - L_SCR1
382 | $40 cmdreg1b - L_SCR2
383 | $44 dtag - L_SCR3
384 | etemp - FP_SCR2
385 |
386 | The cu savepc is set to zero, and the frame is restored to the
387 | fpu.
388 |
389 op2_xu:
390 movel STAG(%a6),L_SCR1(%a6)
391 movel CMDREG1B(%a6),L_SCR2(%a6)
392 movel DTAG(%a6),L_SCR3(%a6)
393 andil #0xe0000000,L_SCR3(%a6)
394 moveb #0,CU_SAVEPC(%a6)
395 movel ETEMP(%a6),FP_SCR2(%a6)
396 movel ETEMP_HI(%a6),FP_SCR2+4(%a6)
397 movel ETEMP_LO(%a6),FP_SCR2+8(%a6)
398 movel (%a7)+,%d1 |save return address from bsr
399 frestore (%a7)+
400 fsave -(%a7)
401 |
402 | Check if the instruction which just completed was exceptional.
403 |
404 cmpw #0x4060,(%a7)
405 beq op2_xb
406 |
407 | It is necessary to isolate the result of the instruction in the
408 | xu if it is to fp0 - fp3 and write that value to the USER_FPn
409 | locations on the stack. The correct destination register is in
410 | cmdreg2b.
411 |
412 bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no
413 cmpil #3,%d0
414 bgts op2_xi
415 beqs op2_fp3
416 cmpil #1,%d0
417 blts op2_fp0
418 beqs op2_fp1
419 op2_fp2:
420 fmovemx %fp2-%fp2,USER_FP2(%a6)
421 bras op2_xi
422 op2_fp1:
423 fmovemx %fp1-%fp1,USER_FP1(%a6)
424 bras op2_xi
425 op2_fp0:
426 fmovemx %fp0-%fp0,USER_FP0(%a6)
427 bras op2_xi
428 op2_fp3:
429 fmovemx %fp3-%fp3,USER_FP3(%a6)
430 |
431 | The frame returned is idle. We must build a busy frame to hold
432 | the cu state information and fix up etemp.
433 |
434 op2_xi:
435 movel #22,%d0 |clear 23 lwords
436 clrl (%a7)
437 op2_loop:
438 clrl -(%a7)
439 dbf %d0,op2_loop
440 movel #0x40600000,-(%a7)
441 movel L_SCR1(%a6),STAG(%a6)
442 movel L_SCR2(%a6),CMDREG1B(%a6)
443 movel L_SCR3(%a6),DTAG(%a6)
444 moveb #0x6,CU_SAVEPC(%a6)
445 movel FP_SCR2(%a6),ETEMP(%a6)
446 movel FP_SCR2+4(%a6),ETEMP_HI(%a6)
447 movel FP_SCR2+8(%a6),ETEMP_LO(%a6)
448 movel %d1,-(%a7)
449 bra op2_com
450
451 |
452 | We have the opclass 2 single source situation.
453 |
454 op2_com:
455 moveb #0x15,%d0
456 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, double
457
458 cmpw #0x407F,ETEMP_EX(%a6) |single +max
459 bnes case2
460 movew #0x43FF,ETEMP_EX(%a6) |to double +max
461 bra finish
462 case2:
463 cmpw #0xC07F,ETEMP_EX(%a6) |single -max
464 bnes case3
465 movew #0xC3FF,ETEMP_EX(%a6) |to double -max
466 bra finish
467 case3:
468 cmpw #0x3F80,ETEMP_EX(%a6) |single +min
469 bnes case4
470 movew #0x3C00,ETEMP_EX(%a6) |to double +min
471 bra finish
472 case4:
473 cmpw #0xBF80,ETEMP_EX(%a6) |single -min
474 bne fix_done
475 movew #0xBC00,ETEMP_EX(%a6) |to double -min
476 bra finish
477 |
478 | The frame returned is busy. It is not possible to reconstruct
479 | the code sequence to allow completion. fpsp_fmt_error causes
480 | an fline illegal instruction to be executed.
481 |
482 | You should replace the jump to fpsp_fmt_error with a jump
483 | to the entry point used to kill a process.
484 |
485 op2_xb:
486 jmp fpsp_fmt_error
487
488 |
489 | Enter here if the case is not of the situations affected by
490 | bug #1238, or if the fix is completed, and exit.
491 |
492 finish:
493 fix_done:
494 rts
495
496 |end
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