taglinefilesource code
mii_wr620drivers/net/de4x5.cstatic void    mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
mii_wr2243drivers/net/de4x5.cmii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr2261drivers/net/de4x5.cmii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr2403drivers/net/de4x5.cmii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
mii_wr3458drivers/net/de4x5.cmii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
mii_wr745drivers/net/de4x5.hmii_wr(MII_CR_10|(de4x5_full_duplex?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
mii_wr762drivers/net/de4x5.hmii_wr(mii_rd(0x18, lp->phy[lp->active].addr, DE4X5_MII) & ~0x2000,\
mii_wr769drivers/net/de4x5.hmii_wr(MII_CR_100|(fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
mii_wr784drivers/net/de4x5.hmii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\