root/arch/ppc/kernel/ppc_machine.h.isin.processor.h

/* */

   1 /*
   2  * PowerPC machine specifics
   3  */
   4 
   5 #ifndef _PPC_MACHINE_H_
   6 #define _PPC_MACHINE_H_ 
   7 
   8 /* Bit encodings for Machine State Register (MSR) */
   9 #define MSR_POW         (1<<18)         /* Enable Power Management */
  10 #define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
  11 #define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
  12 #define MSR_EE          (1<<15)         /* External Interrupt enable */
  13 #define MSR_PR          (1<<14)         /* Supervisor/User privilege */
  14 #define MSR_FP          (1<<13)         /* Floating Point enable */
  15 #define MSR_ME          (1<<12)         /* Machine Check enable */
  16 #define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
  17 #define MSR_SE          (1<<10)         /* Single Step */
  18 #define MSR_BE          (1<<9)          /* Branch Trace */
  19 #define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
  20 #define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
  21 #define MSR_IR          (1<<5)          /* Instruction MMU enable */
  22 #define MSR_DR          (1<<4)          /* Data MMU enable */
  23 #define MSR_RI          (1<<1)          /* Recoverable Exception */
  24 #define MSR_LE          (1<<0)          /* Little-Endian enable */
  25 
  26 #define MSR_            MSR_FP|MSR_FE0|MSR_FE1|MSR_ME
  27 #define MSR_USER        MSR_|MSR_PR|MSR_EE|MSR_IR|MSR_DR
  28 
  29 /* Bit encodings for Hardware Implementation Register (HID0) */
  30 #define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
  31 #define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
  32 #define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
  33 #define HID0_SBCLK      (1<<27)
  34 #define HID0_EICE       (1<<26)
  35 #define HID0_ECLK       (1<<25)
  36 #define HID0_PAR        (1<<24)
  37 #define HID0_DOZE       (1<<23)
  38 #define HID0_NAP        (1<<22)
  39 #define HID0_SLEEP      (1<<21)
  40 #define HID0_DPM        (1<<20)
  41 #define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
  42 #define HID0_DCE        (1<<14)         /* Data Cache Enable */
  43 #define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
  44 #define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
  45 #define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
  46 #define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
  47  
  48 #endif

/* */