root/arch/mips/kernel/head.S

/* */

   1 /*
   2  *  mips/head.S
   3  *
   4  *  Copyright (C) 1994 Waldorf Electronics
   5  *  Written by Ralf Baechle and Andreas Busse
   6  *
   7  *  Head.S contains the MIPS exception handler and startup code.
   8  */
   9 
  10 #undef DEBUGPICA /* undef this if you have a different system */
  11 
  12 #include <linux/tasks.h>
  13 
  14 #include <asm/segment.h>
  15 #include <asm/cachectl.h>
  16 #include <asm/mipsregs.h>
  17 #include <asm/mipsconfig.h>
  18 #include <asm/stackframe.h>
  19 #include <asm/regdef.h>
  20 #include <asm/bootinfo.h>
  21 #include <asm/segment.h>
  22 
  23 #define PAGE_SIZE       0x1000
  24 
  25 /*
  26  * For now we can't enable write caching. This would cause trouble
  27  * with the page aliases used by the memory management.
  28  * The page table's aliases even have to be uncachable, but that
  29  * doesn't hurt much anyway.
  30  */
  31 #define PAGE_TABLE      0x0580  /* uncachable */
  32 #define PAGE_SHARED     0x0580  /* cachable, writethrough, no write allocate */
  33 #define MODE_ALIAS      0x0016  /* uncachable */
  34 
  35                 .globl  _empty_bad_page
  36                 .globl  _empty_bad_page_table
  37                 .globl  _pg0
  38                 .globl  _empty_zero_page
  39                 .globl  _tmp_floppy_area
  40                 .globl  _floppy_track_buffer
  41                 .globl  _swapper_pg_dir
  42 
  43                 .text
  44                 .globl  _kernelbase
  45 _kernelbase:
  46 
  47 /*
  48  * This is space for the interrupt handlers.
  49  * They are located at virtual address KSEG[01] (physical 0x0)
  50  */
  51                 /*
  52                  * TLB refill, EXL == 0
  53                  */
  54                 .set    noreorder
  55                 .set    noat
  56 except_vec0:
  57 #if KERNELBASE == KSEG1
  58                 la      k0,1f
  59                 jr      k0
  60                 nop
  61 1:
  62 #endif
  63                 dmfc0   k1,CP0_CONTEXT
  64                 dsra    k1,k1,1
  65                 lwu     k0,(k1)                 # May cause another exception
  66                 lwu     k1,4(k1)
  67                 dsrl    k0,k0,6                 # Convert to EntryLo format
  68                 dsrl    k1,k1,6                 # Convert to EntryLo format
  69                 dmtc0   k0,CP0_ENTRYLO0
  70                 dmtc0   k1,CP0_ENTRYLO1
  71                 tlbwr
  72                 eret
  73 
  74                 /*
  75                  * XTLB refill, EXL == 0
  76                  * Should never be reached
  77                  */
  78                 .org    except_vec0+0x80
  79 except_vec1:    
  80 #if KERNELBASE == KSEG1
  81                 la      k0,1f
  82                 jr      k0
  83                 nop
  84 1:
  85 #endif
  86                 la      a0,xtlb_text
  87                 jal     _panic
  88                 nop
  89 1:              j       1b
  90                 nop
  91 xtlb_text:      .asciz  "XTLB Refill exception.\n"
  92 
  93                 /*
  94                  * Cache Error
  95                  */
  96                 .org    except_vec1+0x80
  97 except_vec2:
  98 #if KERNELBASE == KSEG1
  99                 la      k0,1f
 100                 jr      k0
 101                 nop
 102 1:
 103 #endif
 104                 /*
 105                  * Should never be reached
 106                  */
 107                 la      a0,xtlb_text
 108                 jal     _panic
 109                 nop
 110 1:              j       1b
 111                 nop
 112 cache_text:     .asciz  "Cache error exception\n"
 113 
 114                 /*
 115                  * General exception vector.
 116                  */
 117                 .org    except_vec2+0x80
 118 except_vec3:    /*
 119                  * Register saving is delayed as long as we don't know
 120                  * which registers really need to be saved.
 121                  */
 122 #if KERNELBASE == KSEG1
 123                 la      k0,1f
 124                 jr      k0
 125                 nop
 126 1:
 127 #endif
 128                 .set    noat
 129                 mfc0    k1,CP0_CAUSE
 130                 la      k0,_exception_handlers
 131                 /*
 132                  * Next lines assumes that the used CPU type has max.
 133                  * 32 different types of exceptions. We might use this
 134                  * to implement software exceptions in the future.
 135                  */
 136                 andi    k1,k1,0x7c
 137                 addu    k0,k0,k1
 138                 lw      k0,(k0)
 139                 FILL_LDS
 140                 jr      k0
 141                 nop
 142 
 143 /******************************************************************************/
 144 
 145 /*
 146  * Kernel entry
 147  */
 148                 .set    noreorder
 149                 .set    at
 150 kernel_entry:
 151                 jal     refill
 152                 nop
 153 
 154                 /*
 155                  * Clear BSS first so that there are no surprises...
 156                  */
 157                 la      t0,__edata
 158                 la      t1,__end
 159                 sw      zero,(t0)
 160 1:              addiu   t0,t0,4
 161                 bnel    t0,t1,1b
 162                 sw      zero,(t0)
 163 
 164 #ifdef DEBUGPICA
 165                 la      t0,_boot_info
 166                 lw      t0,OFFSET_BOOTINFO_VRAM_BASE(t0)
 167                 li      t1,0x0f00 + '3'
 168                 sh      t1,4(t0)
 169 #endif
 170 
 171                 .set    noreorder
 172                 jal     _tlbflush
 173                 mtc0    zero,CP0_WIRED
 174                 /*
 175                  * Spread some mines...
 176                  */
 177                 la      t0,_end
 178                 la      t1,0x003ffffc
 179                 la      t2,KERNELBASE
 180                 or      t1,t2
 181                 li      t2,0xdeadbeef
 182 1:              sw      t2,(t0)
 183                 bne     t0,t1,1b
 184                 addiu   t0,t0,4
 185                 /*
 186                  * Initialize memory management, map lowest 4MB
 187                  */
 188                 .set    reorder
 189                 jal     setup_paging
 190 #if KERNELBASE == KSEG0
 191                 jal     _sys_cacheflush
 192 #endif
 193 
 194 #ifdef DEBUGPICA
 195                 la      t0,_boot_info
 196                 lw      t0,OFFSET_BOOTINFO_VRAM_BASE(t0)
 197                 li      t1,0x0f00 + '4'
 198                 sh      t1,6(t0)
 199 #endif
 200                 /*
 201                  * Stack for kernel and init
 202                  */
 203                 la      sp,_init_user_stack+PAGE_SIZE-24
 204                 sw      sp,_kernelsp
 205 
 206 1:              jal     _start_kernel
 207                 /*
 208                  * Main should never return here, but
 209                  * just in case, we know what happens.
 210                  */
 211                 j       1b
 212 
 213 /*
 214  * Setup_paging
 215  *
 216  * Wire mappings for page_tables.
 217  * The page tables are set up, identity-mapping
 218  * the first 4MB.  The rest are initialized later.
 219  */
 220                 .set    noreorder
 221 setup_paging:
 222                 /*
 223                  * get base address of map0 table for the
 224                  * the board we're running on
 225                  */
 226                 la      t0,_boot_info
 227                 lw      t1,OFFSET_BOOTINFO_MACHTYPE(t0)
 228                 sll     t1,t1,2                 # machtype used as index
 229                 la      t0,map0table
 230                 addu    t0,t0,t1
 231                 lw      t0,(t0)                 # get base address
 232 
 233                 /*
 234                  * Get number of wired TLB entries and
 235                  * loop over selected map0 table.
 236                  */
 237                 lw      t1,(t0)                 # number of wired TLB entries
 238                 move    t2,zero                 # TLB entry counter
 239                 addiu   t3,t1,1                 # wire one additional entry
 240                 beqz    t1,2f                   # null, exit
 241                 mtc0    t3,CP0_WIRED            # delay slot
 242                 addiu   t0,t0,8
 243 1:              lw      t4,24(t0)               # PageMask
 244                 ld      t5,0(t0)                # entryHi
 245                 ld      t6,8(t0)                # entryLo0
 246                 ld      t7,16(t0)               # entryLo1
 247                 addiu   t2,t2,1                 # increment ctr
 248                 mtc0    t2,CP0_INDEX            # set TLB entry
 249                 mtc0    t4,CP0_PAGEMASK
 250                 dmtc0   t5,CP0_ENTRYHI
 251                 dmtc0   t6,CP0_ENTRYLO0
 252                 dmtc0   t7,CP0_ENTRYLO1
 253                 tlbwi 
 254                 bne     t1,t2,1b                # next TLB entry
 255                 addiu   t0,t0,32                # delay slot
 256 
 257                 /*
 258                  * We use only 4k pages. Therefore the PageMask register
 259                  * is expected to be setup for 4k pages.
 260                  */
 261 2:              li      t0,PM_4K
 262                 mtc0    t0,CP0_PAGEMASK
 263 
 264                 la      t1,_swapper_pg_dir      # swapper_pg_dir is at 0x1000
 265                 la      t2,_swapper_pg_dir+(PAGE_SIZE-4)
 266 1:              sw      zero,(t1)
 267                 bne     t1,t2,1b
 268                 addiu   t1,t1,4                 # delay slot
 269 
 270                 /*
 271                  * Setup invalid_pg_table and
 272                  * clear page table for the first 4MB
 273                  */
 274                 la      t0,_pg0                 # swapper_pg_dir is at 0x1000
 275                 la      t1,_pg0+PAGE_SIZE
 276                 li      t2,KERNELBASE
 277                 addu    t0,t2
 278                 addu    t1,t2
 279 1:              sw      zero,(t0)
 280                 addiu   t0,t0,4
 281                 bne     t0,t1,1b
 282                 addiu   t2,t2,4                 # delay slot
 283 
 284                 /*
 285                  * Identity-map the kernel in low 4MB memory for ease
 286                  * of transition. Unlike the Intel version the kernel
 287                  * code/data is automagically being mapped by kseg0.
 288                  */
 289                 la      t0,_pg0+PAGE_TABLE      # set valid bit/user r/w
 290                 sw      t0,_swapper_pg_dir
 291 
 292                 li      t0,PAGE_SHARED          # set valid bit/user r/w
 293                 la      t1,_pg0
 294                 la      t2,_pg0+PAGE_SIZE
 295                 li      t3,KERNELBASE
 296                 addu    t1,t3
 297                 addu    t2,t3
 298 1:              sw      t0,(t1)
 299                 addiu   t1,t1,4
 300                 bne     t1,t2,1b
 301                 addiu   t0,t0,PAGE_SIZE         # delay slot
 302 
 303                 /*
 304                  * Now map the pagetables
 305                  */
 306                 mtc0    zero,CP0_INDEX
 307                 la      t0,TLB_ROOT
 308                 dmtc0   t0,CP0_ENTRYHI
 309                 li      t0,_swapper_pg_dir
 310                 srl     t0,t0,6
 311                 ori     t0,t0,MODE_ALIAS        # uncachable, dirty, valid
 312                 dmtc0   t0,CP0_ENTRYLO0
 313                 dmtc0   zero,CP0_ENTRYLO1
 314                 tlbwi
 315                 /*
 316                  * Make page zero unaccessible to catch zero references
 317                  */
 318                 li      t0,KERNELBASE
 319                 addiu   t0,_pg0
 320                 sw      zero,(t0)
 321                 /*
 322                  * Load the context register with a value that allows
 323                  * it to be used as fast as possible in tlb exceptions.
 324                  * It is expected that this register's content never
 325                  * will be changed.
 326                  */
 327                 li      t0,TLBMAP
 328                 dsll    t0,t0,1
 329                 jr      ra
 330                 dmtc0   t0,CP0_CONTEXT          # delay slot
 331 
 332                 /*
 333                  * Flush the TLB
 334                  *
 335                  * FIXME: knows only how to handle R4x00
 336                  * Read appendix f of the R4000 manual before you change
 337                  * something!
 338                  */
 339                 .globl  _tlbflush
 340 _tlbflush:      li      t0,PM_4K
 341                 mtc0    t0,CP0_PAGEMASK
 342                 lw      t0,_boot_info+OFFSET_BOOTINFO_TLB_ENTRIES(t0)
 343                 dmtc0   zero,CP0_ENTRYLO0
 344                 dmtc0   zero,CP0_ENTRYLO1
 345                 mfc0    t2,CP0_WIRED
 346 1:              subu    t0,t0,1
 347                 mtc0    t0,CP0_INDEX
 348                 lui     t1,0x0008
 349                 or      t1,t0,t1
 350                 dsll    t1,t1,13
 351                 dmtc0   t1,CP0_ENTRYHI
 352                 bne     t2,t0,1b
 353                 tlbwi                                   # delay slot
 354                 jr      ra
 355                 nop
 356 
 357 /*
 358  * Refill icache
 359  */
 360 #include <asm/mipsconfig.h>
 361 #include <asm/regdef.h>
 362 #include <asm/segment.h>
 363 
 364 #define PAGE_SIZE       0x1000
 365 
 366 #define CACHELINES      512             /* number of cachelines    */
 367 
 368                 .set    noreorder
 369                 .text
 370 refill:
 371                 /*
 372                  * Refill icache with cache fill command
 373                  */
 374                 li      t0,KSEG0
 375                 li      t1,CACHELINES
 376 1:              cache   21,0(t0)
 377                 cache   21,32(t0)
 378                 cache   21,64(t0)
 379                 cache   21,96(t0)
 380                 cache   21,128(t0)
 381                 cache   21,160(t0)
 382                 cache   21,192(t0)
 383                 cache   21,224(t0)
 384                 cache   21,256(t0)
 385                 cache   21,288(t0)
 386                 cache   21,320(t0)
 387                 cache   21,352(t0)
 388                 cache   21,384(t0)
 389                 cache   21,416(t0)
 390                 cache   21,448(t0)
 391                 cache   21,480(t0)
 392                 subu    t1,t1,1
 393                 bnez    t1,1b
 394                 addiu   t0,t0,512                       # delay slot
 395 
 396                 jr      ra
 397                 nop
 398 
 399 /*
 400  * Just for debugging...
 401  */
 402                 .globl  _beep
 403 _beep:          lw      t0,beepflag
 404                 nop
 405                 bnez    t0,1f
 406                 lbu     t0,0xe0000061
 407                 xori    t0,t0,3
 408                 sb      t0,0xe0000061
 409                 li      t0,1
 410                 sw      t0,beepflag
 411 1:              jr      ra
 412                 nop
 413 
 414 /*
 415  * Compute kernel code checksum to check kernel code against corruption
 416  */
 417                 .globl  _csum
 418 #if 0
 419 _csum:          jal     _sys_cacheflush
 420                 move    t8,ra                   # delay slot
 421 #else
 422 _csum:          move    t8,ra
 423 #endif
 424                 li      t0,KSEG1
 425                 la      t1,final
 426                 li      t2,KSEG1
 427                 or      t0,t2
 428                 or      t1,t2
 429                 move    v0,zero
 430 1:              lw      t2,(t0)
 431                 addiu   t0,t0,4
 432                 bne     t0,t1,1b
 433                 xor     v0,v0,t2
 434                 jr      t8
 435                 nop
 436 final:
 437 
 438                 .data
 439 /*
 440  * Instead of Intel's strage and unportable segment descriptor magic
 441  * we difference user and kernel space by their address.
 442  * Kernel space (== physical memory) is mapped at KSEG[01],
 443  * User space is mapped at 0x0.
 444  */
 445                 .globl  _segment_fs
 446 _segment_fs:    .word   KERNEL_DS
 447 
 448 /*
 449  * Inital mapping tables for supported Mips boards.
 450  * First item is always the number of wired TLB entries,
 451  * following by EntryHi/EntryLo pairs and page mask.
 452  * Since everything must be quad-aligned (8) we insert
 453  * some dummy zeros.
 454  */
 455 
 456 /*
 457  * Address table of mapping tables for supported Mips boards.
 458  * Add your own stuff here but don't forget to define your
 459  * target system in bootinfo.h
 460  */
 461 
 462 map0table:      .word   map0_dummy              # machtype = unknown
 463                 .word   map0_tyne               # Deskstation Tyne
 464                 .word   map0_pica61             # Acer Pica-61
 465 
 466 map0_dummy:     .word   0                       # 0 entries
 467 
 468 /*
 469  * Initial mappings for Deskstation Tyne boards.
 470  */
 471                 .align  8
 472 
 473 map0_tyne:      .word   3                       # no. of wired TLB entries
 474                 .word   0                       # pad for alignment
 475 
 476 # TLB entry 1: ISA I/O
 477 
 478                 .quad   0xffffffffe0000000      # TLB #0 EntryHi
 479                 .quad   0x24000017              # TLB #0 EntryLo0
 480                 .quad   0                       # TLB #0 EntryLo1
 481                 .word   PM_64K                  # page mask
 482                 .word   0                       # pad for alignment
 483 
 484 # TLB entry 2: ISA memory space
 485 
 486                 .quad   0xffffffffe1000000      # TLB #1 EntryHi
 487                 .quad   0x04000017              # TLB #1 EntryLo0
 488                 .quad   0                       # TLB #1 EntryLo1
 489                 .word   PM_1M
 490                 .word   0                       # pad for alignment
 491 
 492 # TLB entry 3: ISA DMA cache
 493 
 494                 .quad   0xffffffffe2000000      # TLB #2 EntryHi
 495                 .quad   0x04020017              # TLB #2 EntryLo0
 496                 .quad   0                       # TLB #2 EntryLo1
 497                 .word   PM_1M
 498                 .word   0                       # pad for alignment
 499 
 500 /*
 501  * Initial mapping for ACER PICA-61 boards.
 502  * FIXME: These are rather preliminary since many drivers,
 503  * such as serial, parallel, scsi and ethernet need some
 504  * changes to distuingish between "local" (built-in) and
 505  * "optional" (ISA/PCI) I/O hardware.
 506  * Local video ram is mapped to the same location as the
 507  * bios maps it to. Console driver has been changed
 508  * accordingly (new video type: VIDEO_TYPE_PICA_S3).
 509  */
 510 
 511 map0_pica61:    .word   9                       # no. wired TLB entries
 512                 .word   0                       # dummy
 513 
 514 # TLB entry 1: PROM
 515 
 516 #               .quad   0xffffffffe1000000      # BIOS mapping
 517                 .quad   0xffffffffe4000000      # new mapping
 518                 .quad   0x03ffc013
 519                 .quad   0x00000001              # global, not valid
 520                 .word   PM_256K
 521                 .word   0
 522 
 523 # TLB entry 2: local I/O space
 524 
 525                 .quad   0xffffffffe0000000
 526                 .quad   0x02000017
 527                 .quad   0x00000001              # global, not valid
 528                 .word   PM_64K
 529                 .word   0
 530 
 531 # TLB entry 3: DRAM config register
 532 
 533                 .quad   0xffffffffe00e0000
 534                 .quad   0x02003817
 535                 .quad   0x02003c17
 536                 .word   PM_64K
 537                 .word   0
 538 
 539 # TLB entry 4: Interrupt source register
 540 
 541                 .quad   0xffffffffe0100000
 542                 .quad   0x03c00017
 543                 .quad   0x00000001              # global, not valid
 544                 .word   PM_4K
 545                 .word   0
 546 
 547 # TLB entry 5: Local video control
 548 
 549                 .quad   0xffffffffe0200000
 550                 .quad   0x01800017
 551                 .quad   0x01804017
 552                 .word   PM_1M
 553                 .word   0
 554 
 555 # TLB entry 6: Extended video control
 556 
 557                 .quad   0xffffffffe0400000
 558                 .quad   0x01808017
 559                 .quad   0x0180c017
 560                 .word   PM_1M
 561                 .word   0
 562 
 563 # TLB entry 7: Local video memory (BIOS mapping)
 564 
 565                 .quad   0xffffffffe0800000
 566                 .quad   0x01000017
 567                 .quad   0x01010017
 568                 .word   PM_4M
 569                 .word   0
 570 
 571 # TLB entry 8: Local video memory (mapped to where Linux expects it)
 572 # not needed anymore
 573 #               .quad   0xffffffffe1000000
 574 #               .quad   0x01000017
 575 #               .quad   0x01010017
 576 #               .word   PM_4M
 577 #               .word   0
 578 
 579 # TLB entry 9: ISA I/O and ISA memory space (both 16M)
 580 
 581                 .quad   0xffffffffe2000000
 582                 .quad   0x02400017
 583                 .quad   0x02440017
 584                 .word   PM_16M
 585                 .word   0
 586 
 587 # TLB entry 10: PCR (???)
 588 
 589                 .quad   0xffffffffffffe000
 590                 .quad   0x00000001              # nonsense...
 591                 .quad   0x0001ffd7
 592                 .word   PM_4K
 593                 .word   0
 594 
 595 
 596 /* ------------------------------------------------
 597  * Mapping as presented by the PICA BIOS.
 598  * This table works. Please leave unmodified!
 599  * ------------------------------------------------ */
 600 #if 0
 601 map0_pica61:    .word   11                      # no. wired TLB entries
 602                 .word   0                       # dummy
 603 
 604 # TLB entry 0: Don't know what this is good for...
 605 
 606                 .quad   0xfffffffffffe2000
 607                 .quad   0x0000029e
 608                 .quad   0x00000000
 609                 .word   PM_4K
 610                 .word   0
 611 
 612 # TLB entry 1: PROM
 613 
 614                 .quad   0xffffffffe1000000
 615                 .quad   0x03ffc013
 616                 .quad   0x00000001              # nonsense ...
 617                 .word   PM_256K
 618                 .word   0
 619 
 620 # TLB entry 2: local I/O space
 621 
 622                 .quad   0xffffffffe0000000
 623                 .quad   0x02000017
 624                 .quad   0x00000001              # nonsense ...
 625                 .word   PM_64K
 626                 .word   0
 627 
 628 # TLB entry 3: DRAM config register
 629 
 630                 .quad   0xffffffffe00e0000
 631                 .quad   0x02003817
 632                 .quad   0x02003c17
 633                 .word   PM_64K
 634                 .word   0
 635 
 636 # TLB entry 4: Interrupt source register
 637 
 638                 .quad   0xffffffffe0100000
 639                 .quad   0x03c00017
 640                 .quad   0x00000001              # nonsense ...
 641                 .word   PM_4K
 642                 .word   0
 643 
 644 # TLB entry 5: Local video control
 645 
 646                 .quad   0xffffffffe0200000
 647                 .quad   0x01800017
 648                 .quad   0x01804017
 649                 .word   PM_1M
 650                 .word   0
 651 
 652 # TLB entry 6: Extended video control
 653 
 654                 .quad   0xffffffffe0400000
 655                 .quad   0x01808017
 656                 .quad   0x0180c017
 657                 .word   PM_1M
 658                 .word   0
 659 
 660 # TLB entry 7: Local video memory
 661 
 662                 .quad   0xffffffffe0800000
 663                 .quad   0x01000017
 664                 .quad   0x01010017
 665                 .word   PM_4M
 666                 .word   0
 667 
 668 # TLB entry 8: ISA I/O space
 669 
 670                 .quad   0xffffffffe2000000
 671                 .quad   0x02400017
 672                 .quad   0x02440017
 673                 .word   PM_16M
 674                 .word   0
 675 
 676 # TLB entry 9: PCR (???)
 677 
 678                 .quad   0xffffffffffffe000
 679                 .quad   0x00000001              # nonsense...
 680                 .quad   0x0001ffd7
 681                 .word   PM_4K
 682                 .word   0
 683 
 684 # TLB entry 10: Extended video prom
 685 
 686                 .quad   0xffffffff10000000
 687                 .quad   0x0000141f
 688                 .quad   0x00000001              # nonsense
 689                 .word   PM_64K
 690                 .word   0
 691 #endif
 692 
 693 /*
 694  * page 0 is made non-existent, so that kernel NULL pointer references get
 695  * caught. Thus the swapper page directory has been moved to 0x1000
 696  *
 697  * XXX Actually, the swapper page directory is at 0x1000 plus 1 megabyte,
 698  * with the introduction of the compressed boot code.  Theoretically,
 699  * the original design of overlaying the startup code with the swapper
 700  * page directory is still possible --- it would reduce the size of the kernel
 701  * by 2-3k.  This would be a good thing to do at some point.....
 702  */
 703                         .text
 704 
 705                         .org    0x1000
 706 _swapper_pg_dir         =       0x1000
 707 /*
 708  * The page tables are initialized to only 4MB here - the final page
 709  * tables are set up later depending on memory size.
 710  */
 711                         .org    0x2000
 712 _pg0                    =       0x2000
 713 
 714                         .org    0x3000
 715 _empty_bad_page         =       0x3000
 716 
 717                         .org    0x4000
 718 _empty_bad_page_table   =       0x4000
 719 
 720                         .org    0x5000
 721 _empty_zero_page        =       0x5000
 722 
 723                         .org    0x6000
 724 
 725 /*
 726  * tmp_floppy_area is used by the floppy-driver when DMA cannot
 727  * reach to a buffer-block. It needs to be aligned, so that it isn't
 728  * on a 64kB border.
 729  */
 730 _tmp_floppy_area:       .fill   1024,1,0
 731 /*
 732  * floppy_track_buffer is used to buffer one track of floppy data: it
 733  * has to be separate from the tmp_floppy area, as otherwise a single-
 734  * sector read/write can mess it up. It can contain one full cylinder (sic) of
 735  * data (36*2*512 bytes).
 736  */
 737 _floppy_track_buffer:   .fill   512*2*36,1,0
 738                         .globl  _kernelsp
 739 _kernelsp:              .word   0
 740 beepflag:               .word   0

/* */