include/linux/serial.h

/* */
   1 /*
   2  * include/linux/serial.h
   3  *
   4  * Copyright (C) 1992 by Theodore Ts'o.
   5  * 
   6  * Redistribution of this file is permitted under the terms of the GNU 
   7  * Public License (GPL)
   8  */
   9 
  10 /*
  11  * This is our internal structure for each serial port's state.
  12  * 
  13  * Many fields are paralleled by the structure used by the serial_struct
  14  * structure.
  15  *
  16  * For definitions of the flags field, see tty.h
  17  */
  18 #ifndef _LINUX_SERIAL_H
  19 #define _LINUX_SERIAL_H
  20 
  21 struct async_struct {
  22         int                     baud_base;
  23         int                     port;
  24         int                     irq;
  25         int                     flags;          /* defined in tty.h */
  26         int                     hub6;           /* HUB6 plus one */
  27         int                     type;           /* UART type */
  28         struct tty_struct       *tty;
  29         int                     read_status_mask;
  30         int                     timeout;
  31         int                     xmit_fifo_size;
  32         int                     custom_divisor;
  33         int                     x_char; /* xon/xoff characater */
  34         int                     close_delay;
  35         int                     IER;    /* Interrupt Enable Register */
  36         int                     event;
  37         int                     line;
  38         int                     count;      /* # of fd on device */
  39         int                     blocked_open; /* # of blocked opens */
  40         long                    session; /* Session of opening process */
  41         long                    pgrp; /* pgrp of opening process */
  42         struct wait_queue       *open_wait;
  43         struct async_struct     *next_port; /* For the linked list */
  44         struct async_struct     *prev_port;
  45 };
  46 
  47 /*
  48  * Events are used to schedule things to happen at timer-interrupt
  49  * time, instead of at rs interrupt time.
  50  */
  51 #define RS_EVENT_READ_PROCESS   0
  52 #define RS_EVENT_WRITE_WAKEUP   1
  53 #define RS_EVENT_HANGUP         2
  54 #define RS_EVENT_BREAK          3
  55 #define RS_EVENT_OPEN_WAKEUP    4
  56 
  57 /*
  58  * These are the UART port assignments, expressed as offsets from the base
  59  * register.  These assignments should hold for any serial port based on
  60  * a 8250, 16450, or 16550(A).
  61  */
  62 #define UART_RX         0       /* In:  Receive buffer (DLAB=0) */
  63 #define UART_TX         0       /* Out: Transmit buffer (DLAB=0) */
  64 #define UART_DLL        0       /* Out: Devisor Latch Low (DLAB=1) */
  65 #define UART_DLM        1       /* Out: Devisor Latch High (DLAB=1) */
  66 #define UART_IER        1       /* Out: Interrupt Enable Register */
  67 #define UART_IIR        2       /* In:  Interrupt ID Register */
  68 #define UART_FCR        2       /* Out: FIFO Control Register */
  69 #define UART_LCR        3       /* Out: Line Control Register */
  70 #define UART_MCR        4       /* Out: Modem Control Register */
  71 #define UART_LSR        5       /* In:  Line Status Register */
  72 #define UART_MSR        6       /* In:  Modem Status Register */
  73 #define UART_SCR        7       /* I/O: Scratch Register */
  74 
  75 /*
  76  * These are the definitions for the FIFO Control Register
  77  */
  78 #define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
  79 #define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
  80 #define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
  81 #define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
  82 #define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */
  83 #define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */
  84 #define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */
  85 #define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */
  86 #define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */
  87 
  88 #define UART_FCR_CLEAR_CMD      (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)
  89 #define UART_FCR_SETUP_CMD      (UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8)
  90         
  91 /*
  92  * These are the definitions for the Line Control Register
  93  * 
  94  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
  95  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  96  */
  97 #define UART_LCR_DLAB   0x80    /* Devisor latch access bit */
  98 #define UART_LCR_SBC    0x40    /* Set break control */
  99 #define UART_LCR_SPAR   0x20    /* Stick parity (?) */
 100 #define UART_LCR_EPAR   0x10    /* Even paraity select */
 101 #define UART_LCR_PARITY 0x08    /* Parity Enable */
 102 #define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
 103 #define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
 104 #define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
 105 #define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
 106 #define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
 107 
 108 /*
 109  * These are the definitions for the Line Status Register
 110  */
 111 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
 112 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
 113 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
 114 #define UART_LSR_FE     0x08    /* Frame error indicator */
 115 #define UART_LSR_PE     0x04    /* Parity error indicator */
 116 #define UART_LSR_OE     0x02    /* Overrun error indicator */
 117 #define UART_LSR_DR     0x01    /* Receiver data ready */
 118 
 119 /*
 120  * These are the definitions for the Interrupt Indentification Register
 121  */
 122 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
 123 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
 124 
 125 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
 126 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
 127 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
 128 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
 129 
 130 /*
 131  * These are the definitions for the Interrupt Enable Register
 132  */
 133 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
 134 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
 135 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
 136 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
 137 
 138 /*
 139  * These are the definitions for the Modem Control Register
 140  */
 141 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
 142 #define UART_MCR_OUT2   0x08    /* Out2 complement */
 143 #define UART_MCR_OUT1   0x04    /* Out1 complement */
 144 #define UART_MCR_RTS    0x02    /* RTS complement */
 145 #define UART_MCR_DTR    0x01    /* DTR complement */
 146 
 147 /*
 148  * These are the definitions for the Modem Status Register
 149  */
 150 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
 151 #define UART_MSR_RI     0x40    /* Ring Indicator */
 152 #define UART_MSR_DSR    0x20    /* Data Set Ready */
 153 #define UART_MSR_CTS    0x10    /* Clear to Send */
 154 #define UART_MSR_DDCD   0x08    /* Delta DCD */
 155 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
 156 #define UART_MSR_DDSR   0x02    /* Delta DSR */
 157 #define UART_MSR_DCTS   0x01    /* Delta CTS */
 158 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
 159 
 160 #endif /* _LINUX_SERIAL_H */
/* */
root/include/linux/serial.h

INCLUDED FROM
